Forward Bias Stress Research Articles

Suppressed gate leakage and enlarged gate over-drive window of E-mode p-GaN gate double channel HEMTs

A 600-V p-GaN gate double channel HEMT (DC-HEMT) is presented with a systematic investigation of the gate characteristics, including the leakage current, breakdown, and reliability under forward bias stress. It is found that the gate leakage of the DC-HEMT is substantially lower than that of the p-GaN single channel HEMT (SC-HEMT) owing to suppressed electron spillover that stems from hole storage in the quantum well upper channel. Consequently, the gate breakdown voltage of the DC-HEMT is improved to 14.7 V compared to 12.2 V of the SC-HEMT. Besides, the gate operating voltage margin of the DC-HEMT is expanded to 4.2 V compared to 3.3 V of the SC-HEMT according to the gate lifetime evaluation.

Impact of High-Temperature Forward Bias Stress on the Electrical Performance Degradation of β-Ga₂O₃ Schottky Barrier Diodes

Impact of High-Temperature Forward Bias Stress on the Electrical Performance Degradation of β-Ga₂O₃ Schottky Barrier Diodes

Analysis of Forward Bias Degradation Reduction in 4H-SiC PiN Diodes on Bonded Substrates

Analysis of forward bias degradation reduction of 4H-Silicon Carbide (4H-SiC) PiN diodes on bonded substrates was performed. In the analysis, cathodoluminescence (CL), photoluminescence imaging (PL imaging), and transmission electron microscope (TEM) were used. Under high forward bias stress, the Shockley-type stacking fault (SSF) does not expand into the transferred layer of the bonded substrate, while in the monocrystalline substrate, the SSF expands below the epilayer/substrate interface. The basal plane dislocation (BPD) within the transferred layer does not expand to the SSF. The transferred layer has the effect of suppressing the expansion of SSFs. This effect can be caused by hydrogen implantation for wafer splitting to produce bonded SiC substrates.

Evaluation of p-GaN HEMTs degradation under high temperatures forward and reverse gate bias stress

In this study, the degradation behavior and physical mechanism of the p-GaN HEMT devices under high-temperature gate bias (HTGB) with +5 V and −5 V were investigated. The DC characteristics show that the device after forward HTGB stress exhibits an obvious negative threshold voltage (Vth ) shift, while the device after reverse HTGB exhibits a negligible shift. The following explanations could be given for the deterioration mechanism: a portion of the two-dimensional hole gas (2DHG) accumulated in the p-GaN layer at the p-GaN/AlGaN interface under long-term forward bias may fill the trap in the AlGaN layer through the tunneling effect. In addition, the drain-source on-resistance of the device had increased after +5 V HTGB stress, and a distinct decrease of accumulated capacitance was observed in the Cg -Vg curve. It indicates a degradation of the gate quality of the device after applying a forward-biased HTGB stress.

Investigation of the time dependent gate dielectric stability in SiC MOSFETs with planar and trench gate structures

In this work, the time-dependent dielectric breakdown (TDDB) analysis is performed to understand the gate oxide reliability in SiC MOSFETs with two different structures, i.e., planar and trench gate structures. We have discovered different gate leakage current behaviors between the SiC MOSFETs with planar gate (Sample A) and trench gate (Sample B) during the forward gate bias stress. Notably, the slight increase of the gate current during the stress and the negative activation energy (Ea = −0.07 eV) observed in Sample A suggest that the hole generation caused by the impact ionization can be occurred during the forward gate TDDB tests. Furthermore, the SiC MOSFETs with trench gate structure (Sample B) exhibit the operation voltage of 55.7 V (exponential law) and 57.3 V (power law) for the 0.001 % failure of 30 years under 175 °C, indicating that SiC trench gate MOSFETs with enough thick gate dielectric (87.1 nm (bottom) and 77.9 nm (sidewall)) can have the promising forward gate TDDB stability.

Characterization of GaON as a surface reinforcement layer of p-GaN in Schottky-type p-GaN gate HEMTs

The surface of the p-GaN layer in Schottky-type p-GaN gate high-electron-mobility transistors (HEMTs) can be reinforced with enhanced immunity to hot electron bombardment by reconstructing the surface region of p-GaN into GaON. The surface region of p-GaN is treated by remote oxygen plasma and subsequently annealed at 800 °C, thereby becoming a thin crystalline gallium oxynitride (GaON) layer that will be in direct contact with the Schottky metal. The GaON exhibits a lower valence band maximum energy than that of the p-GaN, which leads to a higher Schottky barrier at the metal/GaON interface to holes and, thus, greatly suppresses the forward gate leakage. More importantly, with higher thermodynamic stability and a larger bandgap of ∼4.1 eV, the GaON reinforces the susceptible metal/p-GaN interface against the hot electrons and, thus, substantially enhances the long-term gate reliability of p-GaN gate HEMTs under forward bias stress. The high-temperature thermal process is indispensable for the surface reconstruction, without which the plasma oxidation only reduces the gate leakage but fails to prolong the time-dependent gate breakdown lifetime.

ON-Resistance of Ga2O3 Trench-MOS Schottky Barrier Diodes: Role of Sidewall Interface Trapping

We present a comprehensive study of the ON-resistance ( R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> ) of Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> trench-MOS Schottky barrier diodes (SBDs), with a focus on the effect of sidewall interface trapping. Capacitance-voltage characteristics of MOS-capacitors and current-voltage characteristics of trench SBDs were all repeatedly measured under increasing forward-bias stress voltage to at least +15 V. Both reveal an increase in negative charges trapped near the MOS interface under increasing forward bias, as well as slow detrapping. The slow detrapping in trench SBDs causes a current collapse and a delayed turn-on behavior in the trench SBDs due to sidewall depletion. Through modeling of the fresh R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> , we found that the sidewall depletion can be eliminated under sufficiently high forward bias. Interestingly, the dynamic R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> under the forward-bias stress is lower than the fresh R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> . Such an anomalous behavior is well-explained by analytical calculation of the apparent differential R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> , which can be lowered by a modulation of fin-channel conductivity under forward bias. This study highlights the importance of sidewall interface quality in trench-MOS SBDs and calls for scrutiny on the interpretation of the apparent differential R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> , as artificially low values may arise due to the voltage dependence of R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> .

Towards Understanding the Interaction Between Hydrogen Poisoning and Bias Stress in AlGaN/GaN MIS-HEMTs With SiNx Gate Dielectric

In this work, the interaction between hydrogen poisoning (HP) and bias stress in AlGaN/GaN MIS-HEMTs, which incorporate a SiNx gate dielectric, is investigated. The transfer characteristics show that a hydrogen-poisoned device exhibits a 1.15-V-negative threshold voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> ) shift, a significant direct current (DC) ON-resistance (RON_DC) decrease, and a subthreshold swing (SS) decrease with respect to a fresh device, whereas the max-gm remains unchanged after excluding the effect of RON_DC. Moreover, the border trap energy distribution remains almost unaffected before and after HP, indicating that the border traps are insensitive to HP. The experimental results show that HP causes passivation in the interface states at the SiNx/AlGaN interface and introduces mobile H <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> ions in the bulk SiNx, resulting in the negative V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> shift, RON_DC decrease, and SS decrease. After applying a forward-bias stress on the gate, the H <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> ions in the bulk SiNx underneath the gate electrode drift toward the two-dimensional electron gas (2DEG) and annihilate with electrons, resulting in the irreversible positive V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> shift. The H <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> ions in the bulk SiNx beyond the gate electrode(gate-to-drain- and gate-to-source) remain unchanged, resulting in an unchanged RON_DC. This conclusion is significant for the AlGaN/GaN MIS-HEMT reliability optimization against HP, and it is particularly useful in spatial applications.

Analysis on degradation mechanisms of normally-off p-GaN gate AlGaN/GaN high-electron mobility transistor* *Project supported by the Equipment Developing Advanced Research Program of China (Grant No. 6140A24030107).

The degradation mechanisms of enhancement-mode p-GaN gate AlGaN/GaN high-electron mobility transistor was analyzed extensively, by means of drain voltage stress and gate bias stress. The results indicate that: (i) High constant drain voltage stress has only a negligible impact on the device electrical parameters, with a slightly first increase and then decrease in output current; (ii) A negative shift of threshold voltage and increased output current were observed in the device subjected to forward gate bias stress, which is mainly ascribed to the hole-trapping induced by high electric field across the p-GaN/AlGaN interface; (iii) The analyzed device showed an excellent behavior at reverse gate bias stress, with almost unaltered threshold voltage, output current, and gate leakage current, exhibiting a large gate swing in the negative direction. The results are meaningful and valuable in directing the process optimization towards a high voltage and high reliable enhanced AlGaN/GaN high-electron mobility transistor.

Commercialization of Highly Rugged 4H-SiC 3300 V Schottky Diodes and Power MOSFETs

In this paper, we present a new family of 3300 V silicon carbide (SiC) Schottky barrier diodes (SBDs) and power MOSFETs. The main design requirements are discussed with an emphasis on the design rules to improve the long-term reliability. Basic static and dynamic performance demonstrates low conduction and switching losses. Long-term tests such as high-temperature reverse bias (HTRB) and body diode forward bias stress were performed to evaluate the devices’ reliability. An emission microscopy (EMMI) study was conducted to assess the quality of the gate oxide. Outstanding surge and avalanche capabilities are reported with UIS ruggedness of 11.4 and 20.8 J.cm-2 for SBDs and MOSFETs, respectively.

Experimental evaluation of interface states during time-dependent dielectric breakdown of GaN-based MIS-HEMTs with LPCVD-SiNx gate dielectric**Project supported by the National Key Research and Development Program of China (Grant No. 2017YFB0402800), the Key Research and Development Program of Guangdong Province, China (Grant Nos. 2019B010128002 and 2020B010173001), the National Natural Science Foundation of China (Grant Nos. U1601210 and 61904207), the Natural Science

We experimentally evaluated the interface state density of GaN MIS-HEMTs during time-dependent dielectric breakdown (TDDB). Under a high forward gate bias stress, newly increased traps generate both at the SiNx/AlGaN interface and the SiNx bulk, resulting in the voltage shift and the increase of the voltage hysteresis. When prolonging the stress duration, the defects density generated in the SiNx dielectric becomes dominating, which drastically increases the gate leakage current and causes the catastrophic failure. After recovery by UV light illumination, the negative shift in threshold voltage (compared with the fresh one) confirms the accumulation of positive charge at the SiNx/AlGaN interface and/or in SiNx bulk, which is possibly ascribed to the broken bonds after long-term stress. These results experimentally confirm the role of defects in the TDDB of GaN-based MIS-HEMTs.

Degradation mechanisms of bias stress on nitride-based near-ultraviolet light-emitting diodes in salt water vapor ambient

Degradation mechanisms of nitride-based near-ultraviolet (near-UV) light-emitting diodes (LEDs) were systematically analyzed by applying forward- and reverse-bias stresses to them in a salt water vapor ambient. The surface temperature of the forward-bias stress sample was higher than that of the reverse-bias stress sample. The high temperature of the forward-bias stress sample accelerated the chemical reaction of the device structure with salt water vapors and led to faster degradation. Composition analyses of the sample surface and cross-section were conducted to investigate the failure mechanism. The analyses results indicated that the erosion of the indium–tin–oxide layer enhanced the diffusion of the conducting metal into the LED crystal. The proposed method can effectively characterize the quality of near-UV LEDs in a short duration.

Normally-off recessed-gate AlGaN/GaN MOS-HFETs with plasma enhanced atomic layer deposited AlOxNy gate insulator

We developed a high-quality plasma enhanced atomic layer deposited (PEALD) aluminum oxynitride (AlOxNy) process for the metal-oxide-semiconductor (MOS) gate insulator of fully-recessed-gate AlGaN/GaN-on-Si MOS-heterojunction field-effect transistors (MOS-HFETs). It was found that the cyclic nitrogen incorporation into aluminum oxide (Al2O3) during PEALD process improved the conduction band offset at GaN interface resulting in higher forward breakdown field strength, which also contributed to suppressed trapping effects under forward gate bias stress. Improved interface characteristics, which resulted from suppressed surface oxidation, led to significant improvement of threshold voltage stability. A low threshold voltage hysteresis of 180 mV at maximum gate sweep voltage of 10 V was obtained with AlOxNy gate insulator. The MOS channel mobility was also improved to 235 cm2 V−1 s−1. The fabricated fully-recessed-gate AlGaN/GaN-on-Si MOS-HFET with PEALD AlOxNy gate insulator exhibited excellent overall performances such as a threshold voltage of 3.2 V, a maximum drain current density of 481 mA mm−1, an on/off current ratio of ∼1010, an ON-resistance of 12 mΩ mm, and a breakdown voltage of 1050 V.

Effects of surface plasma treatment on threshold voltage hysteresis and instability in metal-insulator-semiconductor (MIS) AlGaN/GaN heterostructure HEMTs

In a bid to understand the commonly observed hysteresis in the threshold voltage (VTH) in AlGaN/GaN metal-insulator-semiconductor high electron mobility transistors during forward gate bias stress, we have analyzed a series of measurements on devices with no surface treatment and with two different plasma treatments before the in-situ Al2O3 deposition. The observed changes between samples were quasi-equilibrium VTH, forward bias related VTH hysteresis, and electrical response to reverse bias stress. To explain these effects, a disorder induced gap state model, combined with a discrete level donor, at the dielectric/semiconductor interface was employed. Technology Computer-Aided Design modeling demonstrated the possible differences in the interface state distributions that could give a consistent explanation for the observations.

Current linearity and operation stability in Al2O3-gate AlGaN/GaN MOS high electron mobility transistors

To investigate current linearity and operation stability of metal–oxide–semiconductor (MOS) AlGaN/GaN high electron mobility transistors (HEMTs), we have fabricated and characterized the Al2O3-gate MOS-HEMTs without and with a bias annealing in air at 300 °C. Compared with the as-fabricated (unannealed) MOS HEMTs, the bias-annealed devices showed improved linearity of ID–VG curves even in the forward bias regime, resulting in increased maximum drain current. Lower subthreshold slope was also observed after bias annealing. From the precise capacitance–voltage analysis on a MOS diode fabricated on the AlGaN/GaN heterostructure, it was found that the bias annealing effectively reduced the state density at the Al2O3/AlGaN interface. This led to efficient modulation of the AlGaN surface potential close to the conduction band edge, resulting in good gate control of two-dimensional electron gas density even at forward bias. In addition, the bias-annealed MOS HEMT showed small threshold voltage shift after applying forward bias stress and stable operation even at high temperatures.

Electroformed silicon nitride based light emitting memory device

The resistive memory switching effect of an electroformed nanocrystal silicon nitride thin film light emitting diode (LED) is demonstrated. For this purpose, current-voltage (I-V) characteristics of the diode were systematically scanned, paying particular attention to the sequence of the measurements. It was found that when the voltage polarity was changed from reverse to forward, the previously measured reverse I-V behavior was remembered until some critical forward bias voltage. Beyond this critical voltage, the I-V curve returns to its original state instantaneously, and light emission switches from the OFF state to the ON state. The kinetics of this switching mechanism was studied for different forward bias stresses by measuring the corresponding time at which the switching occurs. Finally, the switching of resistance and light emission states was discussed via energy band structure of the electroformed LED.

Characterization of Interface Defects With Distributed Activation Energies in GaN-Based MIS-HEMTs

Charge trapping is one of the main reliability issues for GaN-based MIS-high-electron-mobility-transistor technologies. In this paper, we focus on the defects located at or close to the interface with the dielectric, which are responsible for the threshold voltage instability at positive gate bias conditions. We present a methodology to analyze the experimental data based on the nonradiative multiphonon model for charge trapping. In particular, we show how to extract the density of interface traps as a function of their activation energy from stress and recovery experiments performed at various temperatures. Our approach is applied to two GaN/AlGaN/SiN samples with different trapping properties, at temperatures ranging from −190 °C to 200 °C. We evaluate their response to forward bias stress and finally, we extract the activation energy distribution for electron capture and emission over a continuous energy range.

Application of Photocurrent Model on Polymer Solar Cells Under Forward Bias Stress

We performed a constant current stress at forward bias on organic heterojunction solar cells. We measured current voltage curves in both dark and light at each stress step to calculate the photocurrent. An existing model applied to photocurrent experimental data allows the estimation of several parameters such as generation, recombination, dissociation rate, and nearly zero field voltage within the active layer as a function of the stress time. The analysis of extrapolated parameters shows that the stress mainly affects the recombination rate of the polaron charge transfer states.

Effects of Basal Plane Dislocation Density in 4H-SiC Substrate on Degradation of Body-Diode Forward Voltage

We investigated the effect of the basal plane dislocation (BPD) density in 4H-silicon carbide (SiC) substrates on the forward voltage (Vsd) degradation of body-diodes. Using reflection X-ray topography, the BPD density was automatically estimated from the substrates prior to fabrication of metal–oxide–semiconductor field-effect transistors (MOSFETs). A strong positive correlation was found between the Vsd shift, which was calculated from the difference before and after forward bias stress at 160 A/cm2 for ~500 hours, and the BPD density of the substrate. We show that it is possible to predict Vsd shifts from the BPD densities of SiC substrates prior to the fabrication of MOSFETs. In addition, we examined the origin of stacking faults (SFs) as a result of the application of forward bias stress. We presume that SFs are formed by BPDs converted to threading edge dislocations at the epi/sub interface, as well as by BPDs penetrating into the epitaxial layer.

Gate Reliability Investigation in Normally-Off p-Type-GaN Cap/AlGaN/GaN HEMTs Under Forward Bias Stress

Gate reliability of normally-off p-type-GaN/AlGaN/GaN high-electron mobility transistors grown on Si substrate subjected to forward bias stress at different gate voltages and temperatures was analyzed. Stress-induced gate current degradation was found to be consistent with the percolation process. Obtained time-to-breakdown data were interpreted using the Weibull statistics, and the maximum allowed gate operating voltage was estimated. The gate degradation was found to be weakly dependent on temperature with an activation energy of 0.1 eV.