Shallow Junction Formation Research Articles

Numerical simulation of plasma implanted nitrogen depth profiles in iron

Plasma immersion ion implantation (PIII) is a relatively complex process. Utilizing plasma and TRIM simulation, plasma implanted nitrogen depth profiles in iron are simulated in this work. Many factors such as the high voltage pulse rise time, voltage amplitude, pulse duration, plasma composition, etc. have a critical influence on this depth profiles. Our results confirm the broader distribution as well as shift of the implant peak toward the surface. Compared to the pulse duration and plasma composition, the rise time of the high voltage pulse has a more predominant effect on the shape of the profile. At higher implantation voltage, the nitrogen profile resembles that of multiple energy implantation in the beam-line mode. From this perspective, broadening of the ion energy spectrum in PIII is favorable since a single process can achieve the results of multiple energy ion implantation. This is particularly useful for processes such as shallow junction formation in microelectronics.

Reduction of boride-enhanced diffusion by point defect engineering and its application for shallow junction formation

Point defect engineering using high energy ion bombardment can be used as a method to inject vacancies near the surface region with excessive interstitials created near the end of the projected range. We demonstrated that implantation of MeV Si ions into a Si substrate can suppress boride-enhanced diffusion normally associated with a high B concentration layer. The concept of boron diffusion control can be used as an approach to form ultra-shallow junction.

Optics for Laser Crystallization Technology.

Excimer laser based crystallization has become a workhorse in preparing poly-Si films for the manufacture of back plates for active matrix liquid crystal displays. Alternative laser techniques applying cw laser sources provide high quality crystal films however at a very slow rate. Line Beam optics combined with 300 W power excimer lasers to scan large area electronics substrates are achieving fast processing and very homogeneous poly-Si films. Very good laser beam homogeneity is critical for the near complete melt process. Furthermore high resolution diffraction limited optics systems are described for the sequential lateral solidification of amorphous silicon films. High quality films with electron mobility of 100-300 cm2/Vs can be produced. The generation of films for microelectronic circuits is an additional potential of the laser based crystallization process, thus even the application to the formation of shallow junctions for submicron technology is considered.

Transient-enhanced diffusion in shallow-junction formation

Shallow junctions are formed in crystalline Si by low-energy ion implantation of B+, P+, or As+ species accompanied by electrical activation of dopants by rapid thermal annealing and the special case of spike annealing. Diffusion depths were determined by secondary ion-mass spectroscopy (SIMS). Electrical activation was characterized by sheet resistance, Hall coefficient, and reverse-bias diode-leakage measurements. The B+ and P+ species exhibit transient-enhanced diffusion (TED) caused by transient excess populations of Si interstitials. The electrically activated fraction of implanted dopants depends mainly on the temperature for B+ species, while for P+ species, it depends on both temperature and P+ dose. The relatively small amount of diffusion associated with As+ implants is favorable for shallow-junction formation with spike annealing.

N/sup +//P junction leakage characteristics of Co salicide process for 0.15 μm CMOS devices

We have proposed that As dopants in the n/sup +//p active region are redistributed during Co salicidation process, especially in the active edge area in contact with the field oxide. The dopant redistribution has been verified through a novel two-dimensional (2-D) dopant profiling method, i.e., the transmission electron microscope (TEM) combined with selective chemical etching. It was shown that As dopants move down from the silicide layer into the junction area, which results in the deeper junction compared with nonsilicided junction. On the contrary, the junction profile behavior at the active edge area is completely opposite to that inside active region. That is, the junction profile is bent upward at the active edge, which results in the increase or even fail of junction leakage current of perimeter intensive diodes due to the decreased distance from the silicide bottom to the junction depth. Therefore, the dopant redistribution at the n/sup +//p active edge should be reduced or suppressed for reliable shallow silicided junction formation.

Cluster-ion implantation: An approach to fabricate ultrashallow junctions in silicon

Cluster-ion implantation in combination with two-step annealing is effective in making ultrashallow junctions. We have demonstrated the use of heavy atom–boron cluster ions to effectively reduce the boron energy for shallow-junction formation. SiB, SiB2, and GeB cluster ions have been used to produce 2 keV boron for low-energy ion implantation. We have generated the SiB, SiB2, and GeB cluster ions using the source of negative ions by cesium sputtering ion source. Shallow junctions have been made by SiB, SiB2, and GeB cluster ions implanted into Si substrates at 1×1015/cm2 with energies at 6.88, 8.82, and 15 keV, respectively. We also discussed the benefit of a 550 °C preannealing before a 1000 °C, 10 s rapid thermal annealing.

The effect of plasma exposure and annealing atmosphere on shallow junction formation using plasma source ion implantation

The effect of recoil-implantation and out-diffusion in plasma source ion implantation (PSII) on ultra-shallow p +/n junction formation has been studied. Because the wafer is directly exposed to plasma, diborane radicals in the plasma can be adsorbed on the wafer surface. The amount of recoil-implanted boron as an additive dose was measured. In the annealing process, increasing the nitrogen pressure from vacuum to 360 torr, decreased the boron out-diffusion. In addition, increasing the annealing time rendered the boron out- and in-diffusion severe. Considering recoil implantation, the wafers were implanted with a dose of 1.98×10 15 atoms/cm 2. The as-implanted wafers were subsequently spike-annealed at 1000 °C in nitrogen ambient. With implant energy of 0.5 and 1 keV, ultra-shallow junction depths of 360 and 380 Å, respectively, could be acquired. In addition, sheet resistance of 420 and 373 Ω/□ were obtained, respectively. This junction depth and sheet resistance prepared by PSII was found to satisfy next-generation memory-device doping technology.

Ultra Shallow Junction Formation with High Process Controllability Using Optimized Rapid Thermal Anneal Process

Implant and rapid thermal annealing (RTA) are investigated for a source/drain (S/D) formation process. Optimization of RTA conditions is the key for ultra shallow junction formation. This paper describes the ultra shallow junction formation using RTA. We investigate the effects of thermal budget such as ramp-up rate and ramp-down rate, oxygen content and cap films during the RTA process for achieving a shallow junction and low sheet resistance. In addition, we investigate the effects of these parameters on process controllability and on the combination of complementary metal-oxide-semiconductor (CMOS) fabrication. Using optimized RTA technology, shallow junctions with low sheet resistance and good process controllability for early 100 nm technology nodes can be achieved, even though problems remain with process controllability for wafers of various structures and with the trance enhanced diffusion (TED) effect of gate side-wall spacers.

Sputtering of Si with decaborane cluster ions

Decaborane cluster ions (B10Hx+) may play an important role in the manufacturing of future semiconductor devices, as they facilitate a very shallow implantation of B with a relatively high beam energy, due to its partition among the constituent atoms. While the formation of B-doped shallow junctions in Si has been demonstrated, little is known about other effects of these complex ions on a solid. We have measured the sputtering yield of Si with decaborane cluster ions at 12 keV and demonstrated that their impacts smooth rather than roughen the surface, similarly to much larger Ar cluster ions. The results have implications for the understanding of low-energy atomic impacts in terms of collective motion of many surface atoms and of the behavior of solids far from equilibrium.

Super self-aligned technology of ultra-shallow junction in MOSFETs using selective Si 1− xGe x CVD

The fabrication process is investigated to improve the super self-aligned ultra-shallow junction electrode MOSFET (S 3EMOSFET) by utilizing in-situ impurity-doped Si 1− x Ge x selective epitaxy on the source/drain regions at 550 °C by means of LPCVD. It is found that phosphorus-doped Si 1− x Ge x films with a high Ge fraction have low solid solubility of electrically active phosphorus, and boron-doped Si 1− x Ge x films with a high Ge fraction have a low barrier height for tungsten. Therefore, both a Si 1− x Ge x film with a low Ge fraction and one with a high Ge fraction are necessary to fabricate n- and p-MOSFETs with low contact resistivity. A super self-aligned process on the source/drain regions using selective in-situ-doped Si 1− x Ge x growth, shallow junction formation, and subsequent very-low-temperature tungsten growth are effective in reducing the source/drain resistance. 0.1 μm gate pMOSFETs are fabricated by means of the super self-aligned technology. They show good drain current drivability and roll-off characteristics due to the suppression of parasitic source/drain resistance and the ultra-shallow source/drain layers.

A novel atomic doping technology for ultra-shallow junction of SOI-MOSFETs

A novel technology to fabricate an ultra shallow source and drain extension (SDE) junctions for the future SOI-MOSFETs was investigated. In this technology, a dopant in an adsorbed layer on SOI surface diffuses into the substrate by the rapid thermal annealing (RTA) or laser annealing (LA). Arsenic adsorbed layer is formed using UHV CVD apparatus during thermal decomposition of AsH 3 on Si (001) at 550 °C with a base pressure of ∼1×10 −10 Torr. RTA and LA have been identified as preferred annealing process for shallow junction formation because it provides low thermal budget control for junctions and high level of dopant activation and defect annealing. This method made it possible to control the junction depth with low sheet resistance for the sub 0.1 μm SOI-MOSFET.

Application of NRA to evaluation of boron implants in Si for shallow junctions

In shallow junction formation, the estimation of ion-implanted dopant doses is essential. Secondary ion mass spectrometry (SIMS) has been widely used for the acquisition of depth profiling and quantification of boron implants. However, SIMS analysis is unsuitable for accurate quantification in shallow regions. In this study, we propose nuclear reaction analysis (NRA) as a method for analyzing boron implants for shallow junctions. NRA was also used for the determination of the total amount of boron after rapid thermal annealing (RTA). The results revealed that the total amounts of boron in Si have obvious dependences on both the temperature and duration time of RTA. We proposed channeling-NRA for the evaluation of the activation ratios of boron atoms. In the case of high-temperature annealing, we found that about 90% of boron atoms were located in substitutional sites.

Low Temperature Shallow Junction Formation For 70nm Technology Node And Beyond

AbstractLow temperature shallow junction formation is an attractive activation technique for 70nm technology node and beyond as it can easily be integrated into device structures that are formed using disposable spacer (reverse source drain extension formation) or low power CMOS devices using high-k/metal gate stack structures. Therefore, this paper will first review the shallow junction requirements as stated in the 2001 ITRS (international technology roadmap for semiconductors) and it's interpretation to ion implantation shallow junction formation for various dopant activation and annealing techniques. First high temperature (>1000°C) RTA spike, flash or sub-melt laser annealing techniques with oxide or oxynitride/polysilicon electrode gate stack structures will be discussed and its limitations to >8E19/cm3 boron electrically active dopant level due to boron solid solubility limit in silicon satisfying only the 100nm technology node requirement (2003). Next, higher temperature laser melt annealing (1200°C to 1400°C) will be discussed and it's applicability beyond 70nm node technology (2006) to 25nm node (2016) where boron solid solubility limit is up to 5E20/cm3. However, if high-k (HfO) dielectric/metal electrode gate stack structures are to be used starting at sub-100nm node in 2005 for low power CMOS then low temperature (>700°C) annealing must be used for shallow junction formation to prevent recrystallization and dielectric constant degradation. Using low temperature SPE (solid phase epitaxial regrowth) annealing techniques in the 550°C to 750°C for short anneal times of >5mins., shallow & abrupt junctions 8.0nm deep, >2.0nm/decade with up to 2.5E20/cm3 boron electrical active dopant level can be achieved satisfying the 25nm technology node (2016) requirements.

Point Defect Engineering and Its Application in Shallow Junction Formation

Point defect engineering using high-energy ion bombardment can be used as a method to inject vacancies near the surface region with excessive interstitials created near the end of the projected range deep inside the substrate. We demonstrate that implantation of MeV Si ions into a Si substrate can suppress boride-enhanced diffusion normally associated with a high B concentration layer. B atoms from a surface-deposited boron layer experienced a suppressed diffusion during annealing if the Si substrate was preimplanted with MeV Si ions, and the retardation of B diffusion became more effective with higher dosages. The concept of boron diffusion control was used as an approach to form ultrashallow junctions.

S/D Engineering for Sub-100 nm MOSFET using Ultra Shallow Junction Formation Technique, Elevated S/D Structure and SALICIDE Technique

AbstractSuppression of short channel effect (SCE) by utilizing the technology of formation of ultrashallow junctions is one of the important issues. The annealing process of implantation-damage that induces transient enhanced diffusion during a subsequent thermal process, such as low-pressure chemical vapor deposition (LPCVD) for gate sidewall spacer, should be optimized. To pursuit high performance of MOSFETs, parasitic resistance must be reduced with scaling. On the other hand, it is difficult to decrease the parasitic resistance in the region of contact junction, which is a function of physical constant such as Schottky barrier height of silicide materials and solid solubility of dopant. The elevated source/drain structure reduces parasitic resistance of contact junction due to reduction of resistance of diffusion beneath salicide materials. Cobalt salicide is widely used till 100nm node. However, cobalt salicide has disadvantage in the thermal budget for shallow junction and quantity of silicon consumption during silicidation. Nickel salicide is one of the candidates for successor of cobalt salicide to 70 nm node or above, because of its characteristics of low temperature formation, low silicon consumption and low contact resistivity on p+ junctions. In this paper, S/D engineering will be discussed from the viewpoint of the process integration of sub-100 nm physical gate length complementary metal-oxide-semiconductor field-effect transistor (CMOSFET) device.

Ultra-shallow junction formation by excimer laser annealing and low energy (

Formation of shallow junctions has been investigated by using excimer laser annealing in combination with two implantation schemes: BF 2-ions at 20 keV and B-ions at low energies (<1 keV). The latter approach was shown to produce best results, with ultra-shallow profiles extending to a depth as low as 35 nm. The lateral distribution of the implanted B following laser annealing has been studied with two-dimensional measurements using selective etching and cross-section transmission electron microscopy (TEM) on samples where the implanted dopant was confined within an oxide mask. The results show that there is substantial lateral diffusion of B under the oxide mask when melting occurs in this region while, if melting under the oxide mask is prevented, the implanted B close to the oxide mask edge was not activated by laser annealing. The results have been explained by numerical heat-flow calculations and it is concluded that the melting of the Si under the masked region and, therefore, the lateral diffusion, can be controlled by the oxide mask thickness.

Shallow junction formation on p-like CdTe crystals by indium diffusion using excimer laser annealing

Excimer laser annealing has been investigated to form a shallow junction on p-like CdTe crystals by indium diffusion. By evaporating a thin layer of indium on the CdTe crystals in a physical vapor deposition system without heating the crystals, and then irradiating them with an excimer laser, we could produce a highly conductive thin surface layer on the crystal. These layers showed n-type conductivity in Hall measurements, and an increase on the donor-acceptor pair band, possibly due to indium incorporation, was also observed in the photoluminescent spectrum. The best value of resistivity, carrier concentration and electron mobility of the layer thus obtained was 5 10−3 cm, 9 1018 cm−3, and 138 cm2/Vs, respectively. The carrier transport properties of the shallow p-n junction formed were then investigated by means of current-voltage measurements at different temperatures. Furthermore, applicability of this junction in a gamma-ray detector was also investigated.

Laser Thermal Induced Crystallization for 20 nm Device Structures

ABSTRACTThe melt kinetics of shallow junction formation by laser thermal processes has been studied using transient conductance measurements. The melt and solidification dynamics of 20 nm amorphous layers were measured and shown to follow behaviors predicated by deeper melts, including explosive crystallization and interface bounce back. The effects of surface barrier oxides and metal absorber layers, required for CMOS process integration, were examined and shown to be nearly negligible. Quantitative evaluation of a device process window by these measurements was in good agreement with sheet resistance results. Finally, the effect of the buried oxide in SOI structures was investigated. Solidification velocities in such structures were reduced by a factor of three as compared with bulk silicon.

Applications of plasma immersion ion implantation in microelectronics — a brief review

Recent advances in plasma immersion ion implantation (PIII) are progressing at a rapid pace. PIII was originally envisioned as a conformal ion implantation technology for the surface modification of materials. PIII also offers the advantages of high dose rates, even at low energy, and single wafer implants over large areas. Such advantages are becoming very important for semiconductor manufacturing, particularly for 300-mm wafers and flat panel displays. Applications of PIII in microelectronics introduce new considerations. Conformal implantation is not required, and is unwanted in most semiconductor processes, except for trench doping-type applications. In various implant applications, there are often radically different requirements of plasma physics and chemistry. For example, the formation of shallow junctions requires extremely low energy implantation, and a precise implant range may not be necessary or ideal. In this application, PIII becomes the concept of plasma doping, where a wafer under either a DC or pulse bias is directly exposed to the plasma. On the other hand, hydrogen PIII for layer transfer requires extremely precise implant ranges, straggles and sample temperature, but the exact dose may not be critical. In this paper, two important application areas that have attracted much attention and research in the past 2 years, hydrogen PIII and the fabrication of low- k materials, are reviewed.

Understanding and Modeling Ramp Rate Effects on Shallow Junction Formation

SummaryIn summary, we find it is possible to model the extent of diffusion during spike anneals with varying ramp rates by considering the full thermal cycle. These models allow the optimization of RTP ammealing cycles considering the trade-offs between junction depth and sheet resistance. For example, with 1050°C spike anneals, the active dose (and thus sheet conductivity) varies approximately linearly with junction depth. However, faster ramp rates allow the use of higher spike temperatures, with associated higher activation and reduced sheet resistance for the same junction depth.Work at Bosten University and the University of Washington was supported by the Semiconductor Research Corporation. We would like to thank Eric Perozziello for details and discussion regarding their experimental results.