Ultra Shallow Junction Formation with High Process Controllability Using Optimized Rapid Thermal Anneal Process

Abstract

Implant and rapid thermal annealing (RTA) are investigated for a source/drain (S/D) formation process. Optimization of RTA conditions is the key for ultra shallow junction formation. This paper describes the ultra shallow junction formation using RTA. We investigate the effects of thermal budget such as ramp-up rate and ramp-down rate, oxygen content and cap films during the RTA process for achieving a shallow junction and low sheet resistance. In addition, we investigate the effects of these parameters on process controllability and on the combination of complementary metal-oxide-semiconductor (CMOS) fabrication. Using optimized RTA technology, shallow junctions with low sheet resistance and good process controllability for early 100 nm technology nodes can be achieved, even though problems remain with process controllability for wafers of various structures and with the trance enhanced diffusion (TED) effect of gate side-wall spacers.