Formation Of NiSi Research Articles

Multi-Wavelength Raman and HRTEM Study of Ni/Si Interface after NiSi Formation at Low Temperatures using Various Heating Methods

Low-temperature formation processes of Ni silicide were studied by Raman scattering and cross-sectional transmission electron microscopy (TEM) using Si wafer samples deposited with thin Ni layers. Comparisons were made between two annealing methods; lamp based rapid thermal process (lamp RTP) and a hot wall chamber RTP system. The TEM and Raman observations showed good agreement on the Ni silicidation scheme at the Ni/Si interface. It is shown that Raman scattering spectroscopy is a convenient, non-contact and non-destructive characterization tool to probe and investigate the Ni-silicide formation process in the top nm-order surface of metal/Si contact.

Integrating Selective Epitaxy in Advanced Logic & Memory Devices

In this paper, we review integration of selective epitaxy in advanced logic and memory devices. Embedded SiGe epitaxy has been adapted for logic pMOSFET fabrication from the 90 nm technology node and device performance continues to scale with higher [Ge] in the epitaxial SiGe layer. For nMOSFET performance boost, use of embedded silicon carbon (Si:C) epitaxial layer has been considered. Recent improvements in crystal quality of selective in-situ phosphorus doped Si:C epitaxy enables significant transistor drive current increase. For integration of Si:C epitaxy, effect of various thermal annealing processes on substitutional carbon incorporation and NiSi formation on Si:C epitaxy are described. Also, heavy phosphorus doping in Si and Si:C layers is discussed in terms of film resistivity and strain contribution. Selective epitaxy is being used to form elevated source/drain in DRAM memory devices where it provides immunity against short channel effects and results in improved retention time.

Measurement of the redistribution of arsenic at nickel silicide/silicon interface by secondary ion mass spectrometry: artifact and optimized analysis conditions

The arsenic redistribution after NiSi formation has been measured by secondary ion mass spectrometry (SIMS). The NiSi film has been obtained by solid state reaction of a Ni thin film with a silicon substrate doped with As. An increase in the As SIMS signal at the NiSi/Si interface was observed for some experimental conditions. By varying the SIMS experimental parameters (incidence angle and the impact energy), the As signal at NiSi/Si interface was found to change. The SIMS experimental parameters have been optimized and were found to be an impact energy of 1 keV and an incidence angle superior to 50°. This allows us to minimize differences in sputtering rate and ion yield between NiSi and Si and to obtain a good depth resolution and dynamic range. Under these conditions the bump in the As signal does not appear: this illustrates the difficulty to measure concentration at interface by SIMS.

Effect of stress on the transformation of Ni2Si into NiSi

In situ isothermal x-ray diffraction were performed on Ni∕a-Si and Ni(5%Pt)/(100)Si. In the Ni∕a-Si samples, there is a time delay between the formation of NiSi and the end of the growth of Ni2Si. In the Ni(5%Pt)/(100)Si, the growth of the NiSi phase is accelerated after a time delay. The time delay is related to the strain relaxation in Ni2Si; i.e., the growth of NiSi starts (pure Ni case) or is accelerated [Ni(Pt) case] when most of the strain in Ni2Si is relaxed. This shows that the intrinsic stress associated with the growth of silicide influence the reactive diffusion.

Multi-Wavelength Raman and HRTEM Study of Ni/Si Interface after NiSi Formation at Low Temperatures using Various Heating Methods

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Crystallization kinetics and recording mechanism of a-Si∕Ni bilayer for write-once blue-ray recording

For the a-Si∕Ni bilayer with a thickness ratio of 4:1, the formation of NiSi and NiSi2 phases took place in the temperature range between 200 and 350°C and only ∼9% of unreacted a-Si would crystallize to c-Si, which will not cause appreciable reflectivity change. As the thickness ratio of a-Si to Ni was increased to 20:1, the formation of NiSi2 phase and subsequent crystallization of a-Si mediated by NiSi2 precipitates were clearly observed. The crystallization temperature of a-Si in the a-Si∕Ni bilayer with a thickness ratio of 20:1 was significantly reduced to around 350°C, which was 130°C lower than that in the a-Si∕Cu bilayer. The activation energies for NiSi2 phase formation and crystallizations of a-Si for the a-Si∕Ni bilayer with a thickness ratio of 20:1 were determined to be 1.12±0.09 and 2.19±0.08eV, respectively. The crystallization behavior of the a-Si(20nm)∕Ni(1nm) bilayer recording film under pulsed laser irradiation is similar to that under thermal annealing. During the recording process, the NiSi2 phase will precipitate first and serve as the nucleation sites for the following crystallization of the remaining amorphous Si. The maximum value of carrier to noise ratio for 3T could reach 43dB for the write-once blue-ray disk with layer structure of a-Si(20nm)∕Ni(1nm), demonstrating a high potentiality for practical use.

Transient and end silicide phase formation in thin film Ni/polycrystalline-Si reactions for fully silicided gate applications

The Ni/polycrystalline-Si thin film reaction was monitored by in situ x-ray diffraction during ramp annealings, obtaining a detailed view of the formation and evolution of silicide phases in stacks of interest for fully silicided gate applications. Samples consisted of Ni (30–170nm)/polycrystalline-Si (100nm)∕SiO2 (10–30nm) stacks deposited on (100) Si. The dominant end phase (after full silicidation) was found to be well controlled by the deposited Ni to polycrystalline-Si thickness ratio (tNi∕tSi), with formation of NiSi2 (∼600°C), NiSi (∼400°C), Ni3Si2 (∼500°C), Ni2Si, Ni31Si12 (∼420°C), and Ni3Si (∼600°C) in stacks with tNi∕tSi of 0.3, 0.6, 0.9, 1.2, 1.4, and 1.7, respectively. NiSi and Ni31Si12 were observed to precede formation of NiSi2 and Ni3Si, respectively, as expected for the phase sequence conventionally reported. Formation of Ni2Si was observed at early stages of the reaction. These studies revealed, in addition, the formation of transient phases that appeared and disappeared in narrow temperature ranges, competing with formation of the phases expected in the conventional phase sequence. These included the transient formation of NiSi and Ni31Si12 in stacks in which these phases are not expected to form (e.g., tNi∕tSi of 1.7 and 0.9, respectively), at temperatures similar to those in which these phases normally grow.

The effect of Si addition and Ta diffusion barrier on growth and thermal stability of NiSi nanolayer

Formation and thermal stability of nanothickness NiSi layer in Ni(Pt 4at.%)/Si(100) and Ni0.6Si0.4(Pt 4at.%)/Si(100) structures have been investigated using magnetron co-sputtering deposition method. Moreover, to study the effect of Si substrate in formation of NiSi and its thermal stability, we have used Ta diffusion barrier between the Ni0.6Si0.4 layer and the Si substrate. Post annealing treatment of the samples was performed in an N2 environment in a temperature range from 200 to 900°C for 2min. The samples were analyzed by four point probe sheet resistance (Rs) measurement, X-ray diffraction (XRD) and atomic force microscopy (AFM) techniques. It was found that the annealing process resulted in an agglomeration of the nanothickness Ni(Pt) layer, and consequently, phase formation of discontinuous NiSi grains at the temperatures greater than 700°C. Instead, for the Ni0.6Si0.4(Pt)/Si structure, 100°C excess temperature in both NiSi formation and agglomeration indicated that it can be considered as a more thermally stable structure as compared with the Ni(Pt 4at.%)/Si(100) structure. XRD, AFM and Rs analyses confirmed formation of a continuous NiSi film with Rs value of 5Ω/□ in a temperature range of 700−800°C. Use of Ta diffusion barrier showed that the role of diffusion of Ni atoms into the Si substrate is essential in complete silicidation of a NiSi layer.

The Formation and Characterisation of Lanthanum Based (100)Si/High-k/NiSi Gate Stacks by Electron-Beam Evaporation: An Examination of In-Situ Amorphous Silicon Capping and NiSi Formation

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The Formation and Characterisation of Lanthanum Oxide Based Si/High-k/NiSi Gate Stacks by Electron-Beam Evaporation: An Examination of In-Situ Amorphous Silicon Capping and NiSi formation

The electrical and physical properties of La2O3 based NiSi/High-k/Si structures formed by electron beam evaporation, in-situ amorphous silicon capping and ex-situ NiSi formation are presented for the (100) and (110)Si substrate orientations. The silicon substrate orientation, (100) or (110), does not affect leakage current density or the maximum accumulation capacitance, but does have an impact on interface state densities. The interface states exhibit the electrical signature of Pbo centres for the (100)Si orientation and can be annealed in a H2/N2 ambient. The samples exhibit negligible hysteresis (<2mV). No interfacial silicon layer is observed between the La based high-k film and the silicon substrate. The extracted k value for the La2O3 based thin films is in the range 11-12 suggesting silicate formation. The work indicates an alternative approach for the examination of NiSi/high-k/Si MOS structures without ambient exposure of the high-k layer.

Effect of erbium interlayer on nickel silicide formation on Si(1 0 0)

To reveal the influence of erbium interlayer on the formation of nickel silicide and its contact properties on Si substrate, Er(0.5–3.0 nm) and Ni(20 nm) are successively deposited onto Si(1 0 0) substrate and are treated by rapid thermal annealing in pure N 2 ambient. The NiSi formation temperature is found to increase depending on the Er interlayer thickness. The formation temperature of NiSi 2 (700 °C) is not influenced by Er addition. But with 2 nm Er interlayer, the formed NiSi 2 is observed textured with preferred orientation of (1 0 0). During the formation of NiSi, Er segregates to the surface and little Er remains at the NiSi/Si(1 0 0) interface. Therefore, the Schottky barrier height of the formed NiSi/n-Si(1 0 0) contact is measured to be 0.635 ∼ 0.665 eV which is nearly invariable with different Er addition.

Interfacial reactions of 2-D periodic arrays of Ni metal dots on (0 0 1) Si

The fabrication of 2-D periodic arrays of nickel metal dots using polystyrene (PS) nanosphere lithography and the interfacial reactions of the Ni dot arrays on (0 0 1) Si substrates after different heat treatments have been investigated. The epitaxial NiSi 2 was detected to start growing in samples after annealing at 300 °C. As the annealing temperature was increased to 350–800 °C, only epitaxial NiSi 2 nanodot arrays were observed to form. The results revealed that the formation of epitaxial NiSi 2 is more favorable for the Ni metal dot arrays samples. The shape of the epitaxial NiSi 2 nanodot was found to be inverse pyramidal and the size of the silicide nanodots was measured to diminish with annealing temperature. Furthermore, amorphous SiO x nanowire arrays and single-crystalline Si nanowires were found to form in samples after annealing at 900 and 1100 °C, respectively. The results present the exciting prospect that other nanoscale metal silicide dot and nanowire arrays could be grown on the sub-100 nm pre-patterned Si substrates using the PS nanosphere lithography technique.

Ta/Ni/Ta multilayered ohmic contacts on n-type SiC

The interface formation, electrical properties and the surface morphology of multilayered Ta/Ni/Ta/SiC contacts were reported in this study. It was found that the conducting behavior of the contacts so fabricated is much dependent on the metal layer thickness and the subsequent annealing temperature. Auger electron spectroscopy (AES) and X-ray diffraction analyses revealed that Ni 2Si and TaC formed as a result of the annealing. The Ni atoms diffused downward to metal/SiC interface and converted into Ni 2Si layer in adjacent to the SiC substrate. The released carbon atoms reacted with Ta atoms to form TaC layer. Ohmic contacts with specific contact resistivity as low as 3 × 10 −4 Ω cm 2 have been achieved after thermal annealing. The formation of carbon vacancies at the Ni 2Si/SiC interface, probably created by dissociation of SiC and formation of TaC during thermal annealing, should be responsible for the ohmic formation of the annealed Ta/Ni/Ta contacts. The addition of Ta into the Ni metallization scheme to n-SiC restricted the accumulation of carbon atoms left behind during Ni 2Si formation, improving the electrical and microstructure properties.

Effectiveness of Self-Carbon and Titanium Capping Layers in NiSi formation with Ni Film Deposited by Atomic Layer Deposition

We firstly deposit a Ni film, directly after removing the native oxide, by atomic layer deposition (ALD) using a N2-hydroxyhexafluoroisopropyl-N1 (Bis-Ni) precursor, H2 as the reactant gas and Ar purging gas at 220 °C at a deposition rate of 1.25 Å/cycle. The as-deposited Ni and Ni3C films exhibited sheet resistances of 5 Ω/□ (sample B) and 18 Ω/□ (sample A), respectively. The formation of a Ni3C phase was easily controlled by varying the flow rate of the H2 reactant as above gas. A rapid thermal process (RTP) was then performed in a nitrogen ambient to form NiSi at different temperatures from 400 to 900 °C. We estimated the process window temperature for the formation of low-resistance NiSi to be between 600 and 800 °C for self-carbon and Ti capping layers, as below while in the case of only Ni deposition the process window temperature changes to 700 to 800 °C. The respective sheet resistances of the films were changed to 3 Ω/□ (sample B) and 4 Ω/□ (sample A) after silicidation. The reaction between Ni and Si could be increased by the self-carbon and Ti capping layers due to a decrease in the oxidation contamination and impurity incorporation in the Ni film during the silicidation process. This self-carbon capping layer is formed by the carbon-containing Ni3C phase, which segregates to the surface during the annealing process and forms a relatively thick surface layer. Additionally, this layer also protects the surface from oxygen contamination. The deposition of Ni by ALD and the improved formation of the low-resistance NiSi with increased temperature stability will be useful in the fabrication of advanced devices, such as nano meter-scale complementary metal oxide semiconductor (CMOS) or three-dimensional (3-D) devices.

Addressing materials and integration issues for NiSi silicide contact metallization in nano-scale CMOS devices

As the industry approaches sub-100 nm technology nodes, the trend is to replace cobalt silicide with nickel monosilicide (NiSi) since the use of NiSi for contact metallization shows a number of technological advantages, including its line-width independent low resistivity, less Si consumption and low thermal budget for its formation, and compatibility with Si 1 − x Ge x substrate technology. However, NiSi has not been considered as a serious candidate until recently mainly due to its poor morphological/thermal stability. Recent studies have shown that the morphological/thermal stability of NiSi can be enhanced substantially through the addition of a small amount of impurities, resulting in much improved silicided shallow junction integrity. Moreover, it has also been demonstrated that the addition of certain impurities, such as Ti, effectively reduces the sensitivity of NiSi formation to surface contaminants (e.g., residual interfacial oxide). This paper will present and discuss the details of these experimental results.

Formation and morphological stability of NiSi in the presence of W, Ti, and Ta alloying elements

The formation and degradation of NiSi films has been studied when elements with a high melting point (W, Ta, and Ti) were added to pure Ni films as an alloying element. In situ techniques were used to characterize the phase stability and the morphological stability of the NiSi layers. Depending on the concentration of the alloying element, two distinct regimes could be distinguished. First, the addition of a small quantity of an alloying element (e.g., &amp;lt;10 vol % W) had little impact on the formation of NiSi, but significantly improved the morphological stability. In some cases, the agglomeration temperature was increased by 100 °C. Second, for higher concentrations (e.g., &amp;lt;10 vol % W), no crystalline metal rich phases (NixSiywith x&amp;gt;y) could be observed prior to NiSi formation. Furthermore, a significant increase was observed of the apparent activation energy for NiSi formation.

CMOS Integration of Dual Work Function Phase-Controlled Ni Fully Silicided Gates (NMOS:NiSi, PMOS:$\hbox{Ni}_{2}\hbox{Si}$, and $\hbox{Ni}_{31}\hbox{Si}_{12}$) on HfSiON

The CMOS integration of dual work function (WF) phase-controlled Ni fully silicided (FUSI) gates on HfSiON was investigated. For the first time, the integration of NiSi FUSI gates on n-channel MOS (NMOS) and Ni31Si12 FUSI gates on p-channel MOS (PMOS) with good Vt control to short gate lengths (LG=50 nm, linear Vt of 0.49 V for NMOS, and -0.37 V for PMOS) is demonstrated. A poly-Si etch-back step was used to reduce the poly-Si height on PMOS devices, allowing for the linewidth-independent formation of NiSi on NMOS and Ni-rich silicides on PMOS with a two-step rapid thermal processing (RTP) silicidation process. The process space for the scalable formation of NiSi on NMOS and Ni2Si or Ni31 Si12 on PMOS devices was investigated. It was found that within the process window for linewidth-independent NiSi FUSI formation on 100-nm poly-Si NMOS devices, it is possible to control the silicide formation on PMOS devices by adjusting the poly-Si etch-back and RTP1 conditions to obtain either Ni2Si or Ni31Si12 FUSI gates. A reduction in the PMOS threshold voltage of 90 mV and improved device performance (18% Ion improvement at Ioff=100 nA/mum) was obtained for Ni 31Si12 compared to Ni2Si FUSI gates, as well as a Vt reduction of 350 mV when compared to a single WF flow using NiSi FUSI gates on PMOS

Tuning nickel silicide properties using a lamp based RTA, a heat conduction based RTA or a furnace anneal

For Ni silicidation a lamp based anneal, a furnace anneal and a heater based anneal have been used. Ni silicidation on unstructured Si wafers is characterized by means of sheet resistance, XRD and AES. In the second part of this paper the characterization is extended to product wafers using sheet resistance measurements, transistor performance and product yield to investigate the suitability of the different techniques and processes. We will show that all of the above techniques are suitable for NiSi formation if the thermal budget of the 1st anneal step is sufficient to react enough Ni to Ni rich silicide phases or NiSi. A 2nd anneal step after sequential Ni strip has been found to be of minor importance as the backend processing will finish the NiSi formation in case of Nickel rich phases being left after the Ni 1st anneal step. In the direct comparison of NiSi vs. CoSi the former showed equivalent or better yield and performance.

In situ study of the growth kinetics and interfacial roughness during the first stages of nickel–silicide formation

Metal silicides are widely used as contacts and interconnections in very large-scale integrated circuits. With the continuous scaling down of devices, the silicide thickness should be decreased and it becomes important to understand and control the first stages of the silicide formation. In this work, the first stages of the nickel–silicide formation in 40 nm Ni deposited on Si(1 0 0) wafer have been investigated, together with the development of the roughness linked to this formation. Both crystalline and amorphous phase formations have been followed using in situ X-ray reflectivity (XRR) and X-ray diffraction (XRD). In situ XRR allows to determine the number of formed layers and their individual thicknesses. Combining XRR and XRD, we show that the first nickel–silicide phase that is formed is certainly a metastable amorphous alloy which slightly increases before the formation of the crystalline Ni 2Si phase. We also suggest that the amorphous alloy crystallises to form the Ni 3Si 2 phase at the very beginning of the Ni 2Si formation. After crystallisation, this phase disappears in favour of Ni 2Si. In addition, the Ni 31Si 12 phase is observed before the end of the Ni 2Si formation and seems to have formed a layer.

Phase effects and short gate length device implementation of Ni fully silicided (FUSI) gates

A study of the implementation of Ni fully silicided (FUSI) gates to scaled devices is presented, addressing the issue of phase control at short gate lengths. A linewidth effect for Ni FUSI gates is found for non-optimized processes targeting NiSi, with formation of NiSi at long gate lengths and Ni-rich silicides at short gate lengths. This is attributed to Ni diffusion from areas surrounding the gates, resulting in a larger reacted Ni–Si ratio at short gate lengths. The linewidth dependence of the Ni FUSI phase results in an undesirable kink in the V t roll-off characteristics, due to the difference in effective work function between the Ni silicide phases, which is particularly large for HfSiON dielectrics. An optimized 2-step RTP silicidation process is shown to eliminate this problem allowing the formation of NiSi gates uniformly at all gate lengths. The application and scalability of Ni-rich silicides to PMOS devices is also demonstrated, as well as a scheme for CMOS integration of dual WF phase controlled FUSI (NiSi for NMOS and Ni-rich silicides for PMOS), using an etch back step to reduce the poly-Si height on PMOS electrodes before full silicidation.