Folded Cascode Amplifier Research Articles

0.8-V Enhanced bulk-driven folded cascode amplifier with high gain-bandwidth and slew rate

In this study, the proposed bulk-driven amplifier utilizes the bulk-driven flipped voltage follower together with the auxiliary amplifier to form the adaptive biasing input stage. The quasi-floating gate technique to build the class-AB output stage can enhance the gain-bandwidth, DC gain and slew rate of the conventional bulk-driven counterpart. Therefore, the current efficiency is improved. Simulation verification using a 0.18 μm CMOS technology, with a supply voltage of 0.8V, showed a DC gain of 76.6 dB, a CMRR of 106.6 dB, a gain-bandwidth product of 6.78 MHz and an average slew rate of 3.48 V/μs .

A high current efficiency multipath nested feedforward compensation technique for two-stage amplifier

In this paper, a high current efficiency two-stage amplifier using multipath nested feedforward compensation (MNFC) method is proposed. For the purpose of achieving the high current efficiency, the first stage of the amplifier uses a recycling folded cascode amplifier (RFC) and a nested small-gain stage is added between the two stages of the amplifier so that there are two paths in the feedforward path. This two-stage amplifier improves the phase margin (PM) and extends the gain bandwidth (GBW) by using the MNFC technique which can eliminate the non-dominant pole. The chip area of this two-stage MNFC amplifier which using 0.18μm CMOS process is 0.01272 mm2. The simulated and measured results shows that the phase margin(PM), DC gain, gain-bandwidth(GBW), average 1% settling time, slew rate- (SR-) and slew rate+ (SR+) is 72.7°, 104.4 dB, 4.29 MHz, 246.2 ns, 16 V/μs, and 6.15 V/μs, respectively, when the load capacitance is 120 pF. The supply voltage of this circuit is 1.8 V and the power consumption is 0.13 mW.

Research on the Polygraph: the CMOS Neural Amplifier

The polygraph is an effective piece of equipment to detect if the suspect is lying in order to track down the criminal. The paper simulates and sets up the host part of the polygraph in order to explain how the polygraph works and some fields to use it. And we successfully make a neural amplifier to show the way that the host amplifies neural signals, and has a low passband that can filter out high-frequency signals. The circuit has two parts the folded cascode amplifier DC gain is 64.56, the -3dB bandwidth is about 100kHz and the total current consumption is 4uA and the capacitive feedback amplifier passband gain is 40dB and the passband is from about 3Hz to 5kHz. It is of great value not only in the field of criminal investigation, but also in VR, artificial intelligence (AI), and mental health. Because it can record and let people observe human brain activity and emotional changes. What’s more, with its development of it, it can solve many small crimes automatically, which means police can have more time and energy to deal with difficult cases and society can be more stable.

A fully integrated overshoot-reduction low-dropout regulator based on hybrid NMOS/PMOS power transistors technique for SoC applications

This paper presents a fully integrated low dropout regulator (LDO) based on a hybrid NMOS/PMOS power transistors(HPT) technique. The HPT consists of a sub-power transistor NMOS and a main power transistor PMOS. Using the proposed HPT in the LDO, the high dc gain is achieved under heavy load condition and stability requirements are relaxed. With no extra power consumption, the proposed HPT provides a high charging rate at the gate of the main power transistor during a high-to-low load step. So the overshoot is reduced during load transient. Besides, the proposed LDO achieves high current efficiency by employing a current-recycling folded cascode amplifier. The post layout simulation results show that the LDO has a quiescent current of 7.4 μA and power supply rejection (PSR) less than −30 dB at 1 MHz. For large load transient of 100 μA to 20 mA and back to 100 μA with CL=100 pF and edge time of 1ns, the overshoot and undershoot are 148 mV and 284 mV respectively. The proposed LDO is designed in SMIC 0.18μm CMOS high-threshold-voltage process and occupies an area of 0.0252mm2.

Improved transconductance multipath recycling folded cascode amplifier

Improved transconductance multipath recycling folded cascode amplifier

Design procedure for noise and power optimisation of CMOS folded-cascode operational transconductance amplifier based on the inversion coefficient

Design procedure for noise and power optimisation of CMOS folded-cascode operational transconductance amplifier based on the inversion coefficient

Swarm intelligence-based mono and multi-objective methods for sizing preamplifier circuits for biomedical applications

In this article, various high-performance optimisation algorithms are used to optimise circuit parameters: firstly in a modified double ended differential amplifier for area optimisation; and secondly in an adaptive recycling folded cascode amplifier to deal with noise power trade-off. These circuits are used as preamplifiers in neural ailment such as epileptic seizure recording systems. Amongst the various analogue design challenges in a preamplifier, minimum area consumption and a good noise power trade-off are the necessary pre-requisites which require consideration. Traditional circuit sizing methods are tedious and prone to human error, so an alternative method is necessary to auto-size the circuit parameters. In this work, single objective algorithms are implemented to minimise area in the circuit, where the whale optimisation algorithm convergences earliest. While the multi-verse multi-objective optimisation algorithm shows good performance to maintain the noise power trade-off. These results are evaluated and compared in MATLAB and Cadence environment.

A Novel Current Density Based Design Approach of Low-Noise Amplifiers

The input-referred noise (IRN) is one of the most crucial performance indicators for the analog front-end (AFE) of neural recording devices. In this study, we present a novel design approach for a low-noise amplifier (LNA) based on the transistor optimization method in CMOS technology. Because flicker noise is predominant in neural recording applications, AFE has been designed to meet input-referred flicker noise specifications, whereas thermal noise contributions are monitored and controlled by flicker noise corner frequencies. Transistor optimization is accomplished using a lookup table that encapsulates its performance based on its current density. Initially, transistors are optimized based on the flicker noise performance; later, they may be further optimized based on their size, power consumption, transconductance, or thermal noise contribution. The proposed approach was validated by designing a folded-cascode amplifier with IRN ranging from 2 to 8 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{V}_{\text {rms}}$ </tex-math></inline-formula> . The results of the simulation show that the errors of our design methodology are less than 10%, which is less than those of the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$g_{m}/I_{D} $ </tex-math></inline-formula> and inversion coefficient methods. The proposed LNA achieves 2.1 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{V}_{\text {rms}}$ </tex-math></inline-formula> while consuming 0.83 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula> from a 1.2 V supply.

A new slew rate enhancement technique for operational transconductance amplifiers

AbstractThis paper presents a new symmetric slew rate enhancement (SRE) circuit suitable for operational transconductance amplifiers (OTAs). The proposed SRE circuit is composed of two auxiliary circuits which are automatically activated during fast signal transitions (slewing) by comparing the input and output signals. The auxiliary circuits pump required current in/out the load capacitance. In this way, the slew rate of the amplifier is significantly improved without any extra static power dissipation. The proposed technique can be applied to a variety of operational amplifiers. However, incorporating the proposed SRE circuit into a folded‐cascode amplifier (FCA) results in 7× slew rate improvement and 66.6% settling time reduction, while the frequency response and small‐signal operation of the amplifier are not degraded. The proposed SRE circuit is designed and simulated in a 0.13‐μm Complementary Metal‐Oxide‐Semiconductor (CMOS) technology. Post‐layout simulation results show that the circuit has a slew rate of 1465 V/μs and 9.75‐ns settling time for a total 3‐pF load capacitance while the power consumption is 841 μW at 1.2‐V supply voltage; that indicates 7‐time SR improvement with lower power dissipation compared to the conventional FCA and an excellent FOML of 6.26 ([V/μs] × pF/μA). Moreover, simulation results of the circuit for worst corner and temperature cases as well as 10% supply variation verify the robustness of the circuit against PVT changes.

A Novel OTA Architecture Exploiting Current Gain Stages to Boost Bandwidth and Slew-Rate

A novel architecture and design approach which make it possible to boost the bandwidth and slew-rate performance of operational transconductance amplifiers (OTAs) are proposed and employed to design a low-power OTA with top-of-class small-signal and large-signal figures of merit (FOMs). The proposed approach makes it possible to enhance the gain, bandwidth and slew-rate for a given power consumption and capacitive load, achieving more than an order of magnitude better performance than a comparable conventional folded cascode amplifier. Current mirrors with gain and a push–pull topology are exploited to achieve symmetrical sinking and sourcing output currents, and hence class-AB behavior. The resulting OTA was implemented using the 130 nm STMicroelectronics process, with a supply voltage of 1 V and a power consumption of only 1 µW. Simulations with a 200 pF load capacitance showed a gain of 92 dB, a unity-gain frequency of 141 kHz, and a peak slew-rate of 30 V/ms, with a phase margin of 80°, and good noise, PSRR and CMRR performance. The small-signal and large-signal current and power FOMs are the highest reported in the literature for comparable amplifiers. Extensive parametric and Monte Carlo simulations show that the OTA is robust against process, supply voltage and temperature (PVT) variations, as well as against mismatches.

Design of high gain and high bandwidth operational transconductance amplifier (OTA)

ABSTRACT A novel operational transconductance amplifier (OTA) having high gain and high bandwidth for high-speed analog communication techniques and precision filtering is designed in this paper. The designed OTA uses β-multiplier-based current biasing scheme with folded cascode amplifier scheme in order to improve the small signal models and the DC gain of circuit. The OTA design was carried out using TSMC 65 nm CMOS technology using Cadence Virtuoso tool with 1 V supply voltage and 10 pf capacitive load. The output DC gain was found to be approximately 75.3 dB. In addition, the unity gain frequency for the designed OTA was found to be around 200 MHz. Superior common mode rejection ratio, power supply rejection ratio and slew rates along with compact chip area and low power are other salient features of the designed OTA. The designed OTA can be employed in order to design high performance analog circuits like data converters, phase-locked loops, etc.

Design of a capacitor-less adaptively biased low dropout regulator using recycling folded cascode amplifier

This paper starts with a comprehensive analysis of the trade-offs among various performance parameters in conventional adaptively biased low dropout regulator (AB-LDO) and then proposes a new structure of output capacitor-less AB-LDO, employing recycling-folded-cascode(RFC) amplifier, to optimize the different trade-offs. With this special structure, the proposed AB-LDO finally achieves faster dynamic response, better linear and load regulation without increasing power consumption. In addition, cascode compensation is employed to bring a wider load range while ensuring loop stability. Finally, the proposed AB-LDO is implemented in 0.18μ m CMOS process and experimental results show that a low quiescent current (10–50.25μA), good load regulation of 0.48 mV/mA, undershoot of 92 mV and overshoot of 86 mV with high current efficiency of 99.95% have been achieved.

Optimal Sizing of Recycling Folded Cascode Amplifier for Low Frequency Applications Using New Hybrid Swarm Intelligence-Based Technique

ABSTRACT A new efficient design approach for sizing a high performance analog amplifier circuit namely the Recycling Folded Cascode (RFC) amplifier is presented. A RFC amplifier is an enhanced version of the conventional folded cascode amplifier and achieves better slew rate, gain, bandwidth, offset etc. for same area and power budget. Low frequency amplifiers such as biomedical or neural have a demanding requirement of low area, low power and low noise apart from meeting other optimal design specifications which have inherent trade-off amongst themselves. As a result, manual sizing becomes a computationally inefficient approach. Thus, swarm based optimization techniques have been employed to efficiently determine the optimal sizing for the RFC amplifier such that the area is minimized while meeting all the optimal design specifications considering the constraints. A new hybrid whale particle swarm optimization (HWPSO) algorithm is employed which takes advantage of the good qualities of both the whale algorithm and the PSO algorithm to optimize the area with less computational complexity. Simulations and statistical analysis have been performed and comparisons with other state of art algorithms reveals that HWPSO-based approach achieves a minimum circuit area of 21 µm2 with a mean Friedman’s statistical rank of 2.05 while meeting optimal design specifications for low frequency systems. Finally, validation with circuit design tool Cadence Virtuoso is done and pre as well as post layout analysis have been performed which further illustrated a close agreement with algorithmic results.

Optimal Sizing of Recycling Folded Cascode Amplifier for Low-Frequency Applications Using New Hybrid Swarm Intelligence-Based Technique

ABSTRACT A new efficient design approach for sizing a high-performance analog amplifier circuit namely the recycling folded cascode (RFC) amplifier is presented. An RFC amplifier is an enhanced version of the conventional folded cascode amplifier and achieves better slew rate, gain, bandwidth, offset, etc. for same area and power budget. Low-frequency amplifiers such as biomedical or neural have a demanding requirement of low area, low power, and low noise apart from meeting other optimal design specifications which have inherent trade-off among themselves. As a result, manual sizing becomes a computationally inefficient approach. Thus, swarm-based optimization techniques have been employed to efficiently determine the optimal sizing for the RFC amplifier such that the area is minimized while meeting all the optimal design specifications considering the constraints. A new hybrid whale particle swarm optimization (HWPSO) algorithm is employed which takes advantage of the good qualities of both the whale algorithm and the PSO algorithm to optimize the area with less computational complexity. Simulations and statistical analysis have been performed and comparisons with other state of art algorithms reveals that HWPSO-based approach achieves a minimum circuit area of 21 µm2 with a mean Friedman’s statistical rank of 2.05 while meeting optimal design specifications for low-frequency systems. Finally, validation with circuit design tool Cadence Virtuoso is done and pre- as well as postlayout analysis have been performed which further illustrated a close agreement with algorithmic results.

Design of PMOS and NMOS Input Folded Cascode Amplifier using 180nm SCL Technology Node for Low Power Application

This paper presents the details design and simulation of the Folded Cascode amplifier using Source-Coupled-Logic (SCL) technology node for both the P-Type Metal Oxide Semiconductor (PMOS) and N-Type Metal Oxide Semiconductor (NMOS) input. The different way to implement the circuit design for a given specification has clearly described including all the design equation has been presented. All the parameter like open loop gain, Unity Gain Bandwidth (UGB) and Phase Margin (PM) are compared for both the NMOS and PMOS input fully differential folded cascode op-amp circuit are discussed and finally we have got after performance analysis that NMOS input fully differential folded cascode op-amp is the best choice for low power high speed application like in pipeline Analog to Digital (ADC). The circuit has been simulated using cadence virtuoso tool in 0.18μm SCL technology node.

Analog IC Design Using Precomputed Lookup Tables: Challenges and Solutions

Design productivity remains an important aspect in the analog integrated circuit design industry, as growing competition and shorter design cycles pressure the traditional flow that involves time-consuming manual iterations in a circuit simulator. This paper describes innovations within an alternative framework that uses precomputed look-up tables (LUTs) to enable fast and accurate evaluation of circuit sizing scenarios without a simulator in the loop. It lets the designer explore and understand the design space boundaries in a systematic setting, thus supporting informed decision making and architectural innovation that is difficult to attain with fully automated, black-box sizing tools. Our discussion begins with an overview of the LUT-based design paradigm and its two primary variants: inverse design (finding design parameters that meet the specifications) and forward evaluation (sweeping design parameters to search the design space). In support of the latter, the core of our work focuses on improving the accuracy and speed of LUT access, enabling millions of queries within seconds on a standard computer. Large improvements over prior art are enabled using enhanced interpolation methods, which allow for a relatively large LUT grid spacing (hence small memory footprint) and yet accurate parameter lookup. We evaluate the efficacy of the proposed methods using two classical analog circuits, a bandgap reference and a folded cascode amplifier. In the bandgap example, we observe less than 1 ppm error between the LUT-predicted temperature coefficient and circuit simulation. In the folded-cascode example, one million design points are generated in only 4 seconds, providing the designer with useful maps that delineate the reachability of certain target specifications.

Design of Radiation Hardened Complementary Folded Cascode Amplifier

Sensitive Node Active Charge Cancellation technique (SNACC) is applied on the Complementary Folded Cascode amplifier (CFC) to study single event transients (SET) on this circuit. A Built-In-Detector (BID) is connected to the circuit to sense the variations of the currents in the op-amp and to represent their input and output characteristics. Two circuits are designed with and without SNACC, using UMC_CMOS_180nm process in cadence virtuoso environment. This work analyses to identify the effectiveness of Radiation Hardening By Design (RHBD) technique by comparing radiation sensitive and radiation hardened CFC amplifier.

A High Current Efficiency Two-Stage Amplifier With Inner Feedforward Path Compensation Technique

A high current efficiency two-stage amplifier with inner feedforward path compensation (IFPC) technique is proposed in this paper. To improve the current utilization of the whole structure, the recycling folded cascode amplifier (RFC) is adopted as the first stage, and the inner feedforward path which is used to eliminate the non-dominant pole is composed of the input stage of RFC and the tail current transistor of the second stage amplifier. By using the IFPC technique, the proposed amplifier achieves an extended gain-bandwidth (GBW) and sufficient phase margin (PM) compared to that of the two-stage amplifier using single Miller compensation (SMC). Moreover, this compensation technique avoids extra power consumption since it does not require additional circuits. The proposed two-stage IFPC amplifier was fabricated in a $0.18~\mu \text{m}$ CMOS technology and the chip area of it is about $0.076mm^{2}$ . The simulated open loop AC response shows the DC gain, GBW, and PM are 130dB, 2.01MHz, and 58.3°, respectively. Measured results of transient response show when driving a 120pF load capacitance, the proposed amplifier achieves 368ns average 1% settling time, and about 1.56V/ $\mu \text{s}$ average slew rate (SR). Note that under the condition of 1.8V power supply, the power consumption is only $108\mu W$ , proving the proposed two-stage IFPC amplifier can achieve high current efficiency while maintaining stability.

128 mA CMOS LDO with 108 db PSRR at 2.4 MHz frequency

A low dropout (LDO) voltage regulator with high power supply rejection ratio (PSRR) and low temperature coefficient (TC) is presented in this paper. Large 1µF off-chip load capacitor is used to achieve the high PSRR. However, this decreases the gain and pushes the LDO’s output pole to lower frequency causing the circuit to become unstable. The proposed LDO uses rail-to-rail folded cascode amplifier to compensate the gain and stability problems. 2nd order curvature characteristic is used in bandgap voltage reference circuit that is applied at the input of the amplifier to minimize the TC. The characteristic is achieved by implementing MOSFET transistors operate in weak and strong inversions. The LDO is designed using 0.18µm CMOS technology and achieves a constant 1.8V output voltage for input voltages from 3.2V to 5V and load current up to a 128mA at temperature between -40°C to 125°C. The proposed LDO is targeted for RF application which has stringent requirement on noise rejection over a broad range of frequency.

CMOS Fourth-order Delta-sigma Modulator with a Single Reconfigurable Fully Differential Amplifier

This paper describes a CMOS 4SUPth/SUP-order delta-sigma modulator with only one amplifier for the application of bio signal processing. The proposed modulator employed only a single reconfigurable fully differential amplifier which becomes either the folded-cascode amplifier or two stage operational one, depending on the load capacitance. The modulator is implemented with 180 ㎚ CMOS standard process. The measurement results demonstrate the peak SNDR of 72.8 ㏈ and the ENOB of 11.8 bits with an input signal frequency of 250 ㎐, a sampling frequency of 256 ㎑, an input signal bandwidth of 1 ㎑, and an oversampling rate of 128. The power dissipated is measured to be 356 ㎼ (analog power of 302 ㎼ and digital power of 54 ㎼). FOM1 and FOM2 are calculated to be 49.6 pJ/step and 155 ㏈, respectively.