A fully integrated overshoot-reduction low-dropout regulator based on hybrid NMOS/PMOS power transistors technique for SoC applications

Abstract

This paper presents a fully integrated low dropout regulator (LDO) based on a hybrid NMOS/PMOS power transistors(HPT) technique. The HPT consists of a sub-power transistor NMOS and a main power transistor PMOS. Using the proposed HPT in the LDO, the high dc gain is achieved under heavy load condition and stability requirements are relaxed. With no extra power consumption, the proposed HPT provides a high charging rate at the gate of the main power transistor during a high-to-low load step. So the overshoot is reduced during load transient. Besides, the proposed LDO achieves high current efficiency by employing a current-recycling folded cascode amplifier. The post layout simulation results show that the LDO has a quiescent current of 7.4 μA and power supply rejection (PSR) less than −30 dB at 1 MHz. For large load transient of 100 μA to 20 mA and back to 100 μA with CL=100 pF and edge time of 1ns, the overshoot and undershoot are 148 mV and 284 mV respectively. The proposed LDO is designed in SMIC 0.18μm CMOS high-threshold-voltage process and occupies an area of 0.0252mm2.