Floating-point Matrix Multiplication Research Articles

A High-Speed Floating Point Matrix Multiplier Implemented in Reconfigurable Architecture

Matrix multiplication is a fundamental operation in computational applications across various domains. This paper introduces a novel reconfigurable co-processor that enhances the efficiency of matrix multiplication by concurrently executing addition and multiplication operations upon matrix elements of different sizes. The proposed design aims to reduce computation time and improve efficiency for matrix multiplication equations. Experimental evaluations were conducted on matrices of different sizes to demonstrate the effectiveness of the processor. The results reveal substantial improvements in both time and efficiency when compared to traditional approaches. The reconfigurable transformation processor harnesses parallel processing capabilities, enabling the simultaneous execution of addition and multiplication operations by partitioning input matrices into smaller submatrices and performing parallel computations, thus the processor achieves faster results. Additionally, the design incorporates configurable arithmetic units that dynamically adapt to matrix characteristics, further optimizing performance. The experimental evaluations provide evidence of reduction in computation time and improvement in efficiency. present significant benefits over traditional sequential methods. This makes this co-processor ideally fit for domains that require intensive linear algebra computations such as computer vision, machine learning, and signal processing.

Templatized Fused Vector Floating-Point Dot Product for High-Level Synthesis

Machine-learning accelerators rely on floating-point matrix and vector multiplication kernels. To reduce their cost, customized many-term fused architectures are preferred, which improve the latency, power, and area of the designs. In this work, we design a parameterized fused many-term floating-point dot product architecture that is ready for high-level synthesis. In this way, we can exploit the efficiency offered by a well-structured fused dot-product architecture and the freedom offered by high-level synthesis in tuning the design’s pipeline to the selected floating-point format and architectural constraints. When compared with optimized dot-product units implemented directly in RTL, the proposed design offers lower-latency implementations under the same clock frequency with marginal area savings. This result holds for a variety of floating-point formats, including standard and reduced-precision representations.

Implementation of Vedic Multiplier and Floating Point Matrix Multiplier in Image Compression Applications

It is implemented into low Power Verilog Architecture to the area for digital images Process application, In the matrix multiplications are one of the key arithmetically operations. And the constructed into VLSI architecture for Low Power, High Speed & Lowarea, Matrices Multiplications designed into become rare. In the projects, is a simple work of fiction in Verilog architectures with Floating point matrix multiplier be presents. The designs into consider as Pseudo codes with the matrix multiplications, CSD multiplication algorithms with power reductions, Convention floating points as number formatting & Pipeline concept with as improves speeds. In the Floating point matrix multiplier design as appropriate with anyone orbitrary sizes of the matrix among the followed matrices rule. It is designed may also gives as higher precision outputs. The simulation result is perfect matched into the MATLAB result.

Binary Outer Product Expansion of Convolutional Kernels

Convolutional neural networks (CNNs) have found great success in many artificial intelligence applications. At the heart of a CNN is the operation of convolution between multi-channel data and learned kernels. It is usually implemented as a floating-point large matrix multiplication, a major bottleneck of computational speed and memory usage. In this paper, we propose a binary outer product expansion (BOPE) method to represent a kernel matrix or tensor as a weighted sum of the outer products between binary vectors of values +1 or −1. This allows for network compression and simplified computation at the same time. Our theoretical analysis shows such a decomposition converges to the original matrix given a sufficient number of binary vectors. We present computational methods to estimate outer product weights using either optimized or random binary base vectors. Significant data compression can be achieved for a highly redundant matrix, since weights and binary vectors require less storage than array elements. In addition, most floating-point multiplication in matrix convolution can be replaced by addition and binary XOR, lessening computation and memory requirements. We propose a compact convolutional layer in which highly redundant convolutional kernels are projected onto binary vectors, and represented as a weighted sum of outer products. It is shown that the number of weights in AlexNet, VGG−19 and ResNet-50 can be reduced 3.45, 6.87 and 2.95 times respectively with less than a 1% loss in the top-1 and top-5 classification accuracy on ImageNet, and MobileNetV2 can be reduced 2.31 times with a 2% loss. Compared to the standard CNN, this compact convolutional network has fewer trainable weights, is better regularized, and is easier to train from fewer training samples. Therefore, it is particularly suited for devices with limited computation, memory, and battery power.

Design and Evaluation of Floating point Matrix Operations for FPGA based system design

Matrices are considered as the heart of different applications in several scientific fields such as solving electrical circuits, image processing, optimization, control systems, quantum mechanics and many more. Matrix multiplication and inverse of a matrix are considered as the two computationally expensive matrix operations. In this paper, design and evaluation of different floating-point matrix multiplication architectures/approaches and floating-point matrix inversion using model based design for FPGAs is proposed, which is an outcome of a funded project. Details about the scaling of proposed work for larger matrix sizes is also reported in the paper. The performance of proposed matrix operations is evaluated by hardware implementation of the models on a Zynq 7000 FPGA based ZED board and the results are reported.

Design and Analysis of Single and Double Precision Floating Point Matrix Multiplier using Partition Multiplier Method

International Journal of Computer Sciences and Engineering (A UGC Approved and indexed with DOI, ICI and Approved, DPI Digital Library) is one of the leading and growing open access, peer-reviewed, monthly, and scientific research journal for scientists, engineers, research scholars, and academicians, which gains a foothold in Asia and opens to the world, aims to publish original, theoretical and practical advances in Computer Science,Information Technology, Engineering (Software, Mechanical, Civil, Electronics & Electrical), and all interdisciplinary streams of Computing Sciences. It intends to disseminate original, scientific, theoretical or applied research in the field of Computer Sciences and allied fields. It provides a platform for publishing results and research with a strong empirical component. It aims to bridge the significant gap between research and practice by promoting the publication of original, novel, industry-relevant research.

Binary neural networks for speech recognition

Recently, deep neural networks (DNNs) significantly outperform Gaussian mixture models in acoustic modeling for speech recognition. However, the substantial increase in computational load during the inference stage makes deep models difficult to directly deploy on low-power embedded devices. To alleviate this issue, structure sparseness and low precision fixed-point quantization have been applied widely. In this work, binary neural networks for speech recognition are developed to reduce the computational cost during the inference stage. A fast implementation of binary matrix multiplication is introduced. On modern central processing unit (CPU) and graphics processing unit (GPU) architectures, a 5–7 times speedup compared with full precision floatingpoint matrix multiplication can be achieved in real applications. Several kinds of binary neural networks and related model optimization algorithms are developed for large vocabulary continuous speech recognition acoustic modeling. In addition, to improve the accuracy of binary models, knowledge distillation from the normal full precision floating-point model to the compressed binary model is explored. Experiments on the standard Switchboard speech recognition task show that the proposed binary neural networks can deliver 3–4 times speedup over the normal full precision deep models. With the knowledge distillation from the normal floating-point models, the binary DNNs or binary convolutional neural networks (CNNs) can restrict the word error rate (WER) degradation to within 15.0%, compared to the normal full precision floating-point DNNs or CNNs, respectively. Particularly for the binary CNN with binarization only on the convolutional layers, the WER degradation is very small and is almost negligible with the proposed approach.

Analysis of Area and Delay for Floating Point Matrix Multiplication

In this paper, a new area and delay minimization architecture is proposed for rank-1 update matrix–matrix multiplication whose inputs are double precision floating point number. The architecture design is based on pipelined multiplication which handles matrix of arbitrary sizes; the processing data are stored in dedicated on-chip BRAM. This minimization is introduced to designers as a trade-off between bandwidth and local memory. Analysis is presented for the design parameters optimal choice. In addition, Vedic matrix multiplication architecture is given in order to explore the variations in power, delay and memory. The hardware architecture is described in Verilog HDL synthesized for a family virtex-6 and device xc6vlx240t FPGA, which scale more than 40 processing elements. Various parameters like LUTs, Slices, bonded IOBs, frequency, DSP48E1S, delay, Power, CPU Completion time and Memory usage are analysed. Rank 1 update consumes a power of 2.520 watt and has a delay of 5.277 ns respectively. Comparing other rank-1 multiplication methods our proposed algorithms uses 15% less area resources and improves the delay in 12%.

High-Level Synthesis Optimization for Blocked Floating-Point Matrix Multiplication

In the last decade floating-point matrix multiplication on FPGAs has been studied extensively and efficient architectures as well as detailed performance models have been developed. By design these IP cores take a fixed footprint which not necessarily optimizes the use of all available resources. Moreover, the low-level architectures are not easily amenable to a parameterized synthesis. In this paper high-level synthesis is used to fine-tune the configuration parameters in order to achieve the highest performance with maximal resource utilization. An\ exploration strategy is presented to optimize the use of critical resources (DSPs, memory) for any given FPGA. To account for the limited memory size on the FPGA, a blockoriented matrix multiplication is organized such that the block summation is done on the CPU while the block multiplication occurs on the logic fabric simultaneously. The communication overhead between the CPU and the FPGA is minimized by streaming the blocks in a Gray code ordering scheme which maximizes the data reuse for consecutive block matrix product calculations. Using highlevel synthesis optimization, the programmable logic operates at 93% of the theoretical peak performance and the combined CPU-FPGA design achieves 76% of the available hardware processing speed for the floating-point multiplication of 2K by 2K matrices.

Evaluating the Performances of Double Precision Floating Point Matrix Multiplication

Most of the DSP applications make matrix multiplication as basic kernel. We proposed an algorithm for IEEE 754 Double Precision floating point matrix multiplication (Level-3 BLAS). The design is based on rank-2update scheme, which handles matrix of arbitrary sizes and is centred on pipelined multiplication the matrices are stored in dedicated on-chip BRAM; the aim of this investigation is to advance the performance in terms of delay and area. The hardware architectures are described in Verilog HDL synthesized for a family virtex5 and device SX240T FPGA, which scale more than 40 processing elements. Various parameters like LUTs, Slices, bonded IOBs, frequency, delay, Power, CPU Completion time and Memory usage are analysed. Rank-2 scheme consumes a power of 0.382 watt and has a delay of 7.582 ns. The proposed algorithms consume 10% less area and 8% less delay than the rank-1 update scheme.

Fast description and synthesis of control-dominant circuits

General purpose processors, graphics processing units (GPUs) and field-programmable gate-arrays (FPGAs) compete and collaborate to offer ever increasing performances. Nevertheless, despite fruitful decades of research, FPGA are still a lot more difficult to exploit than processor-based approaches. It is today possible to automatically map C/C++/SystemC algorithms into circuits. However, exploiting fine grain parallelism for control dominant applications is still reserved to highly specialized people in hardware design. This paper presents the application of our synchronized-transfer-level hardware design methodology to the implementation of pipelined floating point operators. The methodology builds on a hardware description language for which the designer manages dynamic connections between data token sources and sinks. A compiler automates the generation and the optimization of the synchronization logic, whose low-level complexity is thus hidden to the designer. Applied to the design of a floating-point matrix multiplication hardware accelerator, the proposed methodology leads to similar computing performances than the dedicated designs reported in the literature but within shorter design times (hours instead of days), simpler source code and no need for advanced hardware design skills.

Analysis of Blocking and Scheduling for FPGA-Based Floating-Point Matrix Multiplication Analyse du blocage et de l’ordonnancement d’une multiplication matricielle à virgule flottante sur un FPGA

This paper considers blocking and scheduling for the design and implementation of field-programmable gate array (FPGA)-based floating-point parallel matrix multiplication in the presence of a memory hierarchy. For high performance, on-chip memory holds data that are reused when the computation is divided into blocks, and multiple arithmetic units perform independent operations within each block in parallel. The first contribution of this paper is a detailed analysis of the design space to characterize performance based on the amount of on-chip memory used and the approaches considered for blocking and scheduling of the computation. A comparison is also made to prior work with a unified view. The second contribution is a flexible high-performance implementation for the Altera Stratix IV EP4SGX530C2 FPGA with an interface to external double-data-rate synchronous dynamic RAM (DDR2 SDRAM) memory. Various configuration options support optimization of different objectives, and the resulting configurations have been verified in simulation and in hardware. For double-precision floating-point, a performance of 16 giga-floating-point operations per second (GFLOPS) is achievable with 64 arithmetic units at 160 MHz.

An Optimized Floating-Point Matrix Multiplication on FPGA

An Optimized Floating-Point Matrix Multiplication on FPGA

FPGA accelerator for floating-point matrix multiplication

This study treats architecture and implementation of a field-programmable gate array (FPGA) accelerator for double-precision floating-point matrix multiplication. The architecture is oriented towards minimising resource utilisation and maximising clock frequency. It employs the block matrix multiplication algorithm which returns the result blocks to the host processor as soon as they are computed. This avoids output buffering and simplifies placement and routing on the chip. The authors show that such architecture is especially well suited for full-duplex communication links between the accelerator and the host processor. The architecture requires the result blocks to be accumulated by the host processor; however, the authors show that typically more than 99% of all arithmetic operations are performed by the accelerator. The implementation focuses on efficient use of embedded FPGA resources, in order to allow for a large number of processing elements (PEs). Each PE uses eight Virtex-6 DSP blocks. Both adders and multipliers are deeply pipelined and use several FPGA-specific techniques to achieve small area size and high clock frequency. Finally, the authors quantify the performance of accelerator implemented in Xilinx Virtex-6 FPGA, with 252 PEs running at 403 MHz (achieving 203.1 Giga FLOPS (GFLOPS)), by comparing it to double-precision matrix multiplication function from MKL, ACML, GotoBLAS and ATLAS libraries executing on Intel Core2Quad and AMD Phenom X4 microprocessors running at 2.8 GHz. The accelerator performs 4.5 times faster than the fastest processor/library pair.

Scalable and Modular Algorithms for Floating-Point Matrix Multiplication on Reconfigurable Computing Systems

The abundant hardware resources on current reconfigurable computing systems provide new opportunities for high-performance parallel implementations of scientific computations. In this paper, we study designs for floating-point matrix multiplication, a fundamental kernel in a number of scientific applications, on reconfigurable computing systems. We first analyze design trade-offs in implementing this kernel. These trade-offs are caused by the inherent parallelism of matrix multiplication and the resource constraints, including the number of configurable slices, the size of on-chip memory, and the available memory bandwidth. We propose three parameterized algorithms which can be tuned according to the problem size and the available hardware resources. Our algorithms employ linear array architecture with simple control logic. This architecture effectively utilizes the available resources and reduces routing complexity. The processing elements (PEs) used in our algorithms are modular so that it is easy to embed floating-point units into them. Experimental results on a Xilinx Virtex-ll Pro XC2VP100 show that our algorithms achieve good scalability and high sustained GFLOPS performance. We also implement our algorithms on Cray XD1. XD1 is a high-end reconfigurable computing system that employs both general-purpose processors and reconfigurable devices. Our algorithms achieve a sustained performance of 2.06 GFLOPS on a single node of XD1

Design and implementation of a scalable low-cost shared-memory multiprocessor system using IBM compatible PCs

The design and implementation of a low-cost shared-memory multiprocessor system using a number of 386 PCs connected through a common bus is presented. Throughout the design, emphasis is placed on using standard PC components, particularly for the microprocessors and the shared memory, which results in significantly lower prices, at the cost of using components not designed for this specific application. The cost of the entire add-on components to the system is only AUD $300 and this is further facilitated by the use of features already available in standard PC operating systems and programming environments. The system offers encouraging results for benchmark problems on block transfers and floating point matrix multiplication. An effort has also been made to include sufficient flexibility in the design to allow for future modifications and upgrades.