Abstract
Most of the DSP applications make matrix multiplication as basic kernel. We proposed an algorithm for IEEE 754 Double Precision floating point matrix multiplication (Level-3 BLAS). The design is based on rank-2update scheme, which handles matrix of arbitrary sizes and is centred on pipelined multiplication the matrices are stored in dedicated on-chip BRAM; the aim of this investigation is to advance the performance in terms of delay and area. The hardware architectures are described in Verilog HDL synthesized for a family virtex5 and device SX240T FPGA, which scale more than 40 processing elements. Various parameters like LUTs, Slices, bonded IOBs, frequency, delay, Power, CPU Completion time and Memory usage are analysed. Rank-2 scheme consumes a power of 0.382 watt and has a delay of 7.582 ns. The proposed algorithms consume 10% less area and 8% less delay than the rank-1 update scheme.
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