Abstract
Matrices are considered as the heart of different applications in several scientific fields such as solving electrical circuits, image processing, optimization, control systems, quantum mechanics and many more. Matrix multiplication and inverse of a matrix are considered as the two computationally expensive matrix operations. In this paper, design and evaluation of different floating-point matrix multiplication architectures/approaches and floating-point matrix inversion using model based design for FPGAs is proposed, which is an outcome of a funded project. Details about the scaling of proposed work for larger matrix sizes is also reported in the paper. The performance of proposed matrix operations is evaluated by hardware implementation of the models on a Zynq 7000 FPGA based ZED board and the results are reported.
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