Floating-gate Technique Research Articles

A new gate current measurement technique for the characterization of hot-carrier induced degradation in MOSFETs

A new gate current measurement method is proposed for the characterization of hot-carrier induced degradation in MOSFETs. This method requires a much shorter measurement time to obtain the I g- V g curve of the MOSFETs as compared to the conventional floating-gate technique, and therefore has a lower risk of degrading the test device during the measurement process. This paper also discusses the appropriateness of using a high-frequency (100 kHz–1 MHz) measurement to obtain the gate capacitance of MOSFETs when applying the floating-gate technique to obtain the device gate current.

A coupled study by floating-gate and charge-pumping techniques of hot carrier-induced defects in submicrometer LDD n-MOSFET's

The creation of defects by hot-carrier effect in submicrometer (0.85- mu m) LDD n-MOSFETs is analyzed by the floating-gate and the charge-pumping techniques. It is emphasized that the floating-gate technique is an attractive tool for characterizing the oxide traps located in the drain-gate overlap region, near the oxide spacer of the LDD structures. This work gives new insight into the creation of acceptorlike oxide traps which are electrically active only after electron injection phases. These defects are generated in the whole stress gate bias range (from V/sub d//8 to V/sub d/) by hot-hole and/or hot-electron injections, and their generation rates (10/sup -9/ and 10/sup -2/ for electron and hole injections, respectively) are one decade greater than for the interface state generation. Two-dimensional simulations show that they are mainly responsible for the I/sub d/-V/sub g/ degradation of the LDD MOSFETs, and that the trap concentrations deduced from charge-pumping experiments are consistent with the I/sub d/-V/sub g/ degradation. >

Charging and discharging properties of electron traps created by hot-carrier injections in gate oxide of n-channel metal oxide semiconductor field effect transistor

The charging and discharging properties of electron traps created by hot-carrier injections in the thin gate oxide of n-channel metal oxide semiconductor transistors are analyzed by means of the effects that charge state transitions induce on the low-level gate current (lower than 1 pA) of the transistor. This current is measured by a very senstive floating-gate technique [F.H. Gaensslen and J.M. Aitken, IEEE Electron. Device Lett. EDL-1, 231 (1980)]. Two traps with electron capture cross sections of the order of 10−14 and 10−15 cm2 are analyzed which are linked with optical and field-dependent measurements of electron emission properties. Thermal and optical ionization energies of these defects are determined at ≊1.7±0.2 and ≊3.0±0.5 eV, respectively. Comparison with theory suggests that Si dangling bonds or oxygen vacancy in the oxide should be the defects created by hot-carrier injections.

Characterization of oxide trap and interface trap creation during hot-carrier stressing of n-MOS transistors using the floating-gate technique

A technique has been developed to differentiate between interface states and oxide trapped charges in conventional n-channel MOS transistors. The gate current is measured before and after stress damage using the floating-gate technique. It is shown that the change in the I/sub g/-V/sub g/ characteristics following the creation and filling of oxide traps by low gate voltage stress shows distinct differences when compared to that which occurs for interface trap creation at mid gate voltage stress conditions, permitting the identification of hot-carrier damage through the I/sub g/-V/sub g/ characteristics. The difference is explained in terms of the changes in occupancy of the created interface traps as a function of gate voltage during the I/sub g/-V/sub g/ measurements.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Properties of hot carrier induced traps in MOSFETs characterized by the floating-gate technique

A measurement of the low-level (10 −17-10 −12 A) electronic gate current in Si MOSFETs by the floating-gate technique is presented as a powerful tool to characterize the properties of defects induced in MOSFETs by hot-carrier-effects. This paper discusses the use of this technique to analyze: (i) the creation of new traps in the oxide in the gate-drain overlap region; (ii) the determination of the carrier capture properties of these traps; (iii) their localization; and (iv) their nature (interface states vs oxide traps). Finally, it is shown how the floating-gate technique is able to detect process-related reliability problems. The paper emphazises the new possibilities offered by the floating-gate technique compared to a standard characterization technique like charge-pumping.

Measurement of very low tunneling current density in SiO/sub 2/ using the floating-gate technique

The floating-gate technique for measuring extremely low gate currents has been adapted to the measurement of Fowler-Nordheim tunneling currents in metal-oxide-semiconductor (MOS) capacitors. Using a special structure consisting of an MOS capacitor and a monitor transistor sharing a common-gate electrode, it has proved possible to measure tunneling current densities as low as 2*10/sup -13/ A/cm/sup 2/. The Fowler-Nordheim tunneling relationship was found to be obeyed over the entire measurable range of current density. >

Application of the floating-gate technique to the study of the n-MOSFET gate current evolution due to hot-carrier aging

The evolution of the gate current-voltage (I/sub g/-V/sub gs/) characteristics of n-MOSFETs induced by DC stresses at different gate voltage over drain voltage (V/sub ds/) ratios is studied by the floating-gate (FG) measurement technique. It is shown that the I/sub g/-V/sub gs/ curves are always lowered after aging, and that the kinetics are dependent on the aging conditions. A time power law is representative of the V/sub gs/=V/sub ds/ case. It is demonstrated that electron traps are created in the oxide by both hot-hole and hot-electron injection stresses. They are not present in the devices before aging. They can be easily charged and discharged by short electron and hole injections, respectively.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Direct observation of the influence of the electron-electron interaction on the chemical potential of a 2D electron gas

Using the floating gate technique, we have found that for the two-dimensional electron gas in a quantized magnetic field the rate of increase of the chemical potential with magnetic field can be much higher than the maximum value for a noninteracting gas. This corresponds to the negative sign of the thermodynamic density of states. The effect can be explained by the interactions between electrons and allows us to estimate the energy of the electron-electron interaction in Si inversion layers.

Floating gate technique as a thermodynamic probe of two-dimensional electron systems

Measurements of the chemical potential as a function of the magnetic field at low temperatures reveal the density of states. We apply this to Ga,AlAs heterostructures.

Observation of hot-hole injection in NMOS transistors using a modified floating-gate technique

A modified floating-gate technique for measuring small gate currents in MOSFET's with very high resolution (0.01 fA) is described. Using this technique, gate oxide currents due to hot-carrier injection are measured in n-channel MOSFET's. The conventional negative channel hot-electron gate oxide current is observed near V_{g} = V_{d} and a small positive gate current occurs at low V g . We argue that the dependencies of this small positive current on V g and gate length, together with results from a separate floating-source experiment, are consistent only with hot-hole injection.

Floating-gate technique applied to two-dimensional systems.

We report a new technique of using a floating-gate capacitive structure to measure the electrochemical potential difference between a reference conductor and the material in question as a function of some external parameter. It is illustrated by measurements on two two-dimensional systems: Si metal-oxide-semiconductor structures and (Ga,Al)As:GaAs heterostructures.

DIFMOS—A floating-gate electrically erasable nonvolatile semiconductor memory technology

Electrically alterable read-only memories (EAROM's) or reprogrammable read-only memories (RPROM's) can be fabricated using a single-level metal-gate p-channel MOS technology with all conventional processing steps. Given the acronym DIFMOS for dual-injector floating-gate MOS, this technology utilizes the floating-gate technique for nonvolatile storage of data. Avalanche injection of hot electrons through gate oxide from a special injector diode in each bit is used to charge the floating gates. A second injector structure included in each bit permits discharge of the floating gate by avalanche injection of holes through gate oxide. The overall design of the DIFMOS bit is dictated by the physical considerations required for each of the avalanche injector types. The end result is a circuit technology which can provide fully decoded bit-erasable EAROM-type circuits using conventional manufacturing techniques.