Floating Gate NAND Flash Memory Research Articles

Adaptive Artificial Neural Network-Coupled LDPC ECC as Universal Solution for 3-D and 2-D, Charge-Trap and Floating-Gate NAND Flash Memories

Adaptive artificial neural network (ANN)coupled low-density parity-check (LDPC) error-correcting code (ECC) (ANN-LDPC ECC) is proposed to increase acceptable errors for various NAND flash memories. The proposed ANN-LDPC ECC can be the universal solutions for 3-D and 2-D, charge-trap and floating-gate NAND flash memories. In 3-D NAND flash, lateral charge migration, vertical charge de-trap, inter floating-gate capacitive coupling noise, and inter word-line variations cause errors. On the other hand, in 2-D NAND flash, the charge de-trap and the harsh inter floating-gate capacitive coupling of adjacent word-lines and bit-lines cause errors. To solve these reliability problems, the proposed ANN automatically and adaptively compensates for complex memory cell errors. Moreover, the proposed ANNLDPC can reproduce the dynamic endurance and data-retention time dependence of errors. In addition, this paper evaluates the impacts of the chip-to-chip variations on the proposed ANN-LDPC. The proposed ANN-LDPC is implemented in the storage controller and can precisely and adaptively estimate bit-error rate (BER) and log-likelihood ratio (LLR). By using the precise LLR, LDPC decoder effectively corrects errors. As a result, ANN-LDPC extends the acceptable data-retention time by over 76× and 45× compared with conventional Bose-Chaudhuri-Hocquenghem (BCH) ECC in 3-D and 2-D triple-level cell (TLC) NAND flash memories, respectively.

Characterizing 3D Floating Gate NAND Flash

In this paper, we characterize a state-of-the-art 3D floating gate NAND flash memory through comprehensive experiments on an FPGA platform. Then, we present distinct observations on performance and reliability, such as operation latencies and various error patterns. We believe that through our work, novel 3D NAND flash-oriented designs can be developed to achieve better performance and reliability.

A new erase method for scaled NAND flash memory device

A suitable bird-beak thickness is crucial to the cell reliability. However, the process control for bird-beak thickness in the edge region is very difficult. A new erase method is proposed in this work to modulate the electron tunneling region of 40nm floating gate NAND flash memory device. The erasing electron can move to gate center from gate edge under back bias at 0.3V/−0.8V. The Fowler-Nordheim (FN) current of erase operation distributes on the whole channel region, not located at the gate edge region. Results show that the proposed method can improve cell reliability about 33%. TCAD analysis is employed to explain and prove the mechanism. This new erase method is promising for scaled NAND flash memory.

Investigation of Hysteresis Phenomenon in Floating-Gate NAND Flash Memory Cells

The origin of hysteresis phenomenon in floating-gate (FG) NAND flash memory cells in cell strings was identified. To analyze the hysteresis phenomenon in FG NAND flash memory strings, pulsed $I$ – $V$ and fast transient bitline current ( $I_{\textrm {BL}}$ ) measurements were used in this study. It was found that the hysteresis phenomenon is originated by traps in the bottom oxide of the oxide/nitride/oxide interpoly dielectric. When the control-gate voltage ( $V_{\textrm {CG}}$ ) of a selected cell in the erased state is 5 V, the electrons in the FG are captured in the traps, because the trap energy level ( $E_{T}$ ) is lower than the Fermi energy level ( $E_{F}$ ) of the FG ( $E_{T}- E_{F} ), which leads to the increase in $I_{\textrm {BL}}$ . When the $V_{\textrm {CG}}$ of the selected cell is $V_{\textrm {th}}$ , trapped electrons are emitted to the FG, because the $E_{T}$ is higher than the $E_{F}$ of the FG ( $E_{T}- E_{F}>0$ ), which leads to the decrease in $I_{\textrm {BL}}$ .

Unified Endurance Degradation Model of Floating Gate NAND Flash Memory

Endurance degradation model applicable to the broad node range of floating-gate NAND flash memory is proposed for the first time. The model is based on generation of the trapped charge, which follows nonuniform spatial distribution of the erase tunneling current. A special Topology Computer-Aided Design (TCAD) simulation technique to simulate program/erase cycling is described in detail. Simulation parameters, determining change of midgap voltage (vertical centroid position and maximum value of the trapped charge) are extracted from the reference device with known endurance curve, and these are applied to the target cell. The endurance characteristics predicted by the model are verified to reproduce measured endurance curves for design rules of 27, 42, and 90 nm. Several factors affect midgap voltage change-area occupied by trapped charge; vertical position of charge centroid; separation of trapped charge distribution and tunnel current. A 3-D TCAD simulation allows accurate consideration of the given factors, resulting in good match between measured and simulated endurance curves.

Novel Concept of the Three-Dimensional Vertical FG nand Flash Memory Using the Separated-Sidewall Control Gate

Recently, we proposed a novel 3-D vertical floating gate (FG)-type nand Flash memory cell array using the separated-sidewall control gate (CG) (S-SCG). This novel cell consists of one cylindrical FG with line-type CG and S-SCG structures. For simplifying the process flow, we realized the common S-SCG lines by using the prestacked polysilicon layer, through which variable medium voltages are applied not only to control the electrically inverted S/D region but also to assist the program and erase operations. In this paper, we successfully demonstrate the normal Flash cell operation and show its superior performances in comparison with the recent 3-D FG nand cells by using the cylindrical device simulation. It is shown that the proposed cell can realize the highest CG coupling ratio, low-voltage cell operations of program with 15 V at <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$V_{\rm th} = \hbox{4}\ \hbox{V}$</tex> </formula> and erase with 14 V at <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$V_{\rm th} = -\hbox{3}\ \hbox{V}$</tex> </formula> , good retention-mode electric field, and sufficient read-mode on-current margin. Moreover, the proposed S-SCG cell array can fully suppress both the interference effects and the disturbance problems at the same time by removing the direct coupling effects in the same cell string, which are the most critical problems of the recent 3-D vertical stacked cell structures. Above all, the proposed cell array has good potential for terabit 3-D vertical nand Flash cell array with highly reliable multilevel cell operation.

3-D Vertical FG nand Flash Memory With a Novel Electrical S/D Technique Using the Extended Sidewall Control Gate

We propose a novel 3-D vertical floating-gate (FG) nand Flash memory cell array with a novel electrical source/drain (S/D) technique using extended sidewall control gates (ESCGs). A cylindrical FG structure is implemented to overcome the reliability issues of charge-trap-type cells. A novel electrical S/D layer by the ESCG structure also allows enhancement-mode operation. With this novel structure, we successfully demonstrate normal Flash cell operation with high-speed programming and superior read currents due to both the increase in coupling ratio and the use of low resistive electrical S/D technique by device simulation. Moreover, we found that the 3-D vertical Flash memory cell array with the novel electrical S/D technique had less interference with neighboring cells by about 50% in comparison with the conventional 3-D vertical FG nand cell array without an ESCG. Above all, the proposed cell array is one of the candidates for a Terabit 3-D vertical nand Flash cell array with high-speed read/program operation and high reliability.

Cross-cell interference variability aware model of fully planar NAND Flash memory including line edge roughness

The main reliability issue of highly scaled floating gate NAND Flash memories is the cross-cell interference phenomenon. This is an active area of research in microelectronics engineering. In the last decade, there has been much progress and there are already proposed models for extraction of parasitic capacitive couplings within floating gate transistors. However, most of simulation-based methodologies for evaluation of the impact of cross-cell interference on the electrical behavior rely on deterministic capacitive coupling, neglecting the variability effects. This approach ignores the variable nature of the capacitive couplings caused by technological limitations such as line edge roughness (LER) in advanced technological nodes. The aim of this work is to present an alternative approach of modeling threshold voltage disturbance propagation in a raw NAND Flash memory array, sourced by variability-affected parasitic capacitive couplings. The major contribution of this work is the introduction of probabilistic framework to link the process technology and system level.

Threshold Voltage Fluctuation by Random Telegraph Noise in Floating Gate nand Flash Memory String

Read current fluctuation (ΔIread) due to random telegraph noise was measured from a cell in a NAND flash memory cell string, and its effect on threshold voltage fluctuation (ΔVth) was analyzed. Sixteen-level fluctuation (four traps) was observed in a 60-nm cell of a cell string (ΔIread/Iread of ~0.4). ΔIread increased with decreasing Lg, and ΔIread/Iread up to 0.75 was observed at 48 nm. ΔIread, ΔVth, and their relation were clearly analyzed with program/erase mode of a cell and pass cells in a string. Although ΔIread is largest when a read cell and pass cells are erased, ΔVth is largest when a read cell is erased and pass cells are programmed in a cell string. We also observed the specific noise amplitude under various conditions, such as the bit-line bias, the pass bias of unselected cells in the NAND strings, and the temperature.

The Optimum Physical Targets of the 3-Dimensional Vertical FG NAND Flash Memory Cell Arrays with the Extended Sidewall Control Gate (ESCG) Structure

Recently, the 3-dimensional (3-D) vertical Floating Gate (FG) type NAND flash memory cell arrays with the Extended Sidewall Control Gate (ESCG) was proposed [7]. Using this novel structure, we successfully implemented superior program speed, read current, and less interference characteristics, by the high Control Gate (CG) coupling ratio with less interference capacitance and highly electrical inverted S/D technique. However, the process stability of the ESCG structure has not been sufficiently confirmed such as the variations of the physical dimensions. In this paper, we intensively investigated the electrical dependency according to the physical dimensions of ESCG, such as the line and spacing of ESCG and the thickness of barrier oxide. Using the 2-dimentional (2-D) TCAD simulations, we compared the basic characteristics of the FG type flash cell operation, in the aspect of program speed, read current, and interference effect. Finally, we check the process window and suggest the optimum target of the ESCG structure for reliable flash cell operation. From above all, we confirmed that this 3-dimensional vertical FG NAND flash memory cell arrays using the ESCG structure is the most attractive candidate for terabit 3-D vertical NAND flash cell array.

Improvement of Read Disturb, Program Disturb and Data Retention by Memory Cell VTH Optimization of Ferroelectric (Fe)-NAND Flash Memories for Highly Reliable and Low Power Enterprise Solid-State Drives (SSDs)

This paper presents an improvement of the memory cell reliability by the memory cell VTH optimization of the ferroelectric (Fe)-NAND flash memory. The effects of the memory cell VTH on the reliability of the Fe-NAND flash memory are experimentally analyzed for the first time. The reliability is evaluated by the measured VTH shift due to the read disturb, program disturb and data retention. Three types of Fe-NAND flash memory cells, a positive, zero and negative VTH memory cell, are defined on the basis of the memory cell VTH. The middle of VTH of programmed and erased states is 1V, 0V and -0.3V in a positive, zero and negative VTH memory cell, respectively. The VTH shift of the positive, zero and negative VTH memory cells show similar characteristics in the program/erase and the VPASS and VPGM disturbs because the external electric field is so high that the internal depolarization field does not affect the VTH shift. On the other hand, in the data retention, the VTH shift of the three types of VTH memory cells show different characteristics. The reliability of the Fe-NAND flash memory is best optimized in the zeroVTH memory cell. In the proposed zero VTH Fe-NAND flash memory cell scheme, the measured VTH shift due to the read disturb, program disturb and data retention decreases by 32%, 24% and 10%, respectively, compared with conventional positive VTH Fe-NAND flash memory cell scheme. Contrarily, in the negative VTH memory cell, the VTH shift during the data retention is 0.49V and unacceptably large because of the depolarization field. The conventional positive VTH memory cell suffers from a sever read and program disturb. The measured results are drastically different from those of the conventional floating-gate NAND flash memory cell where the negative VTH memory cell is most suitable in terms of the reliability.

Study of Retention Characteristics and Program Speed Enhancement Using Plasma Nitridation on Interpoly Dielectric

The interpoly dielectric in floating gate NAND flash memory, as it is used to bolster both programming speed and data retention, has been extensively investigated in studies examining plasma nitridation technologies. The bird’s beak, as found on an interpoly dielectric edge, likely contributes to a degradation program/erase performance and reliability in cell operation and is abnormally increased above 12 Å during gate sidewall oxidation. This phenomenon can be effectively reduced to less than 1.5 Å through the application of nitrogen plasma nitridation on the floating gate and on the top oxide of the interpoly dielectric. In terms of control gate coupling capability and program voltage, both the physical and electrical properties of the interpoly dielectric can improve by 6% and 1.2 V, respectively. Nevertheless, this study found that data retention problems resulting from plasma nitridation, a process which induces the oxynitride remaining in shallow trench isolation, are the source of electron leakage through the word line. To reduce charging loss and sustain the coupling capabilities of the control gate, selective oxynitride removal with diluted HF is proposed. This interpoly dielectric can enhance memory characteristics and also extends the functional limitation of the NAND flash memory to the 40 nm generation.

Improving the cell characteristics using arch-active profile in NAND flash memory having 60 nm design-rule

Recently the cell integration density of NAND flash memory is increasing rapidly due to its simple structure, which is suitable for high resolution lithography. Therefore, the reduction of cell size has become the most important issue. However, with an increase in the number of cells and the downscale of cell size, the NAND cell string has problems of not only small on-cell current and poor program speed but also current fluctuation due to random telegraph signal (RTS) noise. In this paper, in order to overcome revealed problems, we would like to propose the floating gate NAND flash memory, which has an arch structure active region. Also, we applied the arch structure on a poly-Si/W six stack gate of 60 nm design-rule NAND flash device for the first time, which improved cell operation characteristics such as cell current, program speed and current fluctuation (Δ I d / I d ) due to RTS noise.

Investigation of the Electron-Injection Spread in Barrier-Engineered NAND Flash Memories

This letter investigates the threshold voltage statistical spread induced by the electron-injection process during programming of barrier-engineered floating-gate NAND Flash memories. The spread is shown to be independent of the tunnel-dielectric stack composition for low amplitudes of the programming staircase, for which the granular electron injection follows the Poisson statistics. Differences in the spread arise instead for large staircase step amplitudes, as in this regime the sub-Poissonian nature of the electron-injection process strictly depends on the steepness of the tunnel-dielectric current-voltage characteristics. This steepness can be modified by changing the electron-injection regime from Fowler-Nordheim (FN) to direct tunneling (DT) to modified FN (MFN): MFN is shown to allow a reduction of the electron-injection spread with respect to FN tunneling, while the DT regime gives rise to a large increase of the spread.