Abstract
Recently the cell integration density of NAND flash memory is increasing rapidly due to its simple structure, which is suitable for high resolution lithography. Therefore, the reduction of cell size has become the most important issue. However, with an increase in the number of cells and the downscale of cell size, the NAND cell string has problems of not only small on-cell current and poor program speed but also current fluctuation due to random telegraph signal (RTS) noise. In this paper, in order to overcome revealed problems, we would like to propose the floating gate NAND flash memory, which has an arch structure active region. Also, we applied the arch structure on a poly-Si/W six stack gate of 60 nm design-rule NAND flash device for the first time, which improved cell operation characteristics such as cell current, program speed and current fluctuation (Δ I d / I d ) due to RTS noise.
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