Unified Endurance Degradation Model of Floating Gate NAND Flash Memory

Abstract

Endurance degradation model applicable to the broad node range of floating-gate NAND flash memory is proposed for the first time. The model is based on generation of the trapped charge, which follows nonuniform spatial distribution of the erase tunneling current. A special Topology Computer-Aided Design (TCAD) simulation technique to simulate program/erase cycling is described in detail. Simulation parameters, determining change of midgap voltage (vertical centroid position and maximum value of the trapped charge) are extracted from the reference device with known endurance curve, and these are applied to the target cell. The endurance characteristics predicted by the model are verified to reproduce measured endurance curves for design rules of 27, 42, and 90 nm. Several factors affect midgap voltage change-area occupied by trapped charge; vertical position of charge centroid; separation of trapped charge distribution and tunnel current. A 3-D TCAD simulation allows accurate consideration of the given factors, resulting in good match between measured and simulated endurance curves.