Floating-gate Devices Research Articles

A synaptic transistor based on van der Waals heterojunction HfS2/HfOx/SnS2 with optical modulation properties

Neuromorphic devices, which break the traditional von Neumann architecture, have attracted much attention for their ability to mimic the perception, learning, and memory functions of the human brain. Two-dimensional (2D) materials are excellent candidates for building neuromorphic devices due to their atomic-level thickness and excellent optoelectronic properties. In this work, we designed a nonvolatile floating-gate synaptic device based on an HfS2/HfOx/SnS2 van der Waals heterostructure. This device exhibits a large memory window of 60 V, based on which synaptic properties, such as an excitatory postsynaptic current, and short-term and long-term plasticity, were simulated. In addition, the long-term potentiation/depression (LTP/D) characteristics of the device can be optically modulated. The device has a low nonlinearity of 0.22 for LTP, and the ratio of the number of effective conductance states was 93.3% under 532 nm illumination; this is an improvement on the levels reported using 2D-material floating-gate devices in recent years. This work offers the possibility of future applications of optoelectronic synaptic devices.

The Nonvolatile Memory and Neuromorphic Simulation of ReS2/h-BN/Graphene Floating Gate Devices Under Photoelectrical Hybrid Modulations.

The floating gate devices, as a kind of nonvolatile memory, obtain great application potential in logic-in-memory chips. The 2D materials have been greatly studied due to atomically flat surfaces, higher carrier mobility, and excellent photoelectrical response. The 2D ReS2 flake is an excellent candidate for channel materials due to thickness-independent direct bandgap and outstanding optoelectronic response. In this paper, the floating gate devices are prepared with the ReS2/h-BN/Gr heterojunction. It obtains superior nonvolatile electrical memory characteristics, including a higher memory window ratio (81.82%), tiny writing/erasing voltage (±8V/2ms), long retention (>1000s), and stable endurance (>1000 times) as well as multiple memory states. Meanwhile, electrical writing and optical erasing are achieved by applying electrical and optical pulses, and multilevel storage can easily be achieved by regulating light pulse parameters. Finally, due to the ideal long-time potentiation/depression synaptic weights regulated by light pulses and electrical pulses, the convolutional neural network (CNN) constructed by ReS2/h-BN/Gr floating gate devices can achieve image recognition with an accuracy of up to 98.15% for MNIST dataset and 91.24% for Fashion-MNIST dataset. The research work adds a powerful option for 2D materials floating gate devices to apply to logic-in-memory chips and neuromorphic computing.

2D van der Waals Heterostructure with Tellurene Floating-Gate for Wide Range and Multi-Bit Optoelectronic Memory.

Intensive research on optoelectronic memory (OEM) devices based on two-dimensional (2D) van der Waals heterostructures (vdWhs) is being conducted due to their distinctive advantages for electrical-optical writing and multilevel storage. These features make OEM a promising candidate for the logic of reconfigurable operations. However, the realization of nonvolatile OEM with broadband absorption (from visible to infrared) and a high switching ratio remains challenging. Herein, we report a nonvolatile OEM based on a heterostructure consisting of rhenium disulfide (ReS2), hexagonal boron nitride (hBN) and tellurene (2D Te). The 2D Te-based floating-gate (FG) device exhibits excellent performance metrics, including a high switching on/off ratio (∼106), significant endurance (>1000 cycles) and impressive retention (>104 s). In addition, the narrow band gap of 2D Te endows the device with broadband optical programmability from the visible to near-infrared regions at room temperature. Moreover, by applying different gate voltages, light wavelengths, and laser powers, multiple bits can be successfully generated. Additionally, the device is specifically designed to enable reconfigurable inverter logic circuits (including AND and OR gates) through controlled electrical and optical inputs. These significant findings demonstrate that the 2D vdWhs with a 2D Te FG are a valuable approach in the development of high-performance OEM devices.

GaN High Electron Mobility Transistor with Floating Gate for Accurate Threshold Voltage Control

Gallium nitride (GaN) high electron mobility transistors (HEMTs) have high electron mobility, high breakdown voltage, and low on-resistance, and are expected to operate as power devices. When GaN HEMTs are normally-on devices, drain current flow even for 0-gate-voltage. Thus, the normally-off operation is essentially required to the power devices from a fail-safe standpoint. Figure A shows a schematic of the structure, which is constructed with GaN HEMT including floating gate and the injection gate. The block oxide and tunnel oxide were formed between control gate and floating gate, and between injection gate and floating gate, respectively. It is impossible to inject electrons from the channel to the floating gate by the applying voltage to the substrate because AlGaN layer is located on the GaN layer. We introduced the injection gate for injecting electrons into the floating gate, and then the normally-off operation is obtained by the injecting electrons into the floating gate. The injecting electrons decrease the floating gate potential and form the depletion region under the gate oxide. Because the channel is the same as that of a conventional GaN HEMTs during on-operation, the high electron mobility of GaN HEMTs can be maintained, and then the on-operation behaviors are the same as conventional GaN HEMTs except threshold voltage. In this study, we demonstrate the normally-off operation of the fabricated GaN HEMTs with floating gate.Figure B shows the microscopy image of the fabricated device where the gate length, gate width and thickness of gate oxide are 2 μm, 110 μm and 20 nm, respectively. In floating gate device, the coupling ratio between the induced voltage of floating gate and the applied voltage of control gate is important. To increase the coupling ratio, we extended the overlap areas of floating gate and control gate to the drain side. The area of the control gate and the thickness of block oxide are set to be 3600 μm2 and 50 nm, respectively. Then, the coupling ratio becomes 91%, and then the induced voltage of floating gate is almost the same as the applied voltage of control gate. High-quality oxides are required in our devices for block oxide, tunnel oxide and gate oxide, however high-quality oxide films cannot be deposited by the thermal oxidation processes for GaN and polycrystalline Si. To form high-quality dielectric films, we used the microwave exited Plasma Enhanced Chemical Vapor Deposition (PECVD) [1][2][3].The Id-Vcg characteristics before and after the electron injection into the floating gate are shown in figure C. To change the threshold voltage in positive value, the voltages of control gate and injection gate are determined for the electron injection. The threshold voltage before the electron injection is -10.7 V and the electron injection increases the threshold voltage, resulting in a positive threshold voltage of 3.2 V. This voltage is sufficiently high voltage for normally-off operation. The Id-Vd characteristics after electron injection are shown in the figure D. It is found that the electron mobility is 2100 cm2/Vs, which is the similar value of 1500~2250 cm2/Vs in the reported conventional GaN HEMT [4][5][6] and this indicates that the device can be maintained high electron mobility as same as the conventional GaN HEMT.We fabricated the GaN HEMTs with floating gate, which realize the normally-off and high electron mobility. The threshold voltage can be controlled to be 3.2 V and the electron mobility of 2100 cm2/Vs is achieved. It is indicated that normally-off GaN HEMT device with high electron mobility can be demonstrated.[1] T. Ohmi, et al., J. Phys. D: Appl. Phys., 39, p.R,2006. [2] H. Tanaka, et al., Jpn. J. Appl. Phys. 42, p. 1911, 2003. [3] H. Kambayashi, et al., Solid-State Electronics, 54, p. 660 [4] J.-T. Chen, et al., Appl. Phys. Lett. 106, 251601, 2015. [5] K. Shinohara et al., IEEE Trans. Electron Devices, 60, p. 2982, 2013. [6] X. Ding et al., CES Transaction on Electrical Machines and Systems, 3, p54. Figure 1

A high-efficiency, reliable multilevel hardware-accelerated annealer with in-memory spin coupling and complementary read algorithm

We proposed an in-memory spin coupler based on the 55 nm NOR flash technology to tackle the combinatorial optimization problems. The high-density and cost-effective floating-gate (FG) devices can overcome the capacity limitation in the conventional annealing machines based on static random access memory. In addition, the FG devices featuring high endurance and excellent data retention provide more robust annealing computation as compared to resistive random access memory. A novel complementary read algorithm is further developed to increase the tolerance on threshold voltage (V th) variation by 60%. Demonstrations show that the proposed in-memory spin coupling architecture with high efficiency and scalability has great potential for solving the combinatorial optimizations regardless of the problem size.

A Novel Word Line Driver Circuit for Compute-in-Memory Based on the Floating Gate Devices

In floating gate compute-in-memory (CIM) chips, due to the gate equivalent capacitance of the large-scale array and the parasitic capacitance of the long-distance transmission wire, it is difficult to balance the switching speed and area of the word line driver circuit (WLDC). The difference among multiple voltage domains required for floating gate CIM devices has also far exceeded the withstand voltage range of a single transistor in the WLDC. This paper proposes a novel WLDC based on the working principle of the CIM array. A multi-level pre-processing voltage control method is adopted to carry out an optional hierarchical transmission of multiple high voltages, significantly reducing the propagation delay. The proposed WLDC is based on the Wilson current mirror structure, which substantially reduces the physical design area. The simulation results show that the circuit can convert a 1.2 V low-voltage domain input signal with a frequency of 10 MHz into a high-voltage domain output voltage, and the output voltage range of a single WLDC can reach −10 V to 10 V. With a capacitive load within 5 pF, the transmission delay is less than 10 ns. The layout area is 594.88 µm2, which is suitable for a large-scale CIM array.

Multifunctional Memory-Synaptic Hybrid Optoelectronic Transistors for Neuromorphic Computing

Multifunctional neuromorphic devices, integrating the acquisition, computation, and processing of information, have exceptional advantages to simulate biological behaviors and become one of the foundations of future neuromorphic computing. However, the realization of sensor-memory-calculation in a single device remains a great challenge. Herein, memory-synaptic hybrid optoelectronic transistors were developed with hydrolyzed silica-coated lead-free double perovskite Cs <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> AgBiBr <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sub> and organic semiconductors, which exhibited sensor-memory-calculation behavior. This work offers a novel strategy for constructing multifunctional neuromorphic devices, which will further inspire the development of floating-gate device in future neuromorphic computing.

Modeling Switched Bias Irradiations on Floating Gate Devices: Application to Dosimetry

Modeling Switched Bias Irradiations on Floating Gate Devices: Application to Dosimetry

New n-p Junction Floating Gate to Enhance the Operation Performance of a Semiconductor Memory Device

To lower the charge leakage of a floating gate device and improve the operation performance of memory devices toward a smaller structure size and a higher component capability, two new types of floating gates composed of pn-type polysilicon or np-type polysilicon were developed in this study. Their microstructure and elemental compositions were investigated, and the sheet resistance, threshold voltages and erasing voltages were measured. The experimental results and charge simulation indicated that, by forming an n-p junction in the floating gate, the sheet resistance was increased, and the charge leakage was reduced because of the formation of a carrier depletion zone at the junction interface serving as an intrinsic potential barrier. Additionally, the threshold voltage and erasing voltage of the np-type floating gate were elevated, suggesting that the performance of the floating gate in the operation of memory devices can be effectively improved without the application of new materials or changes to the physical structure.

Flexible synaptic floating gate devices with dual electrical modulation based on ambipolar black phosphorus

SummaryTwo-dimensional van der Waals materials offer various possibilities for synaptic devices, matching the requirements of intelligent and energy-efficient computation. However, very few studies on robust flexible synaptic transistors have been reported, which hold great potential for soft robotics and wearable applications. Here a floating gate synaptic device based on ambipolar black phosphorus (BP) on a flexible substrate has been demonstrated with two working modes. The three-terminal mode, where the carriers are injected into the floating gate, shows a nonvolatile memory effect, whereas the two-terminal mode shows a quasi-nonvolatile memory effect. Remarkably, the synaptic device working on the three-terminal mode shows an excellent performance in the energy-efficient computation of sub-fJ/spike with a fast gate voltage response down to ∼10 ns. Furthermore, the flexible synaptic device exhibits good endurance under 5,000 bending cycles with a strain of ∼0.63%, suggesting great potential in flexible neuromorphic applications with low energy consumption.

Assessment of Two-Dimensional Materials-Based Technology for Analog Neural Networks

Embedding advanced cognitive capabilities in battery-constrained edge devices requires specialized hardware with new circuit architecture and – in the medium/long term - new device technology. We evaluate the potential of recently investigated devices based on 2D materials for the realization of analog deep neural networks, by comparing the performance of neural networks based on the same circuit architecture using three different device technologies for transistors and analog memories. As a reference result, it is included in the comparison also an implementation on a standard 0.18 μm CMOS technology. Our architecture of choice makes use of current-mode analog vector-matrix multipliers based on programmable current mirrors consisting of transistors and floating-gate non-volatile memories. We consider experimentally demonstrated transistors and memories based on a monolayer Molibdenum Disulfide channel and ideal devices based on heterostructures of multilayer-monolayer PtSe2. Following a consistent methodology for device-circuit co-design and optimization, we estimate layout area, energy efficiency and throughput as a function of the equivalent number of bits (ENOB), which is strictly correlated to classification accuracy. System-level tradeoffs are apparent: for a small ENOB experimental MoS2 floating-gate devices are already very promising; in our comparison a larger ENOB (7 bits) is only achieved with CMOS, signaling the necessity to improve linearity and electrostatics of devices with 2D materials.

Recharging process of commercial floating-gate MOS transistor in dosimetry application

We investigated the recharging process of commercial floating gate device (EPAD) during the six different dose rates and ten irradiation cycles with the highest dose rate. Dose rate dependence of the floating gate dosimeter was observed from 1 Gy/h to 26 Gy/h (H2O). There is no change of the dosimetric characteristic with a constant dose rate of 26 Gy/h for ten cycles. The absorbed dose does not affect the drift of the threshold voltage readings after the irradiation steps. The reprogramming characteristic is not degrading with the absorbed dose for the ten irradiation cycles, giving the promising potential in the application for dosimetric purposes.

Cryogenic characterization and modeling of a CMOS floating-gate device for quantum control hardware

We perform the characterization and modeling of a floating-gate device realized with a commercial 350-nm CMOS technology at cryogenic temperature. The programmability of the device offers a solution in the realization of a precise and flexible cryogenic system for qubits control in large-scale quantum computers. The device stores onto a floating-gate node a non-volatile charge, which can be bidirectionally modified by Fowler-Nordheim tunneling and impact-ionized hot-electron injection. These two injection mechanisms are characterized and modelled in compact equations both at 300 K and 15 K. At cryogenic temperature, we show a fine-tuning of the stored charge compatible with the operation of a precise analog memory. Moreover, we developed accurate simulation models of the proposed floating-gate device that set the stage for designing a programmable analog circuit with better performances and accuracy at a few Kelvin. This work offers a solution in the design of configurable analog electronics to be employed for accurately read out the qubit state at deep-cryogenic temperature.

Band‐tailored van der Waals heterostructure for multilevel memory and artificial synapse

AbstractTwo‐dimensional (2D) van der Waals heterostructure (vdWH)‐based floating gate devices show great potential for next‐generation nonvolatile and multilevel data storage memory. However, high program voltage induced substantial energy consumption, which is one of the primary concerns, hinders their applications in low‐energy‐consumption artificial synapses for neuromorphic computing. In this study, we demonstrate a three‐terminal floating gate device based on the vdWH of tin disulfide (SnS2), hexagonal boron nitride (h‐BN), and few‐layer graphene. The large electron affinity of SnS2 facilitates a significant reduction in the program voltage of the device by lowering the hole‐injection barrier across h‐BN. Our floating gate device, as a nonvolatile multilevel electronic memory, exhibits large on/off current ratio (~105), good retention (over 104 s), and robust endurance (over 1000 cycles). Moreover, it can function as an artificial synapse to emulate basic synaptic functions. Further, low energy consumption down to ~7 picojoule (pJ) can be achieved owing to the small program voltage. High linearity (&lt;1) and conductance ratio (~80) in long‐term potentiation and depression (LTP/LTD) further contribute to the high pattern recognition accuracy (~90%) in artificial neural network simulation. The proposed device with attentive band engineering can promote the future development of energy‐efficient memory and neuromorphic devices.image

APPLICATIONS OF TCAD SIMULATION SOFTWARE TO THE STUDY OF FLOATING-GATE DEVICE

The floating-gate device has become an established component of all electronic systems, especially Non-volatile memories in recent years. This paper produces a study for this device including the structure and operation (read, program/write and erase). A complete flow which uses ATHENA, ATLAS and DEVEDIT3D tools for 2D and 3D structure simulations including I-V characteristics, Channel Hot Electron Injection, and Fowler-Nordheim Tunnel simulations are performed in TCAD environment.

Cryogenic Floating-Gate CMOS Circuits for Quantum Control

Voltage biases are often required to bias Qubits, and yet applying a static bias requires separate chip wires, dramatically increasing the system complexity. An ideal approach would be having a nonvolatile digital or analog memory to avoid these issues. This article shows floating-gate (FG) structures could be used to set and forget potentials and tunnel barrier tuning as well as enable memory applications. It reports FG measurements at cryogenic temperatures (T = 4 K), enabling reprogrammable FG devices in cryogenic environments. Using a multipurpose FG test structure, measurements show the FG device and circuit operation as well as charge programming measurements based on electron tunneling and hot-electron injection at T = 4 K and T = 300 K. These results open applications in classical cryogenic computing, controlling quantum computation, and other cryogenic temperature applications.

Total Gain Recovery in Floating Gate Thin-Film Transistors for Neuromorphic and Edge Computing

We propose a floating-gate (FG) thin-film transistor architecture which alleviates a significant limitation present since the inception of FG field-effect transistors, namely the loss of gain due to parasitic capacitive coupling on the FG [1].The interest in large area electronics has grown beyond traditional applications, such as display and sensing arrays, with recent trends including neuromorphic and edge computing. However, the challenges of fabricating robust thin film transistor (TFT) circuits have remained despite the many significant achievements in material systems and process development. In order to realise the full benefit of low-cost, high-throughput manufacturing methods, device shortcomings need to be addressed [2]. In FG devices, specifically, one major limitation is the degradation of gain compared to conventional devices, as a result of capacitive coupling of the channel and drain potentials to the floating gate. The problem is far more severe in contact-controlled TFTs, such as the staggered-electrode, high-gain source-gated transistor (SGT) [3, 4], and crippling in conventional TFTs manufactured in materials such as InGaZnO [5].SGT operation differs from conventional field-effect TFTs, whereby the semiconductor is fully depleted at the source edge by an energy barrier (e.g. Schottky), which is reverse biased by the application of drain voltage. Charge injection is modulated via the gate/source overlap, producing very low saturation voltage and ultra-low output conductance gd [3]. This latter feature yields the distinctive and extremely high intrinsic gain observed in such devices. A large voltage drop occurs across the source depletion region, producing the notable early saturation and, consequently, the channel potential is maintained at a value close to the drain potential for operating conditions in which a conventional TFT would still be working in the linear region. As such, when a floating gate is used in a SGT, the FG couples strongly to both the drain and the channel. FG potential varies considerably with drain voltage, thus increasing charge injection along the source, ultimately raising gd . While gd is still orders of magnitude lower than that of a TFT or FG TFT (see Figure 1), many analog applications would benefit from a solution to this problem [1].Here, we present a staggered-electrode contact-controlled device, the multimodal transistor (MMT), which shares SGT charge injection principles, however the switching mechanism of its channel is controlled by a separate gate [6]. In a FG MMT, the source gate responsible for charge injection and channel switching gate are designed as FGs (FG1 and FG2, respectively) and a main control gate (CG) may overlap both FGs. FG MMTs have been fabricated in low T°C technology [6] with Ni source and drain contacts. ICP-CVD (Inductively Coupled Plasma Chemical Vapour Deposition) via the Corial 210D reactor was used to deposit µ-Si as active layer, as well as the insulators of the gate stack (Figure 1a). Temperature never exceeded 250°C in any of the processing steps.The MMT exhibits the same high-gain properties of the SGT and preserves it even in FG configuration. With the channel and drain potentials coupling to FG2, its potential is raised significantly higher than FG1 (see Figures 1b and 1c for TCAD simulation with Silvaco Atlas), which is effectively shielded. As charge injection is exclusively modulated by FG1, the low saturation and extremely low gd are maintained, in contrast to the FG SGT (see Figure 1c). Thus, extremely high gain can be obtained from the FG MMT structure, with a wide range of applicability to traditional analog applications such as displays and sensors, as well as emerging neuromorphic circuits.Figure. 1 a) Photomicrograph of a µ-Si floating gate MMT (FG MMT); b) FG2 potential is significantly raised, while FG1 is shielded from parasitic capacitive coupling from the channel and drain potential, keeping charge injection at the source constant with drain voltage. c) Output conductance gd comparison confirms FG MMT gd is significantly lower than that of the equivalent FG SGT.

A 2D material-based floating gate device with linear synaptic weight update.

Neuromorphic computing is of great interest among researchers interested in overcoming the von Neumann computing bottleneck. A synaptic device, one of the key components to realize a neuromorphic system, has a weight that indicates the strength of the connection between two neurons, and updating this weight must have linear and symmetric characteristics. Especially, a transistor-type device has a gate terminal, separating the processes of reading and updating the conductivity, used as a synaptic weight to prevent sneak path current issues during synaptic operations. In this study, we fabricate a top-gated flash memory device based on two-dimensional (2D) materials, MoS2 and graphene, as a channel and a floating gate, respectively, and Al2O3 and HfO2 to increase the tunneling efficiency. We demonstrate the linear weight updates and repeatable characteristics of applying negative/positive pulses, and also emulate spike timing-dependent plasticity (STDP), one of the learning rules in a spiking neural network (SNN).

Applications of TCAD Simulation Software for Fabrication and study of Process Variation Effects on Threshold Voltage in 180nm Floating-Gate Device

Applications of TCAD Simulation Software for Fabrication and study of Process Variation Effects on Threshold Voltage in 180nm Floating-Gate Device

Analysis of Hot Carrier Injection According to Gate Length.

In this paper, we analyze hot carrier injection (HCI) in an asymmetric dual gate structure with a charge storage layer. In a floating gate device, holes injected by HCI can move freely in the valence band, since the channel potential is constant. In case of charge trapping layer, however, holes are trapped only in the drain side where impact ionization occurs. Therefore, only small threshold voltage shift occurs because channel formation is enhanced only in the drain side. When the gate length is under 100 nm, trapped holes in the drain side start to control the whole channel. Thus, we expect that HCI into the charge trapping layer can be used as a non-volatile memory (NVM) mechanism in short channel devices.