Floating Gate Avalanche Injection MOS Research Articles

Microcrystalline silicon thin films prepared by RF reactive magnetron sputter deposition : M. F. Cerqueria, M. Andritschky, L. Rebouta, J. A. Ferreira and M. F. Da Silva. Vacuum, 46 (12), 1385 (December 1995).

Physical modelling of floating-gate avalanche-injection MOS (FAMOS) devices in the program (write) mode is complicated by a feedback effect to the channel from the floating gate. The floating gate takes on a potential by virtue of capacitive coupling to the drain; this induces a channel near the source; the channel injects carriers into the depletion region near the drain and greatly enhances the avalanche multiplication current. This paper presents a simple method for taking account of this effect using empirical data, and thereby arriving at a first-order model of the FAMOS device. Measurements of drain current are subdivided into channel current and avalanche multiplication current, and a constant hot-carrier injection efficiency is assumed. The hot-carrier (avalanche) injection current is associated with a dielectric resistivity, whose dependence on the electric field in the oxide can be approximated by a simple exponential function. Model predictions for the write characteristics of FAMOS devices are in reasonable agreement with experiment.

A 23-ns 256 K EPROM with double-layer metal and address transition detection

A 256 K EPROM (electrically programmable read-only memory) is described in which 23-ns access time was achieved by a combination of advanced CMOS processing, double-layer metal (DLM), differential sensing, address transition detection (ATD), and a ground-switched decoding scheme. DLM is used to strap wordlines in the array and bus signals in the periphery. Performance is obtained by reducing bit line length to 256 cells, with 2048 cells per word line. This results in a 70.5-mil*229.8-mil array with an efficiency of 41.2%. Die size is 116 mil*339 mil. Short bit lines result in a total column and Y-select capacitance of 1.3 pF. Word line RC delay is only 0.8 ns. DLM saves 7.3 ns over an optimized silicide design using two word line drivers. The 0.8- mu m CMOS DLM EPROM technology yields a typical unloaded ring oscillator gate delay of 115 ps. Lightly doped drain (LLD) is used on both NMOS and PMOS devices for reliability and performance. Ti/Al metalization improves metal reliability. A composite interpoly dielectric is used for improved FAMOS (floating-gate avalanche-injection MOS) reliability. >

A novel, shallow-trench-isolated, planar, N+SAG FAMOS transistor for high-density nonvolatile memories

The authors report the fabrication, for the first time, of a shallow-trench isolated (less than 1 mu m deep) planarized, floating-gate avalanche injection MOS (FAMOS) transistor with n/sup +/ bitlines self-aligned to gate (n/sup +/ SAG). Key to the planar process is the self-alignment of the buried n/sup +/ diffusions (bitlines) to the floating gate of the FAMOS transistor and the deposition over these diffusions of a low-temperature, conformal CVD (chemical vapor deposition) oxide. An oxide-resist etchback process was used to planarize the buried n/sup +/ CVD oxide. Trench etching was done immediately after definition of the stacked polysilicon gates. Using an anisotropic etch for single-crystal silicon, trenches with a 0.75 mu m depth were made in the bitline isolation areas of the planar devices. The trenches were then refilled with thermal and LPCVD (liquid-phase CVD) SiO/sub 2/. Characterization of the planar EPROM (erasable programmable read-only memory) cell shows that the shallow trench between bitlines has improved their isolation characteristics. An increase in programming efficiency of as much as 30% at a pulse width of 1 ms was observed in the case of the shallow-trench-isolated FAMOS. Additional data indicate the possibility of programming the trench isolated cell at drain voltages lower than the present 12.5 V, thus reducing high voltage requirements.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A modifiable weight circuit for use in adaptive neuromorphic networks: [formula omitted]. Code 551, Naval Ocean Systems Center, San Diego, CA 92152-5000, USA

Abstract : The Naval Ocean Systems Center is involved in a collaborative effort with the Naval Weapons Center to implement neuromorphic networks in analog integrated circuitry using CMOS technology. We are investigating the use of a floating-gate charge storage device as a modifiable, non-volatile analog memory element for representing and storing interconnection weights between processing units, and have designed a simple circuit to sense this charge and perform the multiplicative 'synaptic' function. We employ the mechanism of avalanche or hot- carrier injection to move charge onto a floating-gate structure. This mechanism was first used in the mid-1970's for digital memory applications in the 'FAMOS' (floating gate avalanche injection MOS) device, which consisted of a p-channel MOSFET with an isolated gate. At an appropriate biasing voltage, 'hot' electrons are generated in avalanche breakdown, which have sufficient energy to conduct across the gate oxide and charge the gate. In an n-channel device, a complementary process takes place, with holes rather than electrons injected onto the floating gate. The potential due to the charge influences the state of the transistor under the gate just as would an externally applied voltage. Multimedia Reprint, Naval document. (RRH)

A novel trench-isolated buried N+FAMOS Transistor suitable for high-density EPROM's

This paper describes an innovative use of trench isolation to achieve high programmability and improved isolation in a high-density electrically programmable read-only memory (EPROM) cell. This cell, with a 13.5-µm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> area at 1.5-µm design rules, was fabricated by using a novel cross-point structure with buried N+ (BN+) bit lines as source and drain of the floating-gate avalanche injection MOS (FAMOS) transistor. Programming efficiency and bit-line isolation were enhanced by a novel positioning of the trench isolation between bit-lines and between the double-polysilicon FAMOS transistors. Trench isolation should permit scaling of the bit-line spacing to below 1 µm.

E2FAMOS&amp;#8212;An electrically eraseable reprogrammable charge storage device

A new electrically eraseable nonvolatile charge storage device is described. The electrically eraseable floating-gate avalanche injection MOS (E2FAMOS) structure is an n-channel dual-stacked-gate MOS transistor programmed by avalanche injection from the pinchoff region and erased by hot electron injection from the floating gate.

Design of a read-only-memory programmer

A system in described which permits the simple programming of a read only memory. The programmer is particularly suitable for floating gate avalanche-injection MOS charge-storage memories which are erasable by exposure to ultra-violet light. After a discussion of the physical mechanisms involved in programming the paper provides details on circuit design with particular emphasis on interface problems.

Modelling of channel enhancement effects on the write characteristics of FAMOS devices

Physical modelling of floating-gate avalanche-injection MOS (FAMOS) devices in the program (write) mode is complicated by a feedback effect to the channel from the floating gate. The floating gate takes on a potential by virtue of capacitive coupling to the drain; this induces a channel near the source; the channel injects carriers into the depletion region near the drain and greatly enhances the avalanche multiplication current. This paper presents a simple method for taking account of this effect using empirical data, and thereby arriving at a first-order model of the FAMOS device. Measurements of drain current are subdivided into channel current and avalanche multiplication current, and a constant hot-carrier injection efficiency is assumed. The hot-carrier (avalanche) injection current is associated with a dielectric resistivity, whose dependence on the electric field in the oxide can be approximated by a simple exponential function. Model predictions for the write characteristics of FAMOS devices are in reasonable agreement with experiment.

Famos—A new semiconductor charge storage device

A new non-volatile charge storage device is described. The floating gate avalanche injection MOS (FAMOS) structure is a p-channel silicon gate field effect transistor in which no electric contact is made to the silicon gate. It combines the floating gate concept with avalanche injection of electrons from the surface depletion region of a p- n junction to yield reproducible charging characteristics with long term storage retention.

A fully decoded 2048-bit electrically programmable FAMOS read-only memory

A floating-gate avalanche-injection m.o.s. (FAMOS) charge-storage device is used as the basic nonvolatile memory element. The memory is organized as 256 words of 8 bits, it is fully TTL compatible, and can be operated in both the static or dynamic mode. The memory array was successfully fabricated with silicon gate m.o.s. technology yielding functional devices with access times of 800 ns in the static mode and 500 ns in the dynamic mode of operation. The memory chip is assembled in a 24-lead dual-in-line package.

MEMORY BEHAVIOR IN A FLOATING-GATE AVALANCHE-INJECTION MOS (FAMOS) STRUCTURE

A novel charge-storage structure is described. The floating-gate avalanche-injection MOS (FAMOS) structure is shown to exhibit memory behavior in the form of long-term charge storage on the floating conductive gate of an insulated gate field-effect device. Charge is stored in the floating polysilicon gate by avalanche injection of electrons from an underlying p-n junction.