Floating-body Silicon-on-insulator Research Articles

A Dual-Band SP6T T/R Switch in SOI CMOS With 37-dBm <formula formulatype="inline"><tex Notation="TeX">${ P}_{-0.1\ {\rm {dB}}}$</tex></formula> for GSM/W-CDMA Handsets

This paper presents the circuit techniques to achieve superior linearity and isolation for a single-pole six-throw transmit/receive (T/R) switch designed for GSM/W-CDMA dual-band operation at 0.85-0.9 and 1.8-1.9 GHz. Implemented in a 0.18- μm thick-film silicon-on-insulator (SOI) CMOS process, the switch employs an LC-tuned asymmetric topology for the transmit (Tx) and receive (Rx) branch to handle the high-power GSM transmitter requirement. The proposed design also features a switchable double LC-tank acting as a variable impedance block to relax the tradeoff among linearity, insertion loss (IL), and isolation. Feed-forward capacitors, ac-floating bias techniques, and floating-body SOI devices are utilized to further improve the linearity. The measured P-0.1 dB, IL and Tx-Rx isolation in the lower and upper band are 37.2-35.6 dBm, 0.43-0.75 dB, and 45-37 dB, respectively. The proposed T/R switch design in SOI CMOS is an important building block toward more compact and lower cost RF frond-end modules, which integrate the switch, antenna tuning module, and control logic on the same chip.

A Tunnel Diode Body Contact Structure for High-Performance SOI MOSFETs

A tunnel diode body contact (TDBC) silicon-on-insulator (SOI) MOSFET structure without floating-body effects (FBEs) is proposed and successfully demonstrated. The key idea of the proposed structure is that a tunnel diode is embedded in the source region, so that the accumulated carriers can be released through tunneling. In an n-MOSFET, a heavily doped p+ layer is introduced beneath the n+ source region. The simulated and measured results show the suppressed FBE, as expected. Other phenomena that originate from the FBEs, such as the kink, linear kink effect, abnormal subthreshold swing, and small drain-tosource breakdown voltage in the properties, were also sufficiently suppressed. In addition, it should be noted that the proposed SOI MOSFETs are fully laid out and process compatible with SOI CMOS. Hysteresis effects disappear in TDBC SOI MOSFETs, which makes them attractive for digital applications. On the other hand, in analog applications, TDBC SOI MOSFETs are shown to hold the advantage over floating-body SOI MOSFETs due to their higher Gm/ID ratio. TDBC SOI MOSFETs can be considered as one of the promising candidates for digital and analog devices.

Narrow-Width Effects on a Body-Tied Partially Depleted SOI MOSFET

In this paper, we present the investigation of narrow-width effects (NWEs) on partially depleted (PD) silicon-on-insulator (SOI) with different gate shape topologies. Based on dc/ac measurements and TCAD simulations, it shows detailed clarifications of body-tied-induced NWEs. The overall study demonstrates relationship between gate shape topologies, body-tied shape, and electrical width of the transistor. Provided physical-based analytical models are able to capture peak <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GM</i> and <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GG</sub> as function of gate length, transistor width, physical gate-overlap width, and number of body tied. This results in improving the overall model accuracy of body contact and floating-body PD SOI MOSFETs.

Gate direct-tunnelling and hot-carrier-induced hysteresis effect in partially depleted silicon-on-insulator floating-body MOSFETs

The hysteresis effect in the output characteristics of partially depleted (PD) silicon-on-insulator (SOI) floating-body MOSFETs with an ultra-thin gate oxide is studied taking account of both gate direct-tunnelling and impact ionization-induced hot-carrier mechanisms. It is proposed that hole tunnelling from valence band (HVB) for floating-body PD SOI n-MOSFETs, electron tunnelling from conduction band (ECB) for floating-body PD SOI p-MOSFETs and impact-ionization-induced hot carriers are the main causes of the hysteresis effect. Meanwhile, body-contact structures of T-gate and H-gate PD SOI MOSFETs are also studied under floating-body configurations. It is found that the influence of the converse poly-gate on the body-contact side on gate direct-tunnelling cannot be neglected in view of floating-body potential variation. Based on the measurement results, the hysteresis can be suppressed using T-gate and H-gate PD SOI MOSFETs with floating-body configurations.

SOI digital pixel sensor based on charge pumping

In this paper, a digital pixel sensor in silicon on insulator (SOI) is presented. The active part is a partially depleted SOI phototransistor. The technique elaborated in Harik et al. (2008) [1] was designed and implemented. Moreover, we took advantage of some of the characteristics of the floating body SOI MOSFET to implement a first order delta sigma modulator in each pixel. Measured data show that the pixel has a sensitivity of 3mW/m2 and a resolution of about 7bits. This pixel can be operated in two modes: weak inversion (Idc=1.2μA) and moderate inversion (Idc=15μA).

Using layout technique and direct-tunneling mechanism to promote DC performance of partially depleted SOI devices

This paper reports the dc performance enhancements of partially depleted (PD) silicon-on-insulator (SOI) devices with lower subthreshold swing and higher driving capability, kink-onset voltage, and transconductance simultaneously. Based on the measured results, by using layout technique, for floating-body PD SOI pMOSFETs with ultrathin gate-oxide thickness, H-gate configuration with the partial n/sup +/ poly-gate shows the best floating-body characteristics as compared to that in T-gate and three-terminal configurations. Owing to the direct-tunneling mechanism in the partial n/sup +/ poly-gate, the conduction-band electron tunneling current will make the floating-body potential biased in strong inversion region raised. In addition, due to the larger oxide voltage drop across the partial n/sup +/ poly-gate in subthreshold region, the valence-band hole substrate current will result in lower floating-body potential. These dc performance enhancements advantage in both digital and analog designs.

Modeling of drain current overshoot and recombination lifetime extraction in floating-body submicron SOI MOSFETs

This work reports on a new general modeling of recombination-based mechanisms related to electrically floating-body partially-depleted (PD) SOI MOSFETs. The model describes drain current overshoots induced when turning on the transistor gate and suggests a novel extraction method for the recombination lifetime in the silicon film. We show that the recombination process associated with drain current overshoots in PD silicon-on-insulator (SOI) MOSFETs takes place mainly in the depletion region and not in the neutral region as in case of pulsed MOS capacitors. Associated with existing techniques for generation lifetime extraction, our model offers, for the first time, the possibility of complete and rapid characterization for both generation and recombination lifetime using drain current transients in floating-body SOI MOSFETs. The model is used in order to characterize submicron SOI devices, allowing a thorough investigation of technological parameters impact on floating-body-induced transient mechanisms.

Impact of Hot Carrier Stress on Low-Frequency Noise Characteristics in Floating-Body Silicon-on-Insulator Metal Oxide Semiconductor Field-Effect Transistors

The impact of hot carrier stress on low-frequency noise features characteristic of floating-body silicon-on-insulator (SOI) metal oxide semiconductor field-effect transistors (MOSFETs) including fully and partially depleted MOSFETs is investigated. It is reported for the first time that Lorentzian-like excess low-frequency noise, which appears in floating body SOI MOSFETs, is strongly affected by hot carrier stress. The excess noise is well suppressed in fully depleted MOSFETs after stress. However, it is not so significantly suppressed in partially depleted MOSFETs, but the characteristic frequency in the excess noise spectrum shifts after stress. The mechanism of these phenomena is also discussed. Hot carrier stress causes interface-trap generation, and leads to a decrease in the floating-body effect due to recombination of excess holes and electrons through the interface traps, thus leading to instability in the Lorentzian-like excess low-frequency noise.

Temperature dependence of hot-carrier-induced degradation in 0.1 μm SOI nMOSFETs with thin oxide

This letter investigates hot-carrier-induced degradation on 0.1 /spl mu/m partially depleted silicon-on-insulator (SOI) nMOSFETs at various ambient temperatures. The thermal impact on device degradation was investigated with respect to body-contact nMOSFETs (BC-SOI) and floating-body SOI nMOSFETs (FB-SOI). Experimental results show that hot-carrier-induced degradation on drive capacity of FB-SOI devices exhibits inverse temperature dependence compared to that of BC-SOI devices. This is attributed to the floating-body effect (FBE) and parasitic bipolar transistor (PBT) effect.

Hot carrier-induced SOI MOSFET degradation under AC stress conditions

The hot-carrier-induced device degradation in partially depleted silicon-on-insulator (SOI) devices has been investigated under AC stress conditions. The device degradation of both floating-body SOI devices and body contacted SOI devices have been measured and analyzed for different AC stress frequencies and gate bias voltages. Possible degradation mechanisms are suggested.

OFF-State leakage current mechanisms in bulkSi and SOI MOSFETs and their impact on CMOS ULSIs standby current

In this work, an analytical model of the OFF-state leakage current in metal-oxide-semiconductor (MOS) transistors and its relation with the standby current of logic complementary MOS (CMOS) ICs is presented. The OFF leakage currents in (1) bulk MOS; (2) floating-body silicon-on-insulator (FB-SOI); and (3) body-tied SOI (BT-SOI) MOS field effect transistors (MOSFETs) are modeled based on physics mechanisms, equivalent circuits and operational block diagrams. Good correlation is obtained between the theory and experimental devices. The model clarifies and quantifies that in thin film FB-SOI, the OFF leakage current is dominated by (a) V/sub th/ at drain voltages lower than the onset of the "kink" effect V/sub ds/<V/sub dk/, and (b) the impact ionization-induced floating-body effect for V/sub ds/>V/sub dk/. The OFF-state leakage current model is successfully applied to the analysis and prediction of the leakage current components in logic integrated circuits (CMOS ICs).

Effect of starting SOI material quality on low-frequency noise characteristics in partially depleted floating-body SOI MOSFETs

The low-frequency noise properties of partially-depleted (PD) floating-body silicon-on-insulator (SOI) MOSFETs fabricated on two types of commercially available bonded SOI (BSOI) wafers were experimentally investigated. In the pre-kink region, a drain bias dependent Lorentzian-like noise has been observed for UNIBOND wafers, while a pure 1/f noise has been achieved for ELTRAN wafers. Our analysis shows that the charge fluctuation induced by emission process through intermediate-level centers in the drain-depletion region causes the instability in the body voltage, resulting in the pre-kink excess noise for UNIBOND wafers.

Direct Measurement of Transient Drain Currents in Partially-Depleted SOI N-Channel MOSFETs Using a Nuclear Microprobe for Highly Reliable Device Designs

Transient drain currents caused by proton microprobe irradiations in partially-depleted (PD) silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistors (MOSFETs) were analyzed for soft-error issues. Transient currents of the body-tied MOSFETs can be lowered compared to those of the floating body SOI MOSFETs by suppression of the floating body effect. The effectiveness of the body-tie structure was analyzed by device simulation. Increase in the body potential by proton irradiation is suppressed efficiently in the narrow-channel body-tied SOI MOSFETs due to the low body resistance to excess carrier extraction. On the other hand, the body potential of narrow-channel floating body SOI MOSFETs increase to higher levels than those of the wide-channel MOSFETs due to the lower body capacitance. It is indicated that narrow-channel body-tied SOI MOSFETs are suitable for highly reliable devices. Moreover, a more reliable body-tied structure with high impurity concentration in the body regions to reduce the body resistance in the structure is proposed. The collected drain charge was able to be reduced by utilizing this structure. These devices are expected to be applied to highly reliable LSI's used for satellite systems, server and mainstream LSI applications of the multimedia era.

A simple method to determine the floating-body voltage of SOI CMOS devices

A technique to extract the off-state floating-body (FB) voltage of silicon-on-insulator (SOI) CMOS devices is presented. The bias dependent S-parameter measurements of a single standard FB SOI device and its equivalent circuit, along with the capacitance-voltage (C-V) measurements between the drain and source of the same device, are used to determine the FB voltage. No special test structure design is needed. The technique proposes a method for the extraction of the parasitic source, drain, and gate resistances. Using the technique, FB voltage in excess of 0.4 V is measured in a partially depicted (PD) NMOS device at drain voltage of 2.5 V and zero gate voltage.

Phase noise characteristics associated with low-frequency noise in submicron SOI MOSFET feedback oscillator for RF IC's

Phase noise in silicon-on-insulator (SOI) MOSFET feedback oscillators for RF IC applications is investigated. The observed correlation between the oscillator's high frequency phase noise and the transistor's low-frequency noise characteristics demonstrates that the phase noise overshoot still exists in partially-depleted (PD) floating body SOI nMOS Colpitts oscillators. These results suggest that kink-induced effects associated with low-frequency components of the signal are upconverted into the ideally kink-free high frequency domain operation mode of PD floating body SOI oscillators.