Flip Chip On Board Research Articles

The thermal cycling reliability of copper pillar solder bump in flip chip via thermal compression bonding

In this paper, the thermal-mechanical reliability of flip chip on board (FCOB) with copper pillar solder joint is investigated. By increasing the temperature and time of the thermal compression bonding (TCB) process, the copper pillar solder joint with intermetallic compound (IMC) as the main body is obtained. Then the Cu pillar/Sn-Ag/Cu pad and Cu pillar/IMC/Cu pad joint structures are carried out the thermal cycling test separately. It is observed that the crack of the Sn-Ag solder joint caused by ductile fracture, which is leaded by fatigue and then extension through microvoids caused by creep. And the crack of IMC joint is mainly caused by the brittle fracture along the Cu6Sn5 and Cu3Sn phase interface. At the same time, two constitutive of viscoplasticity and elastic-plastic-creep and life prediction models are compared. The effect of underfill on the thermal-mechanical reliability of copper pillar solder joint is evaluated by comparing the underfills filled with different weight ratio filler particles.

Rotational solder self-alignment mechanics modeling for a flip chip in the presence of a viscous fluid

Advent of 2.5/3Dimensional (2.5/3D) integration using through-silicon vias (TSVs) enables the formation of high signal bandwidth, fine pitch, and short-distance interconnections in stacked dies but the new package configuration poses technical challenges in package assembly process. To pace industry demands, a new alternative, Thermal Compression Bonding (TCB), to the conventional Flip Chip on Board (FCOB) process has been being developed for the 3D stacking. Among process materials, epoxy flux (or no-flow underfill) draws high attention again due to its technical advantages in both TCB and mass reflow process. The conventional mass reflow with epoxy flux could provide outstanding benefits to 2.5D package assembly process. The new Low Cost High Throughput Flip Chip Assembly process is one such process requiring fewer processing steps, lower cycle times, and lower cost. In this new process, underfill is dispensed prior to chip placement, and solder reflow and underfill cure occur simultaneously. This reduces the cycle time required for manufacture; however, the presence of a viscous underfill affects the chips' capacity for self-alignment. In a companion study, self-alignment for a flip chip undergoing rectilinear translation was analyzed. This paper applies an equivalent analysis process to a flip chip undergoing rotation in the presence of a viscous underfill. Details of the modeling process are presented along with parametric studies and contrasted against pure translation case. Conditions and process parameters which are more conducive to realignment and those hampering realignment are presented.

Finite element analysis of flip – chip on board (FCOB) assembly during reflow soldering process

PurposeOut‐of‐plane displacement (warpage) is one of the major thermomechanical reliability concerns for board‐level electronic packaging. The warpage and residual stresses can cause unreliability in the performance of electronic chip. An accurate estimation of the distortion and the residual stresses will help in selecting right combination of material for soldering and to determine the better assembly procedure of the chip. The purpose of this paper is to create a 3D nonlinear finite element model to predict the warpage, bending stresses, shear and peel stresses in a flip‐chip on board (FCOB).Design/methodology/approachA 3D finite element procedure has been developed considering the material nonlinearity during solidification for a FCOB assembly. Finite element results have been compared with the experimental values.FindingsThe present finite element method gives better approximation of residual warpage and stresses compared to analytical models available in the literature.Originality/valueThe 3D finite element approach considering the elasto‐plastic and temperature‐dependent material properties has not been attempted by any authors. Experiments have been conducted for the comparison of finite element values. The finite element results compare better than the methods available in the literature. Hence a better method for estimating the deformation and residual stresses in flip‐chip assembly has been suggested.

Design, Fabrication, and Reliability of Low-Cost Flip-Chip-On-Board Package for Commercial Applications up to 50 GHz

This paper presents a flip-chip-on-board (FCOB) packaging technology using a Rogers RO3210 laminate for microwave applications. Compared to the conventional microwave packaging architecture, the proposed FCOB technology skips one level of the ceramic package and thus results in lower reflections and manufacturing costs. To fulfill the small dimension requirement on printed circuit boards, the coplanar waveguide (CPW) transmission line and flip-chip bump were fabricated on a high-k RO3210 board (ε <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">r</sub> = 10.2) with photolithography and electroplating. The GaAs chip patterned with the CPW line was then flip-chip-mounted onto the RO3210 laminate board. This structure displayed excellent performance from dc to 50 GHz with a return loss Sn greater than 18 dB and insertion loss S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">21</sub> less than 0.5 dB. Meanwhile, the flip-chip bonding of the in-house-fabricated In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.52</sub> Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.4</sub> sAs/In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.6</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.4</sub> As metamorphic high-electron-mobility transistor devices on RO3210 also displayed excellent gain performance with a small degradation of 1 dB from dc to 40 GHz, showing the potential of implementing microwave integrated circuits on RO3210. To enhance the mechanical reliability, an epoxy-based underfill was injected into the flip-chip assemblies. Thermal cycling tests were performed to test the interconnect reliability, and the results indicated that the samples passed the thermal cycling test at least up to 600 cycles, showing excellent reliability for commercial applications. To the best of the authors' knowledge, this is the first study that evaluates the use of the RO3210 laminate for microwave flip-chip in open literature.

Demonstration of fine pitch FCOB (Flip Chip on Board) assembly based on solder bumps at Fermilab

Bump bonding is a superior assembly alternative compared to conventional wire bond techniques. It offers a highly reliable connection with greatly reduced parasitic properties. The Flip Chip on Board (FCOB) procedure is an especially attractive packaging method for applications requiring a large number of connections at moderate pitch. This paper reports on the successful demonstration of FCOB assembly based on solder bumps down to 250 μm pitch using a SUSS MA8 mask aligner at Fermilab. The assembly procedure will be described, microscopic cross sections of the connections are shown, and first measurements on the contact resistance are presented.

Effects of the Functional Groups of Nonconductive Films (NCFs) on Material Properties and Reliability of NCF Flip-Chip-On-Organic Boards

Nonconductive films (NCFs) are one of the polymer interconnect materials for flip-chip interconnection. NCFs containing no conductive particles play several roles such as adhesion, insulation, and underfilling at the same time. The most important issue of NCF flip-chip-on-board (FCOB) assemblies is thermal cycling reliability. Thermomechanical properties of cured NCFs, such as glass transition temperature (T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> ), storage modulus (E'), and coefficient of thermal expansion (CTE), significantly affect the thermal cycling reliability of NCF FCOB assemblies. In this paper, the improvement of thermomechanical properties of NCFs was investigated by controlling the number of functional groups of NCF resins. To compare the reliability of conventional and modified NCF FCOB assemblies after thermal cycling test, electrical analysis and scanning acoustic microscopy investigation were performed. Thermal deformations of NCF FCOB assemblies under thermal cycling environment were also investigated, and quantitatively compared using high sensitivity Twyman-Green interferometry and portable engineering Moire interferometry. According to these results, the functional groups of NCFs have significant effects on thermomechanical properties of cured NCFs, thermal deformation, and thermal cycling reliability of NCF-bonded FCOB assemblies. As a result, the functionality modified NCF FCOB assemblies showed significantly enhanced reliability compared conventional NCFs in thermal cycling test.

A Heterogeneous Array of Off-Chip Interconnects for Optimum Mechanical and Electrical Performance

Demand for off-chip bandwidth has continued to increase. It is projected by the Semiconductor Industry Association in their International Technology Roadmap for Semiconductors that by the year 2015, the chip-to-substrate area-array input-output interconnects will require a pitch of 80 μm. Compliant off-chip interconnects show great potential to address these needs. G-Helix is a lithography-based electroplated compliant interconnect that can be fabricated at the wafer level. G-Helix interconnects exhibit excellent compliance in all three orthogonal directions, and can accommodate the coefficient of thermal expansion (CTE) mismatch between the silicon die and the organic substrate without requiring an underfill. Also, these compliant interconnects are less likely to crack or delaminate the low-k dielectric material in current and future integrated circuits. The interconnects are potentially cost effective because they can be fabricated in batch at the wafer level and using conventional wafer fabrication infrastructure. In this paper, we present an integrative approach, which uses interconnects with varying compliance and thus varying electrical performance from the center to the edge of the die. Using such a varying geometry from the center to the edge of the die, the system performance can be tailored by balancing electrical requirements against thermomechanical reliability concerns. The test vehicle design to assess the reliability and electrical performance of the interconnects is also presented. Preliminary fabrication results for the integrative approach are presented and show the viability of the fabrication procedure. The results from reliability experiments of helix interconnects assembled on an organic substrate are also presented. Initial results from the thermal cycling experiments are promising. Results from mechanical characterization experiments are also presented and show that the out-of-plane compliance exceeds target values recommended by industry experts. Finally, through finite element analysis simulations, it is demonstrated that the die stresses induced by the compliant interconnects are an order of magnitude lower than the die stresses in flip chip on board (FCOB) assemblies, and hence the compliant interconnects are not likely to crack or delaminate low-k dielectric material.

Numerical analysis of plastic encapsulated electronic package reliability: Viscoelastic properties of underfill resin

The reliability and mechanical performance of electronic integrated circuit (IC) package is studied based on the finite element analysis. The flip chip on board (FCOB) package – one of the most current plastic encapsulated IC packages – consists of a die, solders, a printed circuit board and underfill resin encapsulated between the die and PCB, which is subjected to a typical thermal cycle experienced during the manufacturing process. The effects of viscoelastic properties of underfill resin on mechanical responses and residual stresses of FCOB packages are specifically studied and the results are compared with those obtained for a thermoelastic underfill resin. The viscoelastic properties of underfill resin are characterized using the time–temperature superposition (TTS) technique. Both the rigid and flexible PCB substrates are considered.It is found that the elastic model underestimates significantly both the thermal stress and the strain level in the solder joints, whereas it overestimates the stress concentrations in the underfill fillet around the die corner than the viscoelastic model. When the package is subjected to an extended dwell time at an elevated temperature, a moderate loss of mechanical coupling between the die and organic substrate is expected due to the relaxation of underfill resin. The implication is that the viscoelastic nature of underfill material should be properly taken into account if the failure of solder joints and the lifetime of the package are to be accurately estimated.

Materials and Processes Issues in Fine Pitch Eutectic Solder Flip Chip Interconnection

New product designs within the electronics packaging industry continue to demand interconnects at shrinking geometry, both at the integrated circuit and supporting circuit board substrate level, thereby creating numerous manufacturing challenges. Flip chip on board (FCOB) applications are currently being driven by the need for reduced manufacturing costs and higher volume robust production capability. One of today's low cost FCOB solutions has emerged as an extension of the existing infrastructure for surface mount technology and combines an under bump metallization (UBM) with a stencil printing solder bumping process, to generate mechanically robust joint structures with low electrical resistance between chip and board. Although electroless Ni plating of the UBM, and stencil printing for solder paste deposition have been widely used in commercial industrial applications, there still exists a number of technical issues related to these materials and processes as the joint geometry is further reduced. This paper reports on trials with electroless Ni plating and stencil paste printing and the correlation between process variables in the formation of bumps and the shear strength of said bumps at different geometries. The effect of precise control of tolerances in squeegees, stencils and wafer fixtures was examined to enable the optimization of the materials, processes, and tooling for reduction of bumping defects

Failures of flip chip assemblies under thermal shock

Flip chip on board (FCOB) solder joint reliability under thermal shock stress was investigated. With underfill materials, the solder joint lifetime was increased from 37 to 1,300/2,480 cycles depending on the particular underfill material used. Through the use of CSAM, SEM, dye penetration tests and cross sectioning, the reliability of a FCOB assembly under thermal shock stress was evaluated. Both dye penetration and SEM fracture analysis can be used to measure quantitatively the extent of crack propagation for assemblies without underfill. A new failure mechanism, PCB cracking was also observed and discussed.

Investigation on flip chip solder joint fatigue with cure-dependent underfill properties

A cure-dependent viscoelastic constitutive relation is applied to describe the curing process of epoxy underfill in flip chip on board (FCOB). The chemical shrinkage of the epoxy underfill during the curing process is applied via incremental initial strains. Thus, the stress and strain build-up, caused by the simultaneous increase in stiffness and shrinkage during the curing process, are simulated. Accelerated fatigue experiments with thermal cycles from -55/spl deg/C to 80/spl deg/C are carried out for a specially designed flip chip configuration. Based on the obtained curing induced initial stress and strain fields, thermo-mechanical predictions are presented for the test carriers. The solder bumps are modeled with temperature dependent visco-plastic properties. A combination of a Coffin-Manson based fatigue relation and a creep fatigue model is used as fatigue failure criterion. The results show that the finite element method (FEM)-based fatigue life predictions match better with the experimental results, if the curing induced initial stress state is taken into account. The effect of cure-induced hydrostatic stress is qualitatively investigated by using a modified energy partitioning damage model with a correction factor in the creep damage formulation to take into account the effect of the hydrostatic stress.

Adhesion characteristics of underfill resins with flip chip package components

Of fundamental importance to enhance the reliability of flip chip on board (FCOB) packages is to avoid the initiation and propagation of various interfacial failures and, therefore, robust interfacial bonds between the underfill and other components are highly desired. In the present study, the interfacial bond strengths of both conventional and no-flow underfill resins with die passivation, eutectic solder and epoxy solder mask are measured using the button shear test. The surface characteristics of these substrates are analyzed using various techniques, including optical scanning interferometry, scanning electron microscopy and contact angle measurements. It is found that the interfacial bond strength of the underfill with the eutectic solder is far weaker than of other interfaces. The degradation of underfill bond strength with silicon nitride passivation, eutectic solder and polymeric solder mask surfaces is enhanced in the presence of solder flux, and cleaning the fluxed surface with a saponifier is an efficient means to restore the original interfacial adhesion. The necessity of post-solder reflow cleaning is shown by performing thermal cycle tests on FCOB packages with different extents of flux residue. Distinctive solder failure behaviors are observed for the packages with and without post-solder reflow cleaning from the cross-sectional analysis.

Hygro-Mechanical Durability of Underfilled Flip-Chip-on-Board (FCOB) Interconnects

The effect of constant temperature and humidity environments on the durability of interconnects in underfilled Flip-Chip-on-Board (FCOB) assemblies is investigated in this study. Polymeric underfills, used to enhance thermomechanical durability of the interconnects, are found to create new failure modes due to hygromechanical swelling. Based on experimental observations, the failure mechanism is hypothesized to be cracking of intermetallics, which have weakened due to thermal aging. Pseudo 3-D finite element analyses are conducted to quantify the moisture absorption and diffusion through the polymeric underfill, and the resulting hygromechanical viscoplastic stress history. The simulations are combined with accelerated aging tests to assess in-service durability in hot, humid environments. Model predictions are compared with results of accelerated life tests available in the literature.

Application assessment of high throughput flip chip assembly for a high lead-eutectic solder cap interconnect system using no-flow underfill materials

Flip chip on board (FCOB) is one of the most quickly growing segments in advanced electronic packaging. In many cases, assembly processes are not capable of providing the high throughputs needed for integrated surface mount technology (SMT) processing (Tummala et al, 1997). A new high throughput process using no-flow underfill materials has been developed that has the potential to significantly increase flip chip assembly throughput. Previous research has demonstrated the feasibility and reliability of the high throughput process required for FCOB assemblies. The goal of this research was to integrate the high throughput flip chip process on commercial flip chip packages that consisted of high lead solder balls on a polyimide passivated silicon die bonded with eutectic solder bumped pads on the laminate substrate interface (Qi, 1999). This involved extensive parametric experimentation that focused on the following elements: no-flow process evaluation and implementation on the commercial packages, reflow profile parameter effects on eutectic solder wetting of high lead solder bumps, interactions between the no-flow underfill materials and the package solder interconnect and tented via features, void capture and void formation during processing, and material set compatibility and the effects on long term reliability performance.

Reliability of FCOB with and without encapsulation

Flip chips were assembled on to ceramic boards using eutectic tin‐lead solder with underfill and with/without encapsulation for temperature cycling and high‐temperature‐high‐humidity tests. After 1.5 years of testing, the reliability performance of the flip chip on board (FCOB) assemblies was compared. All of the FCOB assemblies with underfill, but without encapsulation, survived 5,778 cycles of the temperature cycling test following 5,005 hours of the high‐temperature and high‐humidity test. The results show that encapsulation may not necessarily enhance the reliability of flip chip assemblies and might therefore be omitted.

Yield analysis and process modeling of low cost, high throughput flip chip assembly based on no-flow underfill materials

As a concept to achieve low-cost, high-throughput flip chip on board (FCOB) assembly, a new process has been developed implementing next generation flip chip processing based no-flow fluxing underfill materials. The low-cost, high throughput flip chip process implements large area underfill printing, integrated chip placement and underfill flow and simultaneous solder interconnect reflow and underfill cure. The goals of this study are to demonstrate feasibility of no flow underfill materials and the high throughput flip chip process over a range of flip chip configurations, identify the critical process variables affecting yield, analyze the yield of the high throughput flip chip process, and determine the impact of no-flow underfill materials on key process elements. Reported in this work is the assembly of a series of test vehicles to assess process yield and process defects. The test vehicles are assembled by depositing a controlled mass of underfill material on the chip site, aligning chip to the substrate pads, and placing the chip inducing a compression type underfill flow. The assemblies are reflowed in a commercial reflow furnace in an air atmosphere to simultaneously form the solder interconnects and cure the underfill. A series of designed experiments identify the critical process variables including underfill mass, reflow profile, placement velocity, placement force, and underfill material system. Of particular interest is the fact that the no-flow underfill materials studied exhibit an affinity for unique reflow profiles to minimize process defects.

Field reworkable underfill materials for flip chip on board assemblies

Studies have shown that underfill encapsulation dramatically improves the solder joint fatigue reliability of flip chip on board (FCOB) assemblies. The lack of reworkability of the underfill after the product is in the field has limited the integration of FCOB into cost sensitive electronic products and the continued proliferation of the FCOB technology will depend on the development of reworkable underfill materials systems. This paper presents data that correlates reliability performance to mechanical properties for twelve field reworkable underfill materials from three different suppliers. Their respective properties, processing parameters, and reliability performances are compared to the qualified, commercially available high performance underfills. Techniques were developed to redress the printed wiring board (PWB) site to enhance the reworked FCOB assembly yield. In addition, reliability performance results and failure analysis observations were compared to the first time nonreworked assemblies.

Thermal cycling analysis of flip-chip solder joint reliability

The reliability concern in flip-chip-on-board (FCOB) technology is the high thermal mismatch deformation between the silicon die and the printed circuit board that results in large solder joint stresses and strains causing fatigue failure. Accelerated thermal cycling (ATC) test is one of the reliability tests performed to evaluate the fatigue strength of the solder interconnects. Finite element analysis (FEA) was employed to simulate thermal cycling loading for solder joint reliability in electronic assemblies. This study investigates different methods of implementing thermal cycling analysis, namely using the "dwell creep" and "full creep" methods based on a phenomenological approach to modeling time independent plastic and time dependent creep deformations. There are significant differences between the "dwell creep" and "full creep" analysis results for the flip chip solder joint strain responses and the predicted fatigue life. Comparison was made with a rate dependent viscoplastic analysis approach. Investigations on thermal cycling analysis of the temperature range, (/spl Delta/T) effects on the predicted fatigue lives of solder joints are reported.

A Nested Finite Element Methodology (NFEM) for Stress Analysis of Electronic Products—Part II: Durability Analysis of Flip Chip and Chip Scale Interconnects

The nested finite element methodology (NFEM) presented in Part I of this series, is used in this paper to analyze the viscoplastic stress-state in a flip-chip-on-board (FCOB) and a chip scale package subjected to temperature cycling loads. The results are validated with conventional finite element method (CFEM). An energy-partitioning (EP) damage model is used to predict cycles to failure, based on the energy densities obtained from NFEM and CFEM, and results are compared with experiments.

The impact of underfill properties on the thermomechanical reliability of FCOB assembly

The impact of underfill properties on the thermomechanical reliability of flip chip on board (FCOB) assembly is addressed in this paper. FCOB assemblies using three underfill encapsulants were subjected to a thermal cycling test. The performance of the underfill encapsulants was assessed by a statistical analysis of the failure distribution of the FCOB assemblies. The failure modes in the thermal cycling test were found to be solder joint cracks, delamination at underfill/chip passivation interface, and underfill internal cracks. An attempt was made to correlate these failures with underfill properties such as the coefficient of thermal expansion (CTE), modulus, glass transition temperature (Tg), and adhesive strength to the chip. Additionally, nonlinear finite element analysis (FEA) was conducted to verify the experimental results.