Flip Chip Solder Joints Research Articles

Experimental Damage Mechanics of Micro/Power Electronics Solder Joints under Electric Current Stresses

Experimental damage mechanics of flip chip solder joints under current stressing is studied using 20 test vehicle flip chip modules. Three different failure modes are observed. The dominant damage mechanism is caused by the combined effect of electromigration and thermomigration, where void nucleation and growth lead to the ultimate failure of the module. It is observed that thermomigration driving forces are stronger than electromigration; as a result thermomigration, not electromigration, determines the site of void nucleation. The void nucleation and growth modes and their preferred sites are also observed and discussed in detail. The interface between the Ni barrier layer and the solder joint is found to be the favorite site of void nucleation and growth. The effect of pre-existing voids on the failure process of a solder joint is also studied. It is observed that Black’s time to failure law for thin films is unreliable for solder joints.

Intermetallic compound formation and morphology evolution in the 95Pb5Sn flip-chip solder joint with Ti/Cu/Ni under bump metallization during reflow soldering

Intermetallic compound formation and morphology evolution in the 95Pb5Sn flip-chip solder joint with the Ti/Cu/Ni under bump metallization (UBM) during 350°C reflow for durations ranging from 50 sec to 1440 min were investigated. A thin intermetallic layer of only 0.4 µm thickness was formed at the 95Pb5Sn/UBM interface after reflow for 5 min. When the reflow was extended to 20 min, the intermetallic layer grew thicker and the phase identification revealed the intermetallic layer comprised two phases, (Ni,Cu)3Sn2 and (Ni,Cu)3Sn4. The detection of the Cu content in the intermetallic compounds indicated that the Cu atoms had diffused through the Ni layer and took part in the intermetallic compound formation. With increasing reflow time, the (Ni,Cu)3Sn4 phase grew at a faster rate than that of the (Ni,Cu)3Sn2 phase. Meanwhile, irregular growth of the (Ni,Cu)3Sn4 phase was observed and voids formed at the (Ni,Cu)3Sn2/Ni interface. After reflow for 60 min, the (Ni,Cu)3Sn2 phase disappeared and the (Ni,Cu)3Sn4 phase spalled off the NI layer in the form of a continuous layer. The gap between the (Ni,Cu)3Sn4 layer and the Ni layer was filled with lead. A possible mechanism for the growth, disappearance, and spalling of the intermetallic compounds at the 95Pb5Sn/UBM interface was proposed.

Three-dimensional simulation on current-density distribution in flip-chip solder joints under electric current stressing

Three-dimensional simulations on current-density distribution in solder joints under electric current stressing were carried out by finite element method. Five underbump metallization (UBM) structures were simulated, including Ti∕Cr–Cu∕Cu thin-film UBM, Al∕Ni(V)∕Cu thin-film UBM, Cu thick-film UBM, Ni thick-film UBM, and Cu∕Ni thick-film UBM. The maximum current density inside the solder occurs in the vicinity of the entrance of the Al trace into the solder joint, while there is no obvious current crowding effect in the substrate side of the joint. The crowding ratio, which is defined as the maximum current density inside the solder divided by the average value in the UBM opening, is as high as 24.7 for the solder with the Ti∕Cr–Cu∕Cu UBM. However, it decreases to 23.4, 13.5, 8.7, and 7.2 for the rest of the UBM structures, respectively. Solder joints with thick UBMs were found to have a better ability to relieve the current crowding effect. The simulation results are in reasonable agreement with limited published data. The solder joints with higher current crowding ratios have a shorter electromigration failure time.

Effect of current crowding and Joule heating on electromigration-induced failure in flip chip composite solder joints tested at room temperature

The electromigration of flip chip solder joints consisting of 97Pb–3Sn and 37Pb–63Sn composite solders was studied under high current densities at room temperature. The mean time to failure and failure modes were found to be strongly dependent on the change in current density. The composite solder joints did not fail after 1month stressed at 4.07×104A∕cm2, but failed after just 10h of current stressing at 4.58×104A∕cm2. At a slightly higher current stressing of 5.00×104A∕cm2, the composite solder joints failed after only 0.6h due to melting. Precipitation and growth of Cu6Sn5 at the cathode caused the Cu under bump metallurgy to be quickly consumed and resulted in void formation at the contact area. The void reduced the contact area and displaced the electrical path, affecting the current crowding and Joule heating inside the solder bump. Significant Joule heating inside solder bumps can cause melting of the solder and quick failure. The effect of void propagation on current crowding and Joule heating was confirmed by simulation.

Fracture mechanics analysis of the effect of substrate flexibility on solder joint reliability

Solder joint fatigue failure is a serious reliability concern in area array technologies, such as flip chip and ball grid array packages of integrated-circuit chips. The selection of different substrate materials could affect solder joint thermal fatigue life significantly. The reliability of solder joints in real flip chip assembly with both rigid and compliant substrates was evaluated by the accelerated temperature cycling test and thermal mechanical analysis. The mechanism of substrate flexibility on improving solder joint thermal fatigue lifetime was investigated by fracture mechanics methods. Two different methods (crack tip opening displacement, CTOD and virtual crack closure technique, VCCT) are used to determine the crack tip parameters which are considered as the indices of reliability of solder joints, including the strain energy release rate and phase angle for the different crack lengths and temperatures. It was found that the thermal fatigue lifetime of solder joints in flip chip on flex assembly (FCOF) was much longer than that of flip chip on rigid board assembly (FCOB). The flex substrates could dissipate energy that otherwise would be absorbed by solder joints, that is, substrate flexibility has a great effect on solder joint reliability and the reliability improvement was attributed to flex buckling or bending during thermal cycling.

Growth Kinetics of Intermetallic Compound and Interfacial Reactions in Pb-Free Flip Chip Solder Bump during Solid State Isothermal Aging

In the present work, the growth kinetics of intermetallic compound layer formed in Sn-3.5Ag flip chip solder joints by solid-state isothermal aging was examined at temperatures between 80 and 150 °C for 0 to 60 days. The bumping for the flip chip devices was performed using an electroless under bump metallization. The quantitative analyses were performed on the intermetallic compound layer thickness as a function of aging time and aging temperature. The layer growth of the Ni3Sn4 intermetallic compound followed a parabolic law within a given temperature range. As a whole, because the value of the time exponent (n) is approximately equal to 0.5, the layer growth of the intermetallic compound was mainly controlled by diffusion mechanism in the temperature range studied. The apparent activation energy of the Ni3Sn4 intermetallic was 49.63 kJ/mol.

Effect of aging conditions on interfacial reaction and mechanical joint strength between Sn–3.0Ag–0.5Cu solder and Ni–P UBM

The interfacial microstructure of Sn–3.0Ag–0.5Cu solder with electroless Ni/immersion Au (ENIG) was studied using SEM, EPMA and TEM. (Cu,Ni) 6Sn 5 intermetallic compound layer was formed at the interface between the solder and Ni–P UBM upon reflow. However, after isothermal aging the AuSn 4, with a certain amount of Ni dissolved in it, i.e. (Au,Ni)Sn 4 appeared above the (Cu,Ni) 6Sn 5 layer. Two distinctive layers, P-rich and Ni–Sn–P, were additionally found from the TEM observation. The analytical studies using EDS in TEM revealed that the averaged composition of the P-rich layer is close to that of a mixture of Ni 3P and Ni, while that of the Ni–Sn–P layer is analogous to the P-rich layer but containing a small amount of Sn in it. Shear force of the flip chip solder joints decreased during aging at various temperatures. The decrease in shear force was mainly caused by the coarsening of microstructure within the solder and increase of the interfacial intermetallic compound thickness. Nearly all of the test specimens showed ductile failure mode and this could be well explained with the results of FEM analyses.

Polarity effect of electromigration on kinetics of intermetallic compound formation in Pb-free solder V-groove samples

Intermetallic compound (IMC) formation is critical for the reliability of microelectronic interconnections, especially for flip chip solder joints. In this article, we investigate the polarity effect of electromigration on kinetics of IMC formation at the anode and the cathode in solder V-groove samples. We use V-groove solder line samples, with width of 100 μm and length of 500–700 μm, to study interfacial IMC growth between Cu electrodes and Sn-3.8Ag-0.7Cu (in wt %) solder under different current density and temperature settings. The current densities are in the range of 103 to 104A∕cm2 and the temperature settings are 120, 150, and 180 °C. While the same types of IMCs, Cu6Sn5 and Cu3Sn, form at the solder∕Cu interfaces independent of the passage of electric current, the growth of the IMC layer has been enhanced by electric current at the anode and inhibited at the cathode, in comparison with the no-current case. We present a kinetic model, based on the Cu mass transport in the sample, to explain the growth rate of IMC at the anode and cathode. The growth of IMC at the anode follows a parabolic growth rule, and we propose that the back stress induced in the IMC plays a significant role. The model is in good agreement with our experimental data. We then discuss the influence of both chemical force and electrical force, and their combined effect on the IMC growth with electric current.

In situ observation of the void formation-and-propagation mechanism in solder joints under current-stressing

The electromigration of PbSn eutectic flip-chip solder joints was studied at 30 °C with a nominal current density of 4 × 10 4 A/cm 2. The void formation-and-propagation failure mechanism was observed in situ. In the joint with electrons flowing from the chip side to the substrate side, a void nucleated near the current crowding region after an incubation period that lasted between 30 and 50 min. This void then propagated across the under bump metallurgy very quickly, and eventually resulted in the failure of the solder joint in about another 40 min. The failure was concurrent with the melting of the joint. The joint with electrons flowing from the substrate to the chip side survived the current stressing. This failure mechanism directly reflects that current crowding is a dominant factor responsible for failure in flip-chip solder joints. This study shows that the incubation time of void nucleation is a good indicator of the real lifetime of a joint under current-stressing.

Electromigration Induced Metal Dissolution in Flip-Chip Solder Joints

The failure of flip chip solder joints through the dissolution of the Cu metallization was studied. From the location and geometry of the dissolved Cu, it can be concluded that current crowding played a critical role in the dissolution. It can also be concluded that temperature, as an experimental variable, is not less import than the current density in electromigration study. Experimentally, no evidence of mass transport due to thermomigration was observed.

Electromigration-induced failure in flip-chip solder joints

The electromigration failure mechanism in flip-chip solder joints through the rapid dissolution of the Cu metallization was studied in detail. The ambient temperature was found to be a very important factor in this failure mechanism. When the ambient temperature was changed from 100°C to 70°C, the time to failure changed from 95 min to 31 days. The results of this study indicate that temperature, as an experimental variable, is not less important than the current density in electromigration study. The surface temperatures of the chip and substrate during electromigration were also measured. The temperature of the Si chip was reasonably homogeneous because of the fact that Si is a very good thermal conductor. It was also reasoned that the high thermal conductivity of the PbSn solder could not support a temperature gradient large enough to induce thermomigration across the solder joint in the present study. Experimentally, no evidence of mass transport caused by thermomigration was observed.

Effect of substrate flexibility on solder joint reliability. Part II: finite element modeling

Solder joint fatigue failure is a serious reliability concern in area array technologies, such as flip chip and ball grid array packages of integrated-circuit chips. The selection of different substrate materials could affect solder joint thermal fatigue life significantly. The mechanism of substrate flexibility on improving solder joint thermal fatigue was investigated by thermal mechanical analysis (TMA) technique and finite element modeling. The reliability of solder joints in real flip chip assembly with both rigid and compliant substrates was evaluated by accelerated temperature cycling test. Finite element simulations were conducted to study the reliability of solder joints in flip chip on flex assembly (FCOF) and flip chip on rigid board assembly (FCOB) applying Anand model. Based on the finite element analysis results, the fatigue lives of solder joints were obtained by Darveaux’s crack initiation and growth model. The thermal strain/stress in solder joints of flip chip assemblies with different substrates were compared. The results of finite element analysis showed a good agreement with the experimental results. It was found that the thermal fatigue lifetime of FCOF solder joints was much longer than that of FCOB solder joints. The thermal strain/stress in solder joints could be reduced by flex buckling or bending and flex substrates could dissipate energy that otherwise would be absorbed by solder joints. It was concluded that substrate flexibility has a great effect on solder joint reliability and the reliability improvement was attributed to flex buckling or bending during temperature cycling.

Cross-interaction of under-bump metallurgy and surface finish in flip-chip solder joints

The cross-interaction of the under-bump metallurgy (UBM)/solder interface and the solder/surface-finish interface in flip-chip solder joints was investigated. In this study, the UBM on the chip side was a single layer of Cu (8.5 µm), and the surface finish on the substrate side was a 0.2-µm Au layer over 5-µm Ni. It was shown that, after two reflows, the Ni layer of the surface finish had been covered with (Cu1−xNix)6Sn5. This shows that the effect of cross-interaction of the two interfaces is important even during the reflow stage. During subsequent solid-state aging at 115°C, 135°C, and 155°C, the formation of (Cu1−xNix)6Sn5 over the Ni layer was found to have the effect of reducing the Ni consumption rate. At the same time, the Cu consumption rate of the UBM was accelerated. The results of this study show that the selection of the UBM and the surface finish has to be considered together because the cross-interaction of the two interfaces plays an important role.

Reliability Analysis and Design for the Fine-Pitch Flip Chip BGA Packaging

The geometry of solder joints in the flip chip technologies is primarily determined by the associated solder volume and die/substrate-side pad size. In this study, the effect of these parameters on the solder joint reliability of a fine-pitched flip chip ball grid array (FCBGA) package is extensively investigated through finite element (FE) modeling and experimental testing. To facilitate thermal cycling (TC) testing, a simplified FCBGA test vehicle with a very high pin counts (i.e., 2499 FC solder joints) is designed and fabricated. By the vehicle, three different structural designs of flip chip solder joints, each of which consists of a different combination of these design parameters, are involved in the investigation. Furthermore, the associated FE models are constructed based on the predicted geometry of solder joints using a force-balanced analytical approach. By way of the predicted solder joint geometry, a simple design rule is created for readily and qualitatively assessing the reliability performance of solder joints during the initial design stage. The validity of the FE modeling is extensively demonstrated through typical accelerated thermal cycling (ATC) testing. To facilitate the testing, a daisy chain circuit is designed, and fabricated in the package for electrical resistance measurement. Finally, based on the validated FE modeling, parametric design of solder joint reliability is performed associated with a variety of die-side pad sizes. The results show that both the die/substrate-side pad size and underfill do play a significant role in solder joint reliability. The derived results demonstrate the applicability and validity of the proposed simple design rule. It is more surprising to find that the effect of the contact angle in flip chip solder joint reliability is less significant as compared to that of the standoff height when the underfill is included in the package.

Effect of Underfill Entrapment on the Reliability of Flip-Chip Solder Joint

The application of underfill materials to fill up the room between the chip and substrate is known to substantially improve the thermal fatigue life of flip chip solder joints. Nowadays, no-flow underfill materials are gaining much interest over traditional underfill as the application and curing of this type of underfill can be undertaken before and during the reflow process and thus aiding high volume throughput. However, there is always a potential chance of entrapping no-flow underfill in the solder joints. This work, attempts to find out the extent of underfill entrapment in the solder joints and its reliability effect on the flip chip packages. Some unavoidable underfill entrapments at the edges of the joint between solder bumps and substrate pads are found for certain solder joints whatever bonding conditions are applied. It is interesting to report for the first time that partial underfill entrapment at the edges of the solder joint seems to have no adverse effect on the fatigue lifetime of the samples since most of the first solder joint failure in the no-flow flip chip samples during thermal cycling are not at the site of solder interconnection with underfill entrapment. Our modeling results show good agreement with the experiment that shows underfill entrapment can actually increase the fatigue lifetime of the no-flow flip chip package.

Effects of the gold thickness of the surface finish on the interfacial reactions in flip-chip solder joints

The effects of Au thickness on the flip-chip solder joints with Cu/Ni/Al underbump metallurgy (UBM) on one end and the Au/Ni surface finish on another was studied. Two different thicknesses, 0.1 µm and 0.65 µm, were used for the surface finish. After assembly, the joints were subjected to thermal aging at 150°C. The difference in Au thickness had a strong effect on the consumption rate of the Ni layer in the UBM as well as on the failure mode of the solder joints. When the Au layer was thin (0.1 µm), the dissolved Cu from the Cu/Ni UBM was able to inhibit the formation of AuSn4. When the Au layer was thick (0.65 µm), the dissolved Cu was not able to inhibit the formation of AuSn4. These AuSn4 enhanced the Ni consumption rate of the UBM. The presence of a large amount of AuSn4 inside the solder also weakened the solder because of the Au embrittlement effect. In view of these observations, the gold thickness on the Au/Ni surface finish must be kept to the minimum controlled in order to prolong the service life of flip-chip packages.

Mechanical Implications of High Current Densities in Flip-chip Solder Joints

We studied the electromigration damage to flip-chip solder joints of eutectic Sn/Pb under current stressing at room temperature with a current density of 1.3 × 104 A/cm2. The height of the solder joints was 100 μm. The mass accumulation near the anode side and the void nucleation near the cathode were observed during current stressing. In the preliminary experiment, the surface marker movement technique was used to measure the atomic flux driven by electromigration and to calculate the product of effective charge number and diffusivity (D × Z*) of the solder. Subsequent experiments revealed that the presence of thermomigration due to joule heating makes the extraction of the product of effective charge number and diffusivity erroneous when using marker movement technique.

Failure Modes of Flip Chip Solder Joints Under High Electric Current Density

The failure modes of flip chip solder joints under high electrical current density are studied experimentally. Three different failure modes are reported. Only one of the failure modes is caused by the combined effect of electromigration and thermomigration, where void nucleation and growth contribute to the ultimate failure of the module. The Ni under bump metallization–solder joint interface is found to be the favorite site for void nucleation and growth. The effect of pre-existing voids on the failure mechanism of a solder joint is also investigated

A Study of Electromigration in 3-D Flip Chip Solder Joint Using Numerical Simulation of Heat Flux and Current Density

This paper applies an analogy between heat flow and current flow to examine the current density distribution in a solder interconnect, which has a direct relationship with the atomic flux movement. From a three-dimensional heat conduction analysis, we discover that the heat flux distribution in the solder bump is a strong function of the direction of heat flow. If the heat flow turns 90/spl deg/ when it leaves the solder bump, the high heat flux region will also turn 90/spl deg/. From a cross-sectional view of the mean heat flux, the high heat flux (or current flux) region in the solder moves from the top of the under-bump-metallurgy region to the lower right corner, and the right side of the solder has the highest flux density. This result correlates well with the experimental data where the measured atomic flux in the left side of the solder is less than in the right side. Two other cases with 0 and 180/spl deg/ heat flows also illustrate the difference in heat flux distribution. This suggests that the current density distribution in the solder changes as the direction of the current flow changes.

Residual stress and interfacial reaction of the electroplated Ni-Cu alloy under bump metallurgy in the flip-chip solder joint

Pure Ni, the Ni-Cu alloy, and pure Cu layers as the under bump metallurgy (UBM) for a flip-chip solder joint were deposited by electrolytic plating. For the pure Ni layer, residual stress can be controlled by adding a wetting agent and decreasing current density, and it is always under tensile stress. The Ni-Cu alloys of different Cu compositions from ∼20wt.%Cu to 100wt.%Cu were deposited with varying current density in a single bath. The residual stress was a strong function of current density and Cu composition. Decreasing current density and increasing Cu content simultaneously causes the residual stress of the metal layers to sharply decrease. For the pure Cu layer, the stress is compressive. The Cu layer acts as a cushion layer for the UBM. The residual stress of the UBM strongly depends on the fraction of the Cu cushion layer. Interfacial reaction of the UBM with Sn-3.5 wt.% Ag was studied. As the Cu contents of Ni-Cu alloys increased, the dissolution rate increased. Several different intermetallic compounds (IMCs) were found. The lattice constants of alloys and the IMC increase with increasing Cu contents because the larger Cu atoms substitute for the smaller Ni atoms in the crystallites. The Cu content of the IMC are strongly dependent on the composition of the alloys. Ball shear tests were done with different metal-layer schemes. The failure occurs through the IMC and solder.