Flip Chip Interconnection Research Articles

40 $\mu{\rm m}$ Flip-Chip Process Using Ag–In Transient Liquid Phase Reaction

A flip-chip interconnect process at 180°C using the silver-indium (Ag-In) binary system is reported. An array of 50 × 50 flip-chip joints with 100 μm pitch and 40 μm joint diameter was fabricated. Each joint has the column structure of Ag/(Ag)/Ag2In/(Ag) that connects the silicon (Si) chip to the copper (Cu) substrate. The joint height is approximately 50 μm. In this structure, Ag2In is a dominating intermetallic compound in the Ag-In system with melting temperature of 660°C. (Ag) is a solid solution phase of Ag with In composition up to 20 at.%. It has a solidus temperature range of 695 to 962°C depending on In composition. In long-term operation, (Ag)/Ag2In/(Ag) is expected to gradually convert to a single (Ag) phase, which is more reliable. Thus, the flip-chip joints will get better in use. In fabrication, 50 × 50 Ag columns were made on Si wafer coated with chromium (Cr) and gold (Au). The Cu substrate was electroplated with Ag(10 μm)/In(5 μm)/Ag(thin). Si chips with Ag columns were bonded to Cu substrates at 180°C for 5 min. No flux was used. Cross-sectional scanning electron microscopy images show that all 50 Ag columns in one row are well bonded to the Cu substrate without visible voids or cracks. Energy-dispersive X-ray spectroscopy data indicate that the resulting column structure is Ag/(Ag)/Ag2In/(Ag). The process temperature of this new interconnect method is 80 °C below the typical reflow temperature of tin-based lead-free solders.

40 μm Copper–Silver Composite Flip-Chip Interconnect Technology Using Solid-State Bonding

Copper–silver (Cu–Ag) composite flip-chip interconnect between silicon (Si) chips and Cu substrates is demonstrated. Array of Cu–Ag columns, each 28 μm in height and 40 μm in diameter, is electroplated on 2-in. Si wafers coated with chromium (Cr)/gold (Au) dual layer. The Si wafers are diced into 6 mm × 6 mm chips, each containing 50 × 50 Cu–Ag columns. The Si chip with Cu–Ag columns is bonded to Cu substrates at 260 °C in 80 mTorr vacuum. A bonding force of only 1.8 kg is applied, corresponding to 0.71 g per Cu–Ag column. During bonding, Ag atoms in Cu–Ag columns deform and their surfaces conform to and mate with the surface of Cu substrate. Solid-state bonding incurs when Ag atoms in Cu–Ag columns and Cu atoms in Cu substrates are brought within atomic distance so that they share conduction electrons. The Cu–Ag columns are indeed bonded to the Cu. No molten phase is involved in the bonding. The joint consists of 60% Cu section and 40% Ag section. The ductile Ag is able to accommodate the thermal expansion mismatch between Si and Cu. The Cu–Ag joints do not contain any intermetallic compound (IMC). This interconnect technology avoids all reliability issues associated with IMC growth in conventional soldering processes. Compared to tin-based lead-free solder joints, Cu–Ag composite joints have superior electrical and thermal properties.

A Fully SiP Integrated $V$-Band Butler Matrix End-Fire Beam-Switching Transmitter Using Flip-Chip Assembled CMOS Chips on LTCC

In this paper, a fully system-in-package (SiP) integrated V-band Butler matrix beam-switching transmitter (TX) is presented. The CMOS chips from differential process technologies are assembled on a low-temperature co-fired ceramic (LTCC) substrate carrier by flip-chip interconnects. The vertically embedded folded monopole antenna is designed and integrated into the LTCC. The array consisting of four identical monopole antennas and a Butler matrix for beam switching is realized on the LTCC for loss reduction. Four switched main beams are measured and agree well with simulation. This beam-forming TX shows the potential of the low-cost millimeter-wave SiP with CMOS chips.

150℃이하 저온에서의 미세 접합 기술

Recently, flip chip interconnection has been increasingly used in microelectronic assemblies. The common Flip chip interconnection is formed by reflow of the solder bumps. Lead-Tin solders and Tin-based solders are most widely used for the solder bump materials. However, the flip chip interconnection using these solder materials cannot be applied to temperature-sensitive components since solder reflow is performed at relatively high temperature. Therefore the development of low temperature bonding technologies is required in these applications. A few bonding techniques at low temperature of <TEX>$150^{\circ}C$</TEX> or below have been reported. They include the reflow soldering using low melting point solder bumps, the transient liquid phase bonding by inter-diffusion between two solders, and the bonding using low temperature curable adhesive. This paper reviews various low temperature bonding methods.

Flip-Chip-Assembled $W$-Band CMOS Chip Modules on Ceramic Integrated Passive Device With Transition Compensation for Millimeter-Wave System-in-Package Integration

In this paper, W-band flip-chip-assembled CMOS chip modules with transition compensation are presented, a three-stage amplifier, a balanced amplifier, and a down-converted Gilbert-cell subharmonic mixer are included in the chip set. The flip-chip process on ceramic integrated passive devices (CIPD) with a bump size of 30 μm × 30 μm × 27 m is developed for millimeter-wave applications. Without the flip-chip transition compensation, the frequency of the return loss of each chip is shifted, which deviates from the bare die measurement results. By applying the compensation network in the transition, the dips of the return loss are tuned back closer to the bare die measurement results. Moreover, a W-band amplifier flip-chip-assembled with a CPW-fed Yagi-Uda antenna on a CIPD and a W-band flip-chip-assembled receiver are presented for SiP integration. The effect of dicing edge variation is also included in the flip-chip model to achieve reasonable agreement between simulated and measured scattering parameters. To the best of our knowledge, this is the first demonstration of a CMOS chip set with flip-chip interconnects in the -band for a system-in-package.

60-GHz Band Copper Ball Vertical Interconnection for MMW 3-D System-in-Package Front-End Modules

In order to realize millimeter-wave (MMW) 3-D system-in-package (SiP) front-end modules, we propose a 60-GHz band copper ball vertical interconnection structure, which interconnects between vertically stacked substrates. The structure enables ICs to be placed between the vertically stacked substrates. Since the diameter of the copper balls must exceed the thickness of the ICs, the distance between the substrates in the modules is larger than that of the flip-chip interconnection widely used in the MMW-band. Therefore, the conventional flip-chip interconnection does not scale for the interconnection between the substrates in MMW 3-D SiP front-end modules. The layout of grounded copper balls and the patterns of inner ground layers in the upper/lower substrates are designed using 3-D electromagnetic field simulation. The designed structure allows less than 1dB transmission loss up to 71.1GHz, compared with a through transmission line. The result is verified with fabrication and measurement and confirms the feasibility of MMW 3-D SiP front-end modules.

Assessment of XRF Technique as a Method to Measure Percent Ag in SnAg Solders for Flip Chip Applications

Pb-free SnAg solder has become the industry standard for fabricating flip chip interconnects utilizing C4 (controlled collapse chip connection) technology. One area of interest for manufacturability of Pb-free solders is the ability to control and measure the %Ag composition and its variation from wafer to wafer, chip to chip, and C4 to C4. There are various ways to measure solder composition. These are divided into two categories which are invasive and non-invasive referring to whether solder must be removed from the wafer in order to conduct the measurement. There are a variety of invasive methods including Atomic Absorption (AA), Differential Scanning Calorimetry (DSC), Inductively Coupled Plasma (ICP) and Electron Probe Micro-Analyzer (EPMA) used with cross sections. Non-invasive methods are limited, making the development of the non-invasive X-Ray Fluorescence (XRF) method an important technique to determine both the thickness and composition of C4s on wafers without modifying the wafer. There are many factors which can affect the accuracy of the XRF measurements. These include bump geometry, composition, UBM (under bump metallurgy) stack, bump spatial density, underlying chip wiring, tool vibration and tool parameters, such as collimator size, power levels, scan time, etc. This paper will address the implementation issues in utilizing XRF for Pb-free solder SnAg systems. The paper will describe:(1) Experimental bumping variables,(2) XRF configuration, calibration, optimized measuring methodology and the importance of having known standards with the same dimensions of the bumps being measured(3) Measuring accuracy and correlation with ICP and DSC,(4) Ag distribution study in the die and wafer level

Effect of preformed IMC Layer on Electromigration of Solder Capped Cu Pillar Bump Interconnection on an organic substrate

The electromigration behavior of 80 μm pitch solder capped Cu pillar bump interconnection on an organic carrier is studied and discussed. Recently the solder capped Cu pillar bump technology has been widely used in mobile applications as a peripheral ultra fine pitch flip chip interconnection technique. The solder capped Cu pillar bumps are formed on Al pads which are commonly used in wirebonding technique. It allows us an easy control of the space between the die and the substrate simply by varying the Cu pillar height. Since the control of the collapse of the solder bumps is not necessary, the technology is called the “C2 (Chip Connection)”. Solder capped Cu pillar bumps are connected to OSP surface treated Cu substrate pads on an organic substrate by reflow with a no-clean process, hence the C2 is a low cost ultra fine pitch flip chip interconnection technology. It is an ideal technology for the systems requiring fine pitch structures. In 2011, the EM tests were performed on 80 μm pitch solder capped Cu pillar bump interconnections and the effects of Ni barrier layers on the Cu pillars and the preformed intermetallic compound (IMC) layers on the EM tests were studied. The EM test conditions of the test vehicles were 7–10 kA/cm2 at 125–170°C. The Cu pillar height was 45 μm and the solder height was 25 μm. The solder composition was Sn-2.5Ag. Aged condition for pre-formed IMCs was 2,000 hours at 150°C. It was shown that the formation of the pre-formed IMC layers and the insertion of Ni barrier layers are effective in reducing the Cu atoms dissolution. In this report, it is studied that which of the IMC layers, Cu3Sn or Cu6Sn5, is more effective in preventing the Cu atom dissolution. The cross-sectional analyses of the joints after the 2000 hours of the test with 7kA/cm2 at 170°C were performed for this purpose. The relationship between the thickness of Cu3Sn IMC layer and the Cu migration is also studied by performing the current stress tests on the joints with controlled Cu3Sn IMC thicknesses. The samples were thermally aged prior to the tests at a higher temperature (200°C) and in a shorter time (10–50 hours) than the previous experiments. The cross-sectional analyses of the Sn-2.5Ag joints without pre-aging consisting mostly of Cu6Sn5, showed a significant Cu dissolution while the Cu dissolution was not detected for the pre-aged joints with thick Cu3Sn layers. A large number of Kirkendall voids were also observed in the joints without pre-aging. The current stress tests on the controlled Cu3Sn joints showed that Cu3Sn layer thickness of more than 1.5 μm is effective in reducing Cu dissolution in the joints.

Affect of Anneal Temperature on All-Copper Flip-Chip Connections Formed via Electroless Copper Deposition

A fabrication technique for bonding discrete copper surfaces using electroless deposition has been developed in order to form all-copper flip-chip interconnects. The electroless copper fillet which bonds the two copper surfaces would replace solder as the electrical and mechanical connection mechanism at the first-level of packaging. An organic-additive free electroless bath was used to bond adjacent copper surfaces. The effect of anneal temperature on the electroless bond was analyzed. The electroless bond strength was shown to increase as a function of anneal temperature through the elimination of entrapped hydrogen and recrystallization of the copper. The seam between the intimately mated copper surfaces was removed at temperatures as low as 100°C.

New Flip-Chip Interconnect Technology for High Performance and High Reliability Applications

As the current and next generation devices are embracing geometries below 28nm and requiring softer low-K dielectric isolation on very thin large silicon dies ∼ to perform a reliable die-to-package interconnect is becoming a challenge. Further, the high pressure from Cu wire bonding and high reflow temperature of conventional flip-chip bonding often results in damage of device structure. A new flip-chip bonding technology has been developed for such critical applications, and is claimed to be “damage free”. It uses soft bump made by non-full cured conductive paste on the package substrate. These soft bumps require ultra-low bonding pressure on the pad of the die. Thus the bonding process don't make any damage on ULK isolation layer. Details of the process, material sets used for such fragile device structures have been discussed. Reliability results are shared, which further ensures the robustness of this process. Finally, the cost advantage through adaptation of this process has also been elaborated.

Electromigration Performance of Flip-Chips with Lead-Free Solder Bumps between 30 μm and 60 μm Diameter

As the solder bump sizes continuously decrease with scaling of the geometries, current densities within individual solder bumps will increase along with higher operation temperatures of the dies. Since electromigration of flip-chip interconnects is highly affected by these factors and therefore an increasing reliability concern, long-term characterization of new interconnect developments needs to be done regarding the electromigration performance using accelerated life tests. Furthermore, a large temperature gradient exists across the solder interconnects, leading to thermomigration. In this study, a comprehensive overlook of the long-term reliability and analysis of the achieved electromigration performance of flip-chip test specimen will be given, supplemented by an in-depth material science analysis. In addition, the challenges to a better understanding of electromigration and thermomigration in ultra fine-pitch flip-chip solder joints are discussed. For all experiments, specially designed flip-chips with a pitch of 100 μm and solder bump diameters of 30–60 μm have been used [1]. Solder spheres can be made of every lead-free alloy (in our case SAC305) and are placed on a UBM which has been realized for our test chips in an electroless nickel process [2]. For the electromigration tests within this study, multiple combinations of individual current densities and temperatures were adapted to the respective solder sphere diameters. Online measurements over a time period up to 10,000 hours with separate daisy chain connections of each test coupon provide exact lifetime data during the electromigration tests. As failure modes have been identified: UBM consumption at the chip side or depletion of the Nickel layer at the substrate side, interfacial void formation at the cathode contact interface, and - to a much lesser degree - Kirkendall-like void formation at the anode side. A comparison between calculated life time data using Weibull distribution and lognormal distribution will be given.

Current-induced interfacial reactions in Ni/Sn–3Ag–0.5Cu/Au/Pd(P)/Ni–P flip chip interconnect

Abstract

Flip-Chip Packaging of Low-Noise Metamorphic High Electron Mobility Transistors on Low-Cost Organic Substrate

The rapid growth of high-frequency wireless communication demands high-performance packaging structures at low cost. A flip-chip interconnect is one of the most promising technologies owing to its low parasitic effect and high performance at high frequencies. In this study, the in-house fabricated In0.6Ga0.4As metamorphic high electron mobility transistor (mHEMT) device was flip-chip-assembled using a commercially available low-cost organic substrate. The packaged device with the optimal flip-chip structure exhibited almost similar DC and RF results to the bare die. An exopy-based underfill was applied to the improvement of reliability with almost no degradation of the electrical characteristics. Measurement results revealed that the proposed packaging structure maintained a low minimum noise figure of 3 dB with 6 dB associated gain at 62 GHz. Such a superior performance after flip-chip packaging demonstrates the feasibility of the proposed low-cost organic substrate for commercial high-frequency applications up to the W-band.

40 μm Silver Flip-Chip Interconnect Technology With Solid-State Bonding

Formation of pure silver (Ag) flip-chip interconnect of silicon (Si) chips on copper (Cu) substrates is reported. Arrays of Ag columns, each 36 μm in height and 40 μm in diameter, are fabricated on 2-in. Si wafers which are first coated with chromium (Cr)/gold (Au) dual layers. The Si wafers are diced into 6 mm × 6 mm chips, each having 50 × 50 Ag columns. The Si chip with Ag columns is directly bonded to Cu substrate at 260 °C in 80 mTorr vacuum to inhibit oxidation. The static bonding pressure is as low as 680 psi (4.69 MPa), corresponding to a load of 0.021 oz (0.60 g) per column. During bonding, the Ag columns deform and conform to the Cu substrate. They are well bonded to the Cu. No molten phase is involved in the bonding process. The joints consist of pure Ag only. The ductile Ag joints are able to accommodate the thermal expansion mismatch between Si and Cu. It is well known that in nearly all soldering processes used in electronic industries, intermetallic compound (IMC) formation is essential to make a solder joint. In the pure Ag interconnect, no IMCs exist. Thus, reliability issues associated with IMCs are eliminated. Compared to tin-based lead-free solders, pure Ag joints have superior electrical and thermal properties.

Adhesion and Evaluation of Thermoplastic Nonconductive Film Materials in Flip Chip for Fine-Pitch Chip-on-Flex

In this paper, flip-chip interconnections were made on very flexible polyethylene naphthalate substrates using nonconductive films (NCFs). In general, the NCF/underfill materials are both epoxy thermosetting substances, and it was found that the curing process would increase the internal stress, shrinkage, and warpage. Therefore, the use of thermalplastic materials might solve these problems. Such materials provide lower water absorption at 0.56 ± 0.05% and curing for 4 h at 150 ± 10°C for the elimination of voids. The chip-on-flex (COF) parameters are a bonding temperature of 400 ± 10°C, a bonding force of 95 ± 5 N, and a bonding time of 0.4 ± 0.1 s. The workability test shows that the Au/Sn eutectic condition has fine adhesion for leads and bumps, and the bond accuracy is controlled in less than one-third bump space. The COF products were able to pass all the reliability tests, including the highly accelerated stress, high-temperature storage life, low-temperature storage life, temperature cycling, and pressure cooker tests. The results indicate that the COF assemblies exhibit fine performance in the reliability, workability, and simulation tests. Thus, the NCF thermoplastic materials are suitable for replacing thermosetting materials, and can be applied in fine pitch to improve the reliability issues associated with COF products.

Application of Synchrotron Radiation X-Ray Microtomography to Nondestructive Evaluation of Thermal Fatigue Process in Flip Chip Interconnects

New nondestructive inspection methods with high spatial resolution are expected to support the evaluation and enhancement of the reliability of microjoints on printed circuit boards. An X-ray microtomography system, the SP-μCT has been developed at the Super Photon ring-8 GeV (SPring-8), the largest synchrotron radiation facility in Japan. In this work, the SP-μCT was first applied to the nondestructive evaluation of thermal fatigue phenomena, namely microstructure evolution (i.e., phase growth) and microcrack propagation, appearing in actual solder microbumps of flip chip interconnects due to thermal cyclic loading. In addition, a refraction-contrast imaging technique was simultaneously applied to visualize the fatigue cracks with an actual opening of less than 100 nm. The observed specimen has a flip chip structure joined by Sn-37wt%Pb eutectic solder bumps 150 μm in diameter. Consequently, the process of phase growth and crack propagation was determined via observation of consecutive computed tomography (CT) images obtained in the same plane of the same specimen. As the thermal cycle proceeded, remarkable phase growth was clearly observed, followed by the appearance of fatigue cracks in the corners of the interfaces between the solder bump and Cu pad. Moreover, the CT images also enabled us to evaluate the fatigue lifetime of the bumps, as follows. The lifetime to fatigue crack initiation was estimated by quantifying the increase in the phase growth. The crack propagation lifetime to failure was then determined by measuring the average crack propagation rate. Such results have not been obtainable at all by X-ray CT systems for industrial use and demonstrate the possibility of nondestructive inspection by a synchrotron radiation X-ray microtomography system.

Wafer-Level Packages Using Anisotropic Conductive Adhesives (ACAs) Solution for Flip-Chip Interconnections

In this paper, wafer-level packages (WLPs) using an anisotropic conductive adhesives (ACAs) solution have been newly developed for flip-chip interconnections. WLPs using ACAs (ACA-WLPs) reduce processing steps compared to WLPs using anisotropic conductive films (ACFs), because ACA solution is directly coated on a wafer without an ACF formation process on the releasing film and an ACF lamination process on the wafer. The effects of ACA coating process parameters, such as blade gap and temperature, were first investigated for a uniform thickness coating without voids on an Au-bumped wafer. After solvent drying and subsequent singulation of a B-stage ACA-coated wafer, a singulated chip was flip-chip assembled on an organic substrate using a thermo-compression bonding method. The reliabilities of flip-chip assemblies using ACA-WLPs were evaluated in terms of a high temperature/humidity test, thermal cycling test, and pressure cooker test (PCT) and compared with corresponding results of conventional ACF flip-chip assemblies. In the high temperature/humidity reliability test and thermal cycling test, there was no difference in the flip-chip reliabilities between the two types of flip-chip assemblies. Furthermore, the flip-chip assemblies using ACA-WLPs showed better PCT reliability than the conventional ACF flip-chip assemblies.

Dual Grid Array Antennas in a Thin-Profile Package for Flip-Chip Interconnection to Highly Integrated 60-GHz Radios

We examine the current development of highly integrated 60-GHz radios with an interest in antenna-circuit interfaces. We design and analyze grid array antennas with special attention to the differential feeding and the patterned ground plane. More importantly, we integrate two grid array antennas in a package; propose the way of assembling it to the system printed circuit board; and demonstrate a total solution of low cost and thin profile to highly integrated 60-GHz radios. We show that the package in low temperature cofired ceramic (LTCC) technology measures only 13×13×0.575 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> ; can carry a 60-GHz radio die of current and future sizes with flip-chip bonding; and achieves good antenna performance in the 60-GHz band with maximum gain of 13.5 and 14.5 dBi for the single-ended and differential antennas, respectively.

Integration of analytical techniques in stochastic optimization of microsystem reliability

This paper presents an integrative application of several numerical analytical techniques and associated analysis tools for design optimization and damage prediction in electronics packages and microsystems. This design-for-reliability approach is based on four different types of numerical techniques that allow (1) high-fidelity modelling, (2) reduced order modelling, (3) numerical optimization and (4) uncertainty analysis. The capabilities and the characteristics of the methods that underpin these four types of modelling and analysis tools are firstly investigated. The integration of the methods and tools is then examined and a methodology for coupling the tools in an optimization process is proposed. This numerical methodology involves the following steps: (1) Define sampling points for the design of interest by design of experiments (DOE) and calculate the design response at each DOE point using high-fidelity analysis; (2) construct reduced order models (ROM) for fast analysis using the obtained response values at the DOE points; (3) Undertake deterministic optimization in the defined design space by ROM; and (4) Probabilistic optimization by including variation and uncertainty of the design in the optimization task. This approach is suitable to address design-for-reliability requirements at early design stages in a wide range of application areas. The application of this approach is demonstrated in a case for minimizing the thermal fatigue damage of flip-chip solder interconnects. Design modifications show that this approach can provide improved reliability of the package and in the same time satisfy a number of design requirements.

Surface activation-based nanobonding and interconnection at room temperature

Flip chip nanobonding and interconnect system (NBIS) equipment with high precision alignment has been developed based on the surface activated bonding method for high-density interconnection and MEMS packaging. The 3σ alignment accuracy in the IR transmission system was approximately ±0.2 µm. The performance of the NBIS has been preliminarily investigated through bonding between relatively rough surfaces of copper through silicon vias (Cu-TSVs) and gold-stud bumps (Au-SBs), and smooth surfaces of silicon wafers. The Cu-TSVs of 55 µm diameter and the Au-SBs of 35 µm diameter with ∼6–10 nm surface roughness (RMS) were bonded at room temperature after surface activation using an argon fast atom beam (Ar-FAB) under 0.16 N per bump. Silicon wafers of 50 mm diameter with ∼0.2 nm RMS surface roughness were bonded without heating after surface activation. Void-free interfaces both in Cu-TSV/Au-SB and silicon/silicon with bonding strength equivalent to bulk fracture of Au and silicon, respectively, were achieved. A few nm thick amorphous layers were observed across the silicon/silicon interface that was fabricated by the Ar-FAB. This study in the interconnection and bonding facilitates the required three-dimensional integration on the same surface for high-density electronic and biomedical systems.