Flip Chip Interconnection Research Articles

Indium-Based Flip-Chip Interconnection by Electroplating Method for Superconducting Quantum 3D Integration Architecture

Indium-Based Flip-Chip Interconnection by Electroplating Method for Superconducting Quantum 3D Integration Architecture

Reducing non-effective pixel rate and nonuniformity in AlGaN solar-blind UV focal plane detectors by controlled curvature

A 1600 × 1280 small pixel photodetector was successfully fabricated to verify the controlled curvature of the focal plane array improving the non-effective pixel rate and non-uniformity of the detector. The stress strain generated during epitaxial growth was reduced by growing a 2 μm thick AlN stress correction layer on the backside of the AlGaN/sapphire system substrate. Compared with the material without an AlN stress correction layer on the backside, material curvature reduced from 7.252 μm to 2.740 μm over a length of 0.5 cm. The non-effective pixel rate and the non-uniformity of a focal plane array have been reduced. A process was proposed to reduce the impact of misalignment generated by the flip-chip interconnection process. A solar-blind UV focal plane array was hybridized with a readout integrated circuit using an unsymmetrical flip-chip interconnection process. There is no significant change in peak spectral response, nonuniformity, non-effective pixel rate, or responsivity.

A Foil Flip-Chip Interconnect With an Ultra-Broadband Bandwidth of 130 GHz and Beyond for Heterogeneous High-End System Designs

A Foil Flip-Chip Interconnect With an Ultra-Broadband Bandwidth of 130 GHz and Beyond for Heterogeneous High-End System Designs

Influence of bismuth addition on the physical and mechanical properties of low silver/lead-free Sn-Ag-Cu solder

The Sn–Ag–Cu (SAC) solders with low Ag content have been identified as promising candidates to replace the traditional Sn–Pb solder for flip-chip interconnects. This study examines the impact of incorporating Bi element on the microstructure, thermal behavior, and mechanical performance of low-silver-content Sn-1.5Ag-0.7Cu (SAC157) solder alloy. Besides using the conventional cross-sectioned microstructure image, X-ray diffraction (XRD), differential scanning calorimetry (DSC) and tensile stress- strain techniques were used to investigate the microstructure, thermal and mechanical properties after the addition of Bi, respectively. The results demonstrate that adding of Bi could refine the microstructure, optimize the thermal properties, and improve the tensile strength. Meanwhile, the ductility of the solder alloys reduced evidently in comparison to the Sn-1.5Ag-0.7Cu solder. From the microstructural analysis, 0.5 wt % Bi addition to SAC157 significantly enhanced the solid solution effect of Bi and refined β-Sn dendrite, as well as extended the eutectic area. Moreover, as the Bi addition increases to 5 wt %, finely dispersed bismuth precipitates within the β-Sn matrix, along with an enlarged eutectic area, lead to a remarkable enhancement in both ultimate tensile strength and yield strength. The electrical resistivity was characterized by the four-point probe technique. The results show that the electrical resistivity of Bi-modified SAC157 solder alloy decrease from 13.9 to 9.8 μΩ cm with the addition of 5 wt % Bi. These improvements can be attributed to the solid-solution and precipitation strengthening effects induced by the presence of bismuth. The results confirmed that the developed material is applicable as a potential high strength solder material in the context of advanced interconnecting applications.

Increasing Chip-to-Substrate Spacing Using in Capped SnPb Pillars as Flip Chip Interconnects for Physical Isolation in Superconducting Applications

Increasing Chip-to-Substrate Spacing Using in Capped SnPb Pillars as Flip Chip Interconnects for Physical Isolation in Superconducting Applications

Assembly of Ultra-thin MEMS Device on Driver Chip Using Anisotropic Conductive Film

Assembly solution for large-area, ultra-thin, MEMS-based transducer array dies on driver chips has been investigated using dummy Si dies and substrates. The dummy dies have a thickness of 50 μm, a bonding area on the order of 100 mm2 populated with more than a thousand through-silicon vias connecting corresponding metal pads and redistribution layer (RDL) on both sides. The dummy substrates have conventional thickness as well as necessary RDL and pads for bonding and monitoring electrical resistance and stray capacitance of interconnects. Flip-chip interconnection technology based on anisotropic conductive film (ACF) was selected for bonding and characterization. Handling and ACF bonding of ultra-thin dies to rigid substrates were eased by means of glass carriers attached to the inactive side of the dies. Proper bonding parameters were identified, providing sufficiently low interconnect resistance with satisfactory yield. Stray capacitance of interconnects was found in acceptable range, though lower stray capacitance should be further pursued. The results from this work have demonstrated the feasibility of using ACF for assembling large-area, ultra-thin dies on rigid substrates.

Development and Characterizations of Fine Pitch Flip-Chip Interconnection Using Silver Sintering

Flip-chip interconnects made of silver are promising candidates to overcome the intrinsic limits of solderbased interconnects and match the demand for increased current densities of high-performance microprocessors. Dipbased interconnects have been demonstrated to be a promising approach to form electrical interconnects by sintering paste between copper pillars and pads. However, the quality of the process is limited by residual porosity and poor performances of the sintered joint formed between the pillar and the pad during sintering if a pressure > 50 MPa is not applied in order to decrease the final porosity. In this study, development has been focused on varying key dipping process parameters allowing a pressureless sintering process. Dip-transfer process was optimized on test vehicle and has shown electrical continuity over 700 interconnections with diameter down to 50 μm. We demonstrate high reliability of the process with microstructural observations, tomography X and thermal cycle up to 200 cycles without breakdown.

Flip-Chip Interconnects Based on Single Metal-Coated Polymer Spheres

In microelectronics packaging, minimizing thermomechanical stresses is crucial to achieve high reliability. This paper presents a novel approach for flip-chip interconnects, utilizing individual metal-coated polymer spheres at a low bonding temperature. The method involves selectively depositing individual conductive particles onto a polydimethylsiloxane (PDMS) carrier and then transferring the particles to electrical pads on substrate using Ag sintering followed by die placement and introducing underfill material. The deposition process achieved a high yield of 98.8% on the PDMS carrier, while the transferring process resulted in well-defined ink dots with a yield of 96.2%. The sintered Ag formed good bonds between the particles and electrical pads, leading to moderate interconnect resistance (as low as 0.57 Ω). This work has demonstrated the feasibility of interconnects based on a single metal-coated polymer sphere with low thermomechanical stress induced, thanks to the low bonding temperature (140 °C) and pressure (0.1 MPa) as well as the mechanical compliance of polymer particles.

Cryogenic flip-chip interconnection for silicon qubit devices

Interfacing qubits with peripheral control circuitry poses one of the major common challenges toward realization of large-scale quantum computation. Spin qubits in silicon quantum dots (QDs)are particularly promising for scaling up, owing to the potential benefits from the know-how of the semiconductor industry. In this paper, we focus on the interposer technique as one of the potential solutions for the quantum–classical interface problem and report DC and RF characterization of a silicon QD device mounted on an interposer. We demonstrate flip-chip interconnection with the qubit device down to 4.2 K by observing Coulomb diamonds. We furthermore propose and demonstrate a laser-cut technique to disconnect peripheral circuits no longer in need. These results may pave the way toward system-on-a-chip quantum–classical integration for future quantum processors.

Study on the reliability of nano-silver-coated tin solder joints for flip chips

Abstract The nano-silver-coated tin (Sn@Ag) paste was modeled using the method of the Anand unified viscoplastic constitutive model and elastic model. After thermal cyclic loading, the plastic strain of the solder joints increased cumulatively, while the maximum equivalent stress remained basically stable. The simulation results show that the maximum displacement occurs at the solder joint at the farthest end from the center of the chip, which is a dangerous solder joint. Using the finite element method and EPRI (the American Electric Power Research Institute) estimation method, the fatigue life of the nano-silver-coated tin solder joint is predicted to be 616 weeks, which is significantly higher than that of the nano-silver solder joint. It is indicated that adding a certain amount of nano-tin to the nano-silver paste to form a core–shell structure can improve the shear strength of the solder joint and reduce the plastic strain, thereby significantly improving the reliability of the solder joint. It is proved by experiments that the nano-silver paste is feasible for flip–chip interconnection. The research on this topic provides experimental reference and theoretical basis for the application of a new generation of interconnection materials in power devices and promotes the development and application of microelectronic packaging technology.

Microstructural and micromechanical characterization of sintered nano-copper bump for flip-chip heterogeneous integration

Copper nanoparticles (CuNPs) sintering for flip-chip interconnects is a promising solution for 3D and heterogeneous integration to overcome the limitation of solder materials. To this end, we perform the photolithographic stencil printing method to pattern CuNPs, and the form of flip-chip interconnects is completed after CuNPs sintering process. This paper aims to study the effect of sintering processing parameters (time, pressure, temperature) on the mechanical properties of CuNPs bumps when applying the novel method to approach the Cu interconnects. We fabricated seven groups of specimens of sintered CuNPs bumps, built with a diameter of 100 μm and sintered. The nanoindentation tests assessed the mechanical property to get Young's modulus and hardness. Results clarify that Young's modulus is strongly affected by pressure. An suggested combination of parameters (the 25 MPa and 260 °C for 15 min) give the highest modulus of 126 GPa and the hardness of 1.76 GPa. Moreover, the observations by scanning electron microscopy (SEM) reveal the microstructure and porosity evolution versus different processing parameters.

Electromigration-induced microstructure evolution and failure mechanism of sintered nano-Ag joint

Nanosized silver (nano-Ag) has been proposed as a flip-chip interconnection material owing to its low sintering temperature and impressive working performance. With ever-shrinking size of electronic devices, electromigration (EM) becomes an important reliability issue. However, the EM behavior of nano-Ag joints has rarely been investigated before. In this study, a flip-chip structured nano-Ag joint was examined at a current density of 1.0 × 104 A/cm2 at 150 °C and its microstructural change at different experimental times was analyzed. Severe delamination between the Cu substrate and sintered Ag occurred at the cathode, and the extent of delamination increased with increasing EM time. Fractured surfaces revealed the presence of a large number of whiskers on the opposite side of the cathode owing to stress release during the EM process. For comparison, a Sn-3Ag-0.5Cu solder joint was examined under identical experimental conditions. Although failure in both samples originated from the cathode, the failure mechanism was different. The root cause for the difference in the EM phenomenon observed in the two types of materials was determined in this study.

Golden Bump Based Flip-Chip Interconnection for Superconducting Multi-Chip Module

This paper introduces the preparation of golden bumps on the single flux quantum (SFQ) circuit chip by using the 20-μm-diameter golden wire and the flip-chip (FC) bonding of the SFQ chip and the substrate by the ultrasonic bonding method. Firstly, a coplanar waveguide (CPW) flip-chip interconnect structure was designed and fabricated, and the low-temperature transmission performance i.e., S-parameters were tested. The results showed that <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">S₁₁</i> ≤ -10 dB and <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">S₂₁</i> ≥ -3 dB among the range from 100MHz to 52 GHz at 4.2 K. And the golden bump can transmit PRBSs of 5 Gbps, and its bit error rate (BER) is less than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-12</sup> . Secondly, the flip-chip bonded SFQ driver& receiver circuits with 4.7-Ohm impedance were prepared and the BER of the SFQ pulse signals were measured by the driver& receiver circuits. The test results showed a zero-bit error rate when the number of transmitted codes is in the order of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sup> . The experimental results show that the golden bump based flip-chip interconnection has good high-frequency transmission performance, and can be used for high-bandwidth and narrow pulse signal transmission in superconducting multi-chip modules (MCMs).

224-Gbit/S 4-PAM Operation of Compact DC Block Circuit Integrated Hi-FIT AXEL Transmitter With Low Power Consumption

We previously developed a semiconductor optical amplifier (SOA) assisted extended reach electroabsorption modulator integrated distributed feedback (EADFB) laser (AXEL) to increase the optical modulation output power and a high-frequency integrated design based on the flip-chip interconnection technique (Hi-FIT) to obtain a high modulation bandwidth. We achieved a high-output power 224-Gbit/s 4-level pulse-amplitude-modulation (4-PAM) operation of a Hi-FIT AXEL module. In this paper, we developed a compact DC block circuit integrated into Hi-FIT AXEL module to decrease chip-power consumption without increasing the sub-assembly size and degrading the modulation bandwidth. We designed a Hi-FIT AXEL sub-assembly, that include a flip-chip interconnection board with a DC block circuit that affects the modulation bandwidth. We achieved a 3-dB bandwidth of up to 64 GHz for this designed sub-assembly. The fabricated Hi-FIT AXEL module has a 3-dB bandwidth of more than 62 GHz and a flat frequency response up to 50 GHz. For the 224-Gbit/s 4-PAM operation, the fabricated Hi-FIT AXEL module has a chip-out average output power of +10.0 dBm with a transmitter eye-closure quaternary (TECQ) of 1.9 dB. The integrated compact DC block circuit can reduce chip power consumption by up to 17%.

Cost-Effective Surface-Mount Magnetoelectric Dipole Antenna Based on Ball Grid Array Packaging Technology for 5G Millimeter-Wave New Radio Band Applications

This article presents a cost-effective miniature surface-mount magnetoelectric (ME) dipole antenna. The antenna is realized by a single-layer FR4 substrate and combined with ball grid array (BGA) packaging technology to achieve miniaturization in size. Due to BGA packaging technology, the surface-mount capability allows interconnection between the proposed antenna and other surface-mount devices using a flip-chip interconnect technology, replacing bulky connectors. The proposed antenna element is very compact. Specifically, the electric dipole of the proposed antenna consists of four patches, whereas the magnetic dipole consists of two rows of plated through-holes and a metal ground between them. In addition, the electric and magnetic dipoles are simultaneously excited by an L-shaped metal probe. The prototype has been manufactured and carefully verified. Experimental results show that the proposed antenna element has a −10-dB bandwidth of 23% in the range of 25–31.5 GHz and achieves a peak realized gain of 6.98 dBi at 26 GHz. The dimensions of the proposed antenna element are only 5 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> 5 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times1.8$ </tex-math></inline-formula> mm. The proposed antenna elements can be widely used in the 5G millimeter-wave N257 (26.5–29.5 GHz) and N261 (27.5–28.35 GHz) bands.

Accelerated Solder Interconnect Testing Under Electromigratory and Mechanical Strain Conditions

Abstract Continuous power density increases and interconnect scaling in electronic packages raises risk of electromigration (EM) induced failures in high current interconnects. Concurrently, thermal cycling fatigue also places interconnects at risk of reliability failure during electronics' operating lifetime. These two differing failure mechanisms are historically treated separately, but in operation, the combination of EM effects and thermal cycling can act synchronously in accelerating failure. Presently, there is no model to predict the complexity of reliability estimation arising from these interacting failure modes but is certainly important for high current density applications. In this work, a novel testing system has been employed to facilitate the estimation of the reliability of solder interconnects under the combined influence of EM and mechanical strain. The system subjects solder interconnects to high current density, elevated ambient temperature, and a constant tensile stress while recording the change in electrical resistance and change in length of the solder over time. The solder samples were created using two copper wires connected by a eutectic Pb/Sn solder ball to imitate flip-chip or BGA packaging interconnects, allowing for controlled testing conditions in order to demonstrate the combined effects of a mechanical load and EM on the lifetime of a solder joint. A significant reduction in lifetime was observed for samples that endured the coupled accelerating factors. Comparing the experimental results of different current densities at different stress levels provided a new outlook on the nature of coupled failure acceleration in solders. This novel test methodology can inform model generation for better anticipating the failure rate of solder interconnects which naturally experience multiple stress inputs during their lifetime.

224-Gbit/s 4-PAM operation of a high-modulation-bandwidth high-output-power Hi-FIT AXEL transmitter.

We fabricated an optical transmitter with high frequency and integrated design based on the flip-chip interconnection technique (Hi-FIT) and assisted extended reach electroadsorption modulator integrated distributed feedback (EADFB) laser (AXEL) for 200-Gbit/s/λ application. The Hi-FIT makes it possible to increase modulation bandwidth thanks to wire-free interconnection and peaking control techniques while the AXEL can increase the optical modulation output power thanks to an integrated semiconductor optical amplifier (SOA). The fabricated Hi-FIT AXEL transmitter has a 3-dB bandwidth of more than 66 GHz. We obtained clear 224-Gbit/s 4-level pulse amplitude modulation (4-PAM) eye diagrams with a chip-output optical modulation amplitude (OMA) of more than +7.9 dBm at distributed feedback (DFB) laser and SOA currents of 70 and 30 mA, respectively.

A High Temperature SOI-CMOS Chipset Focusing Sensor Electronics for Operating Temperatures up to 300°C

Abstract Sensors are the key elements for capturing environmental properties and are increasingly important in the industry for the intelligent control of industrial processes. While in many everyday objects highly integrated sensor systems are already state of the art, the situation in an industrial environment is clearly different. Frequently, the use of sensor systems is impossible, because the extreme ambient conditions of industrial processes like high operating temperatures or strong mechanical load do not allow the reliable operation of sensitive electronic components. Fraunhofer is running the Lighthouse Project “eHarsh” to overcome this hurdle. In the course of the project, an integrated sensor readout electronic has been realized based on a set of three chips. A dedicated sensor fron-tend provides the analog sensor interface for resistive sensors typically arranged in a Wheatstone configuration. Furthermore, the chipset includes a 32-bit microcontroller for signal conditioning and sensor control. Finally, it comprises an interface chip including a bus transceiver and voltage regulators. The chipset has been realized in a high-temperature 0.35-micron SOI-CMOS technology focusing operating temperatures up to 300°C. The chipset is assembled on a multilayer ceramic low-temperature cofired ceramics (LTCC) board using flip chip technology. The ceramic board consists of four layers with a total thickness of approximately 0.9 mm. The internal wiring is based on silver paste while the external contacts were alternatively manufactured in silver (sintering/soldering) or in gold alloys (wire bonding). As an interconnection technology, silver sintering has been applied. It has already been shown that a significant increase in lifetime can be reached by using silver sintering for die attach applications. Using silver sintering for flip chip technology is a new and challenging approach. By adjusting the process parameter geared to the chipset design and the design of the ceramic board high-quality flip chip interconnects can be generated.

A High Temperature SOI-CMOS Chipset Focusing Sensor Electronics for Operating Temperatures up to 300 °C

Abstract Sensors are key elements for capturing environmental properties and are increasingly important in the industry for the intelligent control of industrial processes. While in many everyday objects highly integrated sensor systems are already state of the art, the situation in an industrial environment is clearly different. Frequently the use of sensor systems is impossible, because the extreme ambient conditions of industrial processes like high operating temperatures or strong mechanical load do not allow a reliable operation of sensitive electronic components. Fraunhofer is running the Lighthouse Project ‘eHarsh’ to overcome this hurdle. In the course of the project an integrated sensor readout electronic has been realized based on a set of three chips. A dedicated sensor frontend provides the analog sensor interface for resistive sensors typically arranged in a Wheatstone configuration. Furthermore, the chipset includes a 32-bit microcontroller for signal conditioning and sensor control. Finally, it comprises an interface chip including a bus transceiver and voltage regulators. The chipset has been realized in a high temperature 0.35 micron SOI-CMOS technology focusing operating temperatures up to 300 °C. The chipset is assembled on a multilayer ceramic LTCC-board using flip chip technology. The ceramic board consists of 4 layers with a total thickness of approx. 0.9 mm. The internal wiring is based on silver paste while external contacts were alternatively manufactured in silver (sintering/soldering) or in gold-alloys (wire bonding). As interconnection technology, silver sintering has been applied. It has already been shown that a significant increase in lifetime can be reached by using silver sintering for die attach applications. Using silver sintering for flip chip technology is a new and challenging approach. By adjusting the process parameter geared to the chipset design and the design of the ceramic board high quality flip chip interconnects can be generated.

The dark current suppression of black silicon photodetector by a lateral heterojunction

Femtosecond laser hyperdoped silicon, known commonly as black silicon (b-Si), has attracted substantial interest from various fields due to its high absorptance and responsivity ranging from visible to near-infrared wavelengths. However, due to the non-uniformity of b-Si layer and the lattice defects present in it, the processing technique used presently introduces high noise in devices manufactured using b-Si. In this study, a lateral heterojunction is designed and manufactured at the b-Si and silicon interface to restrain the leakage current. Precisely, the lateral structure could support the b-Si photodetector in suppressing the dark current to 783 nA at a bias of -5 V, quite low in terms of orders of magnitude compared to that for the vertical ones. Simultaneously, the photo-to-dark current ratio of 155 is obtained at the same bias voltage with a pertinent external quantum efficiency (EQE) of 371%. Riding on the advantages of low noise, high signal-to-noise ratio, and high sensitivity, this work shows promising prospects for the application of b-Si-based photodetectors toward large-scale integration in optical-electronics or flip-chip interconnection systems. • The dark current of b-Si photodetector is suppressed by a lateral heterojunction. • The detector exhibits a high photo-to-dark current ratio at reverse bias voltage. • The photoconductive gain is achieved for a wide coverage of wavelength.