Flip Chip Interconnection Research Articles

Flip-Chip Interconnect for Coplanar Strip Lines

A flip-chip interconnect configuration with coplanar strip (CPS) lines on printed circuit boards (PCBs) is reported for millimeter-wave applications. For CPS lines, the signal and ground electrodes both lie on the top surface of a chip or substrate. The flip-chip configuration was designed and implemented using a test chip on a dielectric board. Geometrical parameter analysis was carried out using full-wave simulation and equivalent circuit model for wideband performance. The chip was connected to the board using solder bumps. For a typical flip-chip assembly, the measured insertion loss is less than 3dB for frequencies of up to 35GHz and the return loss is higher than 15dB for frequencies of up to 29GHz using CPS flip-chip configuration.

Integrated Process-Aging Modeling Methodology for Flip Chip on Flex Interconnections With Nonconductive Adhesives

This paper presents a comprehensive methodology to model the static temperature-humidity (TH) aging test ( 85 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">deg</sup> C/85%RH over 1000 h) of flip chip on flex interconnections with nonconductive adhesives (NCAs). NCAs, being a special form of conductive adhesives, are chosen, as they allow bringing the pitch further down. The methodology combines experimental techniques for material characterization, finite element modeling (FEM), and model validation. A NCA has been characterized using several techniques. The thermomechanical properties and the moisture absorption properties were obtained for the NCA. A temperature dependent viscoelastic constitutive model was also obtained for the NCA. The viscoelastic model was defined by the Prony series expansion. The shift factor was approximated by the Williams-Landel-Ferry (WLF) equation. Finite element modeling has been performed to analyze the flip chip interconnects on flex with the NCA under process condition and reliability aging conditions. The viscoelastic constitutive relation has been used to model the NCA in aging modeling. An integrated process-aging modeling methodology has been developed to combine the thermo-mechanical stress and hygro-mechanical stress, followed by stress relaxation analysis. To verify the finite element models, static TH aging tests (85 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">deg</sup> C/85%RH) were also performed. The contact resistance was monitored with high measuring resolution during the accelerated test. The simulation results are in good agreement with the experimental results. The approach developed in this paper can be used to provide guidelines with respect to adhesive material properties, assembly process parameters to achieve good reliability performance.

Transmission property of flip chip package with adhesive interconnection for RF applications

The radio frequency (RF) and high frequency performance of the flip chip interconnects with anisotropic conductive film (ACF) and non-conductive film (NCF) was investigated and compared by measuring the scattering parameters (S-parameters) of the flip chip modules. Low cost electroless-Ni immersion-Au (ENIG) plating was employed to form the bumps for the adhesive bonding. To compare the accurate intrinsic RF performance of the ACF and NCF interconnect without lossy effect of chip and substrate, a de-embedding modeling algorithm was employed. The effects of two chip materials (Si and GaAs), the height of ENIG bumps, and the metal pattern gap between the signal line and ground plane in the coplanar waveguide (CPW) on the RF performance of the flip chip module were also investigated. The transmission properties of the GaAs were markedly improved on those of the Si chip, which was not suitable for the measurement of the S-parameters of the flip chip interconnect. Extracted impedance parameters showed that the RF performance of the flip chip interconnect with NCF was slightly better than that of the interconnect with ACF, mainly due to the capacitive component between the bump and substrate and self inductance of the conductive particle surface in the ACF interconnect.

Numerical Investigation of Underfill Failure Due to Phase Change of Pb-Free Flip Chip Solders During Board-Level Reflow

In this paper, the effects of phase change of Pb-free flip chip solders during board-level interconnect reflow are investigated using numerical technique. Most of the current Pb-free solder candidates are based on Sn and their melting temperatures are in the range of 220 deg C-240 deg C. Thus, Pb-free flip chip solders melt again during subsequent board-level interconnect (BGA) reflow cycle. Since solder volume expands as much as 4% during the phase change from solid to liquid, the volumetric expansion of solder in a predefined volume by chip, substrate, and underfill creates serious reliability issues. One issue is the shorting between neighboring flip chip interconnects by the interjected solder through underfill crack or delaminated interfaces. The authors have observed the interjection of molten solder and the interfacial failure of underfill during solder reflow process. In this paper, a flip chip package is modeled to quantify the effect of the volumetric expansion of Pb-free solder. Three possible cases are investigated. One is without existence of micro crack and the other two are with the interfacial crack between chip and underfill and the crack through the underfill. The strain energy release rate around the crack tip calculated by the modified crack closure integral method is compared with interfacial fracture toughness. Parametric studies are carried out by changing material properties of underfill and interconnect pitch. Also, the effects of solder interconnect geometry and crack length are explored. For the case with interfacial crack, the configuration of a large bulge with small pitch is preferred for the board-level interconnect, whereas a large pitch is preferred for cracks in the mid plane of the underfill.

Application of interfacial fracture mechanics approach for obtaining design rules for flip chip interconnections

The reliability of an electronic package can be described by a physics-of-failure approach. Crack initiation and propagation in the bulk material and interface leads to catastrophic mechanical and finally to electrical failure. Therefore, bulk and interfacial fracture mechanics is a suitable method to describe the reliability of an electronic package. As package, a stud bump bonding flip chip interconnection on a thermoplastic substrate material [liquid crystal polymer (LCP)] is studied. The paper focuses on the description of the interfacial cracking between the underfill and the LCP. This is used to obtain design rules for flip chip interconnection on LCP by means of finite element analysis. Geometry design parameters—fillet shape, chip and substrate sizes—are studied. Moreover, the influence of material properties of the substrate and underfill are investigated. The impacts of the parameters are evaluated by analyzing the energy release rate (ERR) and mode-mixity in the interface. For determination of the critical ERR as function of the mode-mixity, a modified button shear test is utilized. The button, made out of underfill, is cured on the LCP substrate. A pre-delamination is established using a Teflon strip. The critical ERR for different mode-mixities is obtained by varying the shearing height of the button test. Additional, the influence of oxygen plasma treatment of the LCP substrate on the interfacial cracking is taken into account. In the investigation, design rules for increasing the reliability of flip chip interconnections are obtained. Moreover, a modified button-test is applied to obtain critical energy releases rates for different mode-mixities for the interface underfill/LCP. These results are used to optimize the geometry and materials of flip chip interconnections for automotive sensor applications in respect to delamination risk between substrate and underfill.

Packaging and Assembly of 3-D Silicon Stacked Module for Image Sensor Application

This paper is for process development of assembly technologies used to fabricate the 3-D silicon carrier system-in-package (SiP). The five assembly technologies are wafer thinning, thin flip chip attach on silicon carrier, ultra low loop wire bonding, glass cap fabrication and sealing, and silicon carrier stacking. The developed SiP has three silicon carriers with four flip chip and one wire bond die chip attached to them and the carrier is stacked one above the other to form the 3-D silicon carrier SiP. Eight-inch bumped wafer thinning down to less than 100 mum, lower flip chip interconnect height between the chip and the carrier down to 35 mum, 40-50- mum low loop wire bonding on overhang by direct reverse wire bonding method using 1- mil-di- ameter Au wire are achieved. And investigation of three types of thin film metallization systems for wirebonding and investigation of two different methods in fabricating glass cap are also studied.

A V-Band Beam-Steering Antenna on a Thin-Film Substrate With a Flip-Chip Interconnection

We propose a planar V-band beam-steering antenna based on a millimeter-wave (mm-wave) system-on-package technology using advanced thin-film technology on a silicon mother board. The thin-film substrate has the capability of integrated passive elements and flip-chip interconnection. Space-consuming components such as a microstrip Rotman lens and patch antennas are implemented on a low-loss, low-cost, and low-dielectric-constant material, benzocyclobutane. V-band monolithic microwave integrated circuits, a power amplifier, and a SP4T switch, are flip-chipped on the thin-film substrate while minimizing parasitic effects. The fabricated antenna module shows if-plane beam steering at four angles, plusmn6deg and plusmn20deg. The measured effective isotropic radiated power is in the range of 17.3-18 dBm. To our knowledge, this is the first demonstration of a planar mm-wave beam-steering antenna module on a thin-film substrate incorporating integrated terminating loads and flip-chip interconnections.

Electrical characterization of adhesive flip chip interconnects for microwave application

Microwave performance of the anisotropic conductive film (ACF) and nonconductive film (NCF) interconnects was investigated by measuring the scattering parameters (S-parameters) of the flip chip modules employing the films. To compare the accurate intrinsic microwave performance of the ACF and NCF interconnects without lossy effect of chip and substrate, a de-embedding technique was employed. The effects of two chip materials, Si and quartz (SiO2), and of the metal pattern gap between the signal line and ground plane in the coplanar waveguide (CPW) on the microwave performance of the flip chip module were also investigated. The transmission properties of the quartz were markedly improved over those of the Si chip, which was not suitable for the measurement of the S-parameters of the flip chip interconnect. Extracted impedance parameters showed that the microwave performance of the flip chip interconnect with NCF was slightly better than that of the interconnect with ACF, mainly due to the inductive effect of the conductive particle surface and capacitance of the epoxy matrix in the ACF interconnect.

Novel Techniques for Characterization of Fast-Cure Anisotropic Conductive and Non-conductive Adhesives

Anisotropic conductive adhesives (ACAs) and non-conductive adhesives (NCAs) are widely used in adhesive flip chip technology. Typically, ACAs and NCAs are formulated to achieve a complete cure in less than 60 s when curing between 180 and 250°C. The fast-cure characteristic of these adhesives poses great difficulties for conventional cure characterization techniques. In this study, novel cure monitoring techniques including Modulated Differential Scanning Calorimetry (MDSC), Dielectric Analysis (DEA) and Fibre Bragg Grating (FBG) techniques were evaluated. Cure-related properties in terms of adhesion strength and cure shrinkage were characterized. Findings showed that MDSC is an improved method for analyzing partial-cured samples compared to conventional Differential Scanning Calorimetry (DSC). It was also demonstrated that cure monitoring of these fast-cure materials was feasible using both DEA and FBG techniques. Adhesion study showed good correlation of adhesion strength and failure modes with degree of cure. Failure mode changes from mixed to cohesive mode at 50% degree of cure. Above 90% degree of cure, adhesion strength was found to surpass the shear strength of silicon substrate. These results clearly emphasize the importance of cure optimization to attain sufficient adhesion strength of these adhesives. For cure shrinkage measurement, feasibility of both FBG and Thermomechanical Analysis (TMA) techniques was demonstrated. In summary, this study has demonstrated the applicability of several techniques for cure behaviour characterization of fast-cure ACA and NCA materials. Key findings from this work represent a significant step towards cure process optimization for the development of reliable adhesives for flip chip interconnects.

Microwave Performance of Flip Chip Interconnects With Anisotropic and Non-conductive Films

Anisotropic conductive films (ACFs) and non-conductive films (NCFs) are film-type, adhesive polymer resins that have been used in flat panel display modules to provide high-resolution, light weight, thin profile and environmental friendliness. We investigated the radiofrequency (RF) and high frequency performance of the flip chip interconnects with ACF and NCF by measuring the scattering parameters (S-parameters) of the flip chip modules. The effects of three chip materials, Si, quartz and gallium arsenide (GaAs), and the metal pattern gap between the signal line and ground plane in the coplanar waveguide (CPW) on the RF performance of the flip chip were also investigated. The transmission properties of the GaAs and quartz chips were markedly improved over those of the Si chip, which was not suitable for the measurement of the S-parameters of the flip chip interconnect. The RF performance of the flip chip module with NCF was slightly better than that of the module with ACF, mainly due to the capacitance of the epoxy resin between the Au bump and pad and the self-inductance of the conductive particle surface in the ACF interconnect.

Secondary Current Crowding Effect during Electromigration of Flip-Chip Solder Joints

In flip-chip interconnects under current stressing, the primary current crowding effect occurs at the entrance edge of the contact interface with the highest current density. In this study, an increased current density also occurred at the other edge of the contact interface, followed by a selective dissolution of under bump metallization. After primary current crowding, the rest of electrons flow to the metallization edge, followed by an abrupt change in direction toward the anode. Primary current crowding is attributed to the electrical field change whereas the secondary crowding effect is due to the physical blocking of the electron flow. Because this effect is not as great as that of primary current crowding, it must be assisted by thermal diffusion.

60 GHz Broadband MS-to-CPW Hot-Via Flip Chip Interconnects

In this letter, the microstrip-to-coplanar waveguide (MS-to-CPW) hot-via flip chip interconnect has been experimentally demonstrated to have broadband performance from dc to 67 GHz. The interconnect structures with the hot-via transitions were first designed and optimized by using the electromagnetic simulation tool. Three types of designs were investigated in this letter. The interconnect structures were then fabricated and radio frequency (RF) tested up to 67GHz. The optimized interconnect structure with the compensation design demonstrated excellent RF characteristics with the insertion loss less than 0.5dB and the return loss below 18dB over a very broad bandwidth from dc to 67GHz. This is to our knowledge the best result reported for this frequency range.

Reliability Assessment of Advanced Flip-Chip Interconnect Electronic Package Assemblies under Extreme Cold Temperatures (−190 and −120°C)

Flip-chip interconnect electronic package boards have been assembled, underfilled, non-destructively evaluated, and subsequently subjected to extreme temperature thermal cycling to assess the reliability of this advanced packaging interconnect technology for future deep-space, long-term, extreme temperature missions. In this very preliminary study, the employed temperature range covers military specifications (−55 to 100°C), extreme cold Martian (−120 to 115°C) and asteroid Nereus (−180 to 25°C) environments. The resistance of daisy-chained, flip-chip interconnects was measured at room temperature and at various intervals as a function of extreme temperature thermal cycling. Electrical resistance measurements are reported and the tests to date have not shown significant change in resistance as a function of extreme temperature thermal cycling. However, the change in interconnect resistance becomes more noticeable with increasing number of thermal cycles. Further research work has been carried out to understand the reliability of flip-chip interconnect packages under extreme temperature applications (−190 to 85°C) via continuously monitoring the daisy chain resistance. Adaptation of suitable diagnostic techniques to identify the failure mechanisms is in progress. This paper will describe the experimental test results of flip-chip testing under extreme temperatures.

Evolution of Contact Resistance during the Bonding Process of NCA Flip-Chip Interconnections

Non-conductive adhesive (NCA) flip-chip interconnects are emerging as an attractive alternative to lead or lead-free solder interconnects due to their environmental friendliness, lower processing temperatures, and extendability to fine-pitch applications. The electrical connectivity of an NCA interconnect relies solely on the pure mechanical contact between the integrated circuit (IC) bump and the substrate pad; the electrical conductivity of the contact depends on the mechanical contact pressure, which in turns depends to a large extent on the cure shrinkage characteristics of the NCA. Therefore, it is necessary to monitor the evolution of the electrical conductivity which could reflect the impact of cure- and thermal-induced stresses during the curing and cooling process, respectively. In this article, in situ measurement of the development of contact resistance during the bonding process of test chips was developed by using a mechanical tester combined with a four-wire resistance measurement system. A drop of resistance induced by the cure stress during the bonding process is clearly observed. With decreasing bonding temperature, the drop of contact resistance induced by cure shrinkage becomes larger, while the cooling-induced drop of resistance becomes smaller. The evolution of contact resistance agrees well with experimental observations of cure stress build-up. It is found that vitrification transformation during the curing of the adhesive could lead to a large cure stress and result in the reduction of the contact resistance. Furthermore, no obvious changes were observed when the applied load was removed at the end of bonding.

Effects of the Functional Groups of Nonconductive Films (NCFs) on Material Properties and Reliability of NCF Flip-Chip-On-Organic Boards

Nonconductive films (NCFs) are one of the polymer interconnect materials for flip-chip interconnection. NCFs containing no conductive particles play several roles such as adhesion, insulation, and underfilling at the same time. The most important issue of NCF flip-chip-on-board (FCOB) assemblies is thermal cycling reliability. Thermomechanical properties of cured NCFs, such as glass transition temperature (T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> ), storage modulus (E'), and coefficient of thermal expansion (CTE), significantly affect the thermal cycling reliability of NCF FCOB assemblies. In this paper, the improvement of thermomechanical properties of NCFs was investigated by controlling the number of functional groups of NCF resins. To compare the reliability of conventional and modified NCF FCOB assemblies after thermal cycling test, electrical analysis and scanning acoustic microscopy investigation were performed. Thermal deformations of NCF FCOB assemblies under thermal cycling environment were also investigated, and quantitatively compared using high sensitivity Twyman-Green interferometry and portable engineering Moire interferometry. According to these results, the functional groups of NCFs have significant effects on thermomechanical properties of cured NCFs, thermal deformation, and thermal cycling reliability of NCF-bonded FCOB assemblies. As a result, the functionality modified NCF FCOB assemblies showed significantly enhanced reliability compared conventional NCFs in thermal cycling test.

Effects of bonding temperature on the properties and reliabilities of anisotropic conductive films (ACFs) for flip chip on organic substrate application

The effects of bonding temperatures on the composite properties and reliability performances of anisotropic conductive films (ACFs) for flip chip on organic substrates assemblies were studied. As the bonding temperature decreased, the composite properties of ACF, such as water absorption, glass transition temperature ( T g), elastic modulus ( E′) and coefficient of thermal expansion ( α), were improved. These results were due to the difference in network structures of cured ACFs which were fully cured at different temperatures. From small angle X-ray scattering (SAXS) test result, ACFs cured at lower temperature, had denser network structures. The reliability performances of flip chip on organic substrate assemblies using ACFs were also investigated as a function of bonding temperatures. The results in thermal cycling test (−55 °C/+150 °C, 1000 cycles) and PCT (121 °C, 100% RH, 96 h) showed that the lower bonding temperature resulted in better reliability of the flip chip interconnects using ACFs. Therefore, the composite properties of cured ACF and reliability of flip chip on organic substrate assemblies using ACFs were strongly affected by the bonding temperature.

Assembly of Copper Column Interconnect Flip Chip

This paper addresses a new flip chip interconnection technology, flexible flip chip connection (F2C2) technology, for attaching silicon chips to a chip carrier using flexible copper wires. F2C2 is a novel approach to create area array flip chip interconnections using a matrix block of wires encapsulated with a heat-resistant, dissolvable substance. A slice from the wire matrix ingot is first attached to the chip using solder. The other end of the slice is then matched and soldered to the footprint of a substrate. Finally, the encapsulating, dissolvable substance is removed from the body of the slice, leaving the chip attached to the carrier by the inter- disposed, flexible copper wires. The compliant copper wire interconnections can accommodate the coefficient of thermal expansion (CTE) mismatch problem between die and substrate, thus eliminating the need for underfill.

Role of bonding time and temperature on the physical properties of coupled anisotropic conductive–nonconductive adhesive film for flip chip on glass technology

Using thermosetting epoxy based conductive adhesive films for the flip chip interconnect possess a great deal of attractions to the electronics manufacturing industries due to the ever increasing demands for miniaturized electronic products. Adhesive manufacturers have taken many attempts over the last decade to produce a number of types of adhesives and the coupled anisotropic conductive–nonconductive adhesive film is one of them. The successful formation of the flip chip interconnection using this particular type of adhesive depends on, among factors, how the physical properties of the adhesive changes during the bonding process. Experimental measurements of the temperature in the adhesive have revealed that the temperature becomes very close to the required maximum bonding temperature within the first 1 s of the bonding time. The higher the bonding temperature the faster the ramp up of temperature is. A dynamic mechanical analysis (DMA) has been carried out to investigate the nature of the changes of the physical properties of the coupled anisotropic conductive–nonconductive adhesive film for a range of bonding parameters. Adhesive samples that are pre-cured at 170, 190 and 210 °C for 3, 5 and 10 s have been analyzed using a DMA instrument. The results have revealed that the glass transition temperature of this type of adhesive increases with the increase in the bonding time for the bonding temperatures that have been used in this work. For the curing time of 3 and 5 s, the maximum glass transition temperature increases with the increase in the bonding temperature, but for the curing time of 10 s the maximum glass transition temperature has been observed in the sample which is cured at 190 °C. Based on these results it has been concluded that the optimal bonding temperature and time for this kind of adhesive are 190 °C and 10 s, respectively.

Predictive Model for Optimized Design Parameters in Flip-Chip Packages and Assemblies

An analytical model is developed to predict the out-of- plane deformation and thermal stresses in multilayered thin stacks subjected to temperature. Coefficient of thermal expansion mismatches among the components (chip, substrate, underfill, flip-chip interconnect or C4s) are the driving force for both first and second levels interconnect reliability concerns. Die cracking and underfill delamination are the concerns for the first level interconnects while the ball grid array solder failure is the primary concern for the second level interconnects. Inadvertently, many researchers use the so-called rule of mixture in its effective moduli for the flip chip solder (C4)/underfill layer. In this study, a proper formula for effective moduli of solder (C4)/underfill layer, is presented. The classical lamination theory is used to predict the out-of-plane displacement of the chip substrate structure under temperature variation (DeltaT). The warpage and stresses resulting from the analytical formulation are compared with the 3-D finite element analysis. The study helps to design more reliable components or assemblies with the design parameters being optimized in the early stage of the development using closed form analytical solutions.

Effects of Phase Change of Pb-Free Flip-Chip Solders During Board-Level Interconnect Reflow

The impact of phase change (from solid to liquid) on the reliability of Pb-free flip-chip solders during board-level interconnect reflow is investigated. Most of the current candidates for Pb-free solder are tin-based with similar melting temperatures near 230 degC. Thus, Pb-free flip-chip solders melt again during the subsequent board-level interconnect reflow cycle. Solder volume expands more than 4% during the phase change from solid to liquid. The volumetric expansion of solder in a volume constrained by chip, substrate, and underfill creates serious reliability issues. The issues include underfill fracture and delamination from chip or substrate. Besides decreasing flip-chip interconnect reliability in fatigue, bridging through underfill cracks or delamination between neighboring flip-chip interconnects by the interjected solder leads to failures. In this paper, the volume expansion ratio of tin is experimentally measured, and a Pb-free flip-chip chip-scale package (FC-CSP) is used to observe delamination and solder bridging after solder reflow. It is demonstrated that the presence of molten solder and the interfacial failure of underfill can occur during solder reflow. Accordingly, Pb-free flip-chip packages have an additional reliability issue that has not been a concern for Pb solder packages. To quantify the effect of phase change, a flip-chip chip-scale plastic ball grid array package is modeled for nonlinear finite-element analysis. A unit-cell model is used to quantify the elongation strain of underfill and stresses at the interfaces between underfill and chip or underfill and substrate generated by volume expansion of solder. In addition, the strain energy release rate of interfacial crack between chip and underfill is also calculated