Flip-chip Devices Research Articles

Advanced lithography and electroplating approach to form high-aspect ratio copper pillars

Advanced packaging technologies continue to enable the semiconductor industry to meet the needs for ever thinner, smaller and faster components required in mobile devices and other high performance applications. In the early days of advanced packaging, C4 solder bumps were the alternative to wire bonding. Although lead-free solder remains one of the preferred methods for assembly, tall copper structures (copper pillars) are becoming the standard interconnect solution for many applications. A process of lithography and subsequent electroplating are the mainstream process for today's copper pillar formation on wafer level for high-end flip chip devices. The latest trends in advanced packaging require another technology development when it comes to copper pillars. Modern integration schemes such as 2.5D interposer as well as 3D stacking have pushed the limits of standard lithography and copper electroplating capabilities. Specifically, the need for fine-pitch high aspect ratio copper pillars represents a challenge. In addition, the trend towards rectangular panel-based packaging as seen with glass interposers or panel fan-out (P-FO) devices demands a challenging scale-up of lithography and electroplating equipment and processing capabilities. This work specifically focuses on the formation of high-aspect ratio copper pillars in excess of 100μm by means of stepper-based lithography followed by electroplating. A unique test vehicle has been created to evaluate the process latitude for lithography for different resist materials as well as the specific electroplating challenges associated with these tall and narrow structures. The paper investigates the influence of key parameters such as CD uniformity, pattern density variations and resist profile on the critically important pillar height uniformity across the wafer or panel. In addition, the resist profile behavior at the substrate interface is being examined as it influences undercut behavior during wet etch of the plating seed layer. A number of wet and dry-film resist materials and appropriate lithography processes (spin coat or laminate, expose, develop) followed by copper plating based on varying chemistries and process parameters are being explored. The paper also summarizes the current requirements for the above mentioned lithography and plating processes as seen in the industry today.

Dramatic Enhancement in Photoresponse of β-In2S3 through Suppression of Dark Conductivity by Synthetic Control of Defect-Induced Carrier Compensation.

We report on the synthesis of dense and faceted indium sulfide (β-In2S3) nano-octahedron films on fluorine-doped tin oxide-coated glass by the hydrothermal method and their photoresponse properties in a flip chip device configuration. We have examined the temporal evolution of the phase constitution, morphology, and optoelectronic properties for films obtained after growth interruption at specific intervals. It is noted that, initially, an In(OH)3 film forms, which is gradually transformed to the β-In2S3 phase over time. In the case of the film wherein most, but not all, of In(OH)3 is consumed, an exceptionally large photoresponse (light to dark current ratio) of ∼10(4) and response time(s) (rise/fall) of ∼88/280 ms are realized. This superior performance is attributed to nearly complete carrier compensation achievable in the system under high pressure growth leading to dramatic reduction of dark conductivity. It is argued that the temporally growth-controlled equilibrium between quasi-In interstitials and cation vacancies dictates the optoelectronic properties.

Light-extraction efficiency control in AlGaN-based deep-ultraviolet flip-chip light-emitting diodes: a comparison to InGaN-based visible flip-chip light-emitting diodes.

We study light-extraction efficiency (LEE) of AlGaN-based deep-ultraviolet light-emitting diodes (DUV-LEDs) using flip-chip (FC) devices with varied thickness in remaining sapphire substrate by experimental output power measurement and computational methods using 3-dimensional finite-difference time-domain (3D-FDTD) and Monte Carlo ray-tracing simulations. Light-output power of DUV-FCLEDs compared at a current of 20 mA increases with thicker sapphire, showing higher LEE for an LED with 250-μm-thick sapphire by ~39% than that with 100-μm-thick sapphire. In contrast, LEEs of visible FCLEDs show only marginal improvement with increasing sapphire thickness, that is, ~6% improvement for an LED with 250-μm-thick sapphire. 3D-FDTD simulation reveals a mechanism of enhanced light extraction with various sidewall roughness and thickness in sapphire substrates. Ray tracing simulation examines the light propagation behavior of DUV-FCLED structures. The enhanced output power and higher LEE strongly depends on the sidewall roughness of the sapphire substrate rather than thickness itself. The thickness starts playing a role only when the sapphire sidewalls become rough. The roughened surface of sapphire sidewall during chip-separation process is critical for TM-polarized photons from AlGaN quantum wells to escape in lateral directions before they are absorbed by p-GaN and Au-metal. Furthermore, the ray tracing results show a reasonably good agreement with the experimental result of the LEE.

Visible Light-Emitting Diodes With Thin-Film-Flip- Chip-Based Wafer-Level Chip-Scale Package Technology Using Anisotropic Conductive Film Bonding

Demonstrated is advanced device and packaging architecture of visible GaN-based light-emitting diodes (LEDs) combining thin-film flip-chip devices and wafer-level chip-scale package with through-silicon-via (TSV) and wafer-to-wafer alignment bonding. In addition, a new interconnect technique for LEDs is introduced using an anisotropic conductive film with metal balls. Thermal rollover in light output versus current characteristics is not observed up to 700 mA. A forward voltage at 350 mA is 3.06 V. The architecture can facilitate excellent heat removal through a TSV-formed Si wafer in addition to expected benefits of easy integration of Si-based devices in lighting modules. Light-output power at 350 mA increases by 11.1% compared with that of conventional flip-chip LEDs. A Lambertian-like emission pattern is also achieved.

Impact of Reprocessing Technique on First Level Interconnects of Pb-Free to SnPb Reballed Area Array Flip Chip Devices

The risk of damage caused by reballing SnPb eutectic solder balls onto a commercial off-the-shelf (COTS) active flip chip with a ball grid array (BGA) of SAC305 was studied. The effects of reballing performed by five different reballers were examined and compared. The active flip chip device selected included manufacturer specified resistance between eight (8) differential port pairs. The path resistance between these pins following reballing, as compared to an unreballed device, was used to assess damage accumulation in the package. 2-dimensional x-ray microscopy, acoustic microscopy, and x-ray computer tomography were also used to characterize the effects of reballing. These studies indicated that no measureable damage was incurred by the reballing process, implying that reballed devices should function as well as non-reballed devices in the same application.

Analysis of fatigue delamination growth in flip-chip package

An incremental crack extension procedure is implemented for simulating the growth of an interface defect in an electronic flip-chip device subjected to fatigue temperature cycling. The distributions of fracture mechanics parameters including the strain energy release rate, the stress intensity factors and phase angles along the curvilinear front of an embedded corner defect on the interface of silicon die and underfill are estimated and substituted into a subcritical crack growth model to predict the evolution of the defect under cyclic loading condition. It is observed from the analysis that the corner defect is under crack faces contact condition during temperature cycling, and consequently, the delamination growth is under mode-II and mode-III driving forces. In addition, the crack growth rate is highest in the middle of the crack front, and the corner crack evolves from an initially concave front to a quarter-circular front under temperature cycling.

Role of substrate aspect ratio on the robustness of capillary alignment

Capillary forces associated with liquid bridges formed across solid substrates are routinely exploited to align and assemble micro- and nanoscale devices. The magnitude of these forces plays a critical role in minimizing substrate misalignment and therefore should be controlled for robust and reliable fabrication process. We explore through simulations and experiments the role of the substrate aspect ratio (L/W) on capillary restoring forces and torques. Simulations show that increasing the aspect ratio of the substrates increases the capillary torques and forces when the substrates are misaligned through either lateral or rotational perturbations. The effect of substrate area, perimeter, and liquid volume are also systematically explored to show that the increase in restoring torque is caused by an increase in aspect ratio. A simple theoretical model based on the geometry of the system shows excellent agreement with Surface Evolver simulations. Finally, parameters from experimental flip-chip devices [Josell, D. Wallace, W.E. Warren, J.A. Wheeler, D. Powell, A.C. J. Electron. Packag. 124, 227, (2002)] are used in our simulations to show how current capillary self-alignment schemes could benefit from using rectangular substrate shapes with aspect ratio greater than one.

Numerical analysis of thermo-mechanical and mobility effects for 28 nm node and beyond: Comparison and design consequences over bumping technologies

Thanks to finite elements simulation and dedicated post-processing routines, this paper explores stress induced mobility changes over three major bumping processes. A numerical comparative analysis over the assembly generations is carried out. In order to do so, models are built for solder flip chip, copper pillar flip chip and micro-copper pillar bumping. Design recommendations for MOSFET placement to include in conception tools are provided, which allow to ensure adherence to product specifications while technologies advance.It is demonstrated that stress effects on mobility are widely dependent on the integration flow, and transistor placements must be considered accordingly. Despite the fact that, qualitatively speaking, the generated stress states are quite similar for whole bumping schemes, the quantitative variations of each stress components in combination with the piezo resistive coefficients of silicon lead to distinct effective mobility variations. As a consequence, design rules and keep out zones can be optimized specifically for each assembly technology. More precisely, it is advised to avoid nMOS placement directly below the bump in flip chip devices, for which the mobility can be degraded by almost 5%. In these cases keep out zones must be considered. Reversely, in the case of 3DICs, the performances of nMOS are improved by more than 2% in that region, which means that no restriction is required and silicon area can hence be saved. As for the p type carriers, variability is sensitive to channel orientation rather than their location with respect to the bump: more precisely, the transport direction must be azimuthally oriented, and radially oriented pMOS are proscribed. Maximum variations of about ±5% are found for the copper pillar flip chip configuration. Thanks to a comprehensive analysis, FEoL designers will be able to integrate BEoL and packaging constraints during the conception phases of advanced semiconductor products.

Optimization of the Au Stud Bump Number for the Flip-Chip Packaged InGaN LEDs

Au stud bump can provide a good heat spreading path for the flip-chip LED due to its high thermal conductivity (300 W/mK) . In this paper, we compared four flip-chip LED devices with four different numbers of Au stud bumps. The thermal imaging analysis indicates that the heat dissipation is proportional to the number of Au stud bump. However, when the number of Au stud bumps was larger than 24, the heat dissipation performance will become deteriorated due to the poor bonding between grain and substrate. Therefore, the number of Au stud bumps was optimized to be 20 to 24, which can be employed to develop flip-chip LEDs with optimum electrical and optical performance.

Catastrophic flip-chip failures at thermal cycles caused by micro-cracks in passivation layer, present only in the spacing between minimum width stripes of last metal level

Our case study concerns flip-chip devices, assembled on Printed Circuit Board with direct bumping, failing catastrophically under thermal cycles stress. The failure analysis highlighted a deep crack in silicon, systematically located under a particular bump. We show the path followed to understand failure mechanism by means analyses performed at various back-end process steps, up to wafer inspection. Micro-cracks in passivation layer were found, generated only in the spacing between minimum width stripes of last metal layer. Fixed the multiple passivation layer, necessary to protect the devices up to bumping process manufacturer, layout study and 3D simulator stress evaluation, allowed us to identify the metal stripe width as the “key” factor.The implemented solution was minimum metal 4 stripes widening. The devices with new layout were submitted to thermal cycles stress, resulting in zero failures (up to 500 cycles), versus 30% of failure rate (after 100 cycles) of first layout version.

Molecular Level Understanding of Adhesion Mechanisms at the Epoxy/Polymer Interfaces

It is important to understand the buried interfacial structures containing epoxy underfills as such structures determine the interfacial adhesion properties. Weak adhesion or delamination at such interfaces leads to failure of microelectronic devices. Sum frequency generation (SFG) vibrational spectroscopy was used to examine buried interfaces at polymer/model epoxy and polymer/commercial epoxy resins (used as underfills in flip chip devices) at the molecular level. We investigated a model epoxy: bisphenol A digylcidyl ether (BADGE) at the interfaces of poly (ethylene terephthalate) (PET) before and after curing. Furthermore, small amounts of different silanes including (3-glycidoxypropyl) trimethoxysilane (γ-GPS), (3-Aminopropyl)trimethoxysilane (ATMS), Octadecyltrimethoxysilane (OTMS(18C)), and Octyltrimethoxysilane (OTMS(8C)) were mixed with BADGE. Silane influences on the polymer/epoxy interfacial structures were studied. SFG was also used to study molecular interfacial structures between polymers and two commercial epoxy resins. The interfacial structures probed by SFG were correlated to the adhesion strengths measured for corresponding interfaces. The results indicated that a small amount of silane molecules added to epoxy could substantially change the polymer/epoxy interfacial structure, greatly affecting the adhesion strength at the interface. It was found that ordered methyl groups at the interface lead to weak adhesion, and disordered interfaces lead to strong adhesion.

Design and Fabrication of a Silicon Interposer With TSVs in Cavities for Three-Dimensional IC Packaging

Flip chip is one of the packaging techniques for high-performance components. There is a greater demand on integrating more functions in a smaller chip nowadays. This leads to the increase of I/O density. Organic substrate is the bottleneck of the high-density packaging. A silicon interposer with through-silicon vias (TSVs) is commonly used to provide a platform with a high wiring density to redistribute I/Os. After I/O redistribution, larger solder joints with a larger pitch can be used to connect the interposer to the organic substrate. In this paper, a TSV-based silicon interposer with a cavity and copper pillars for 3-D packaging is presented. The cavity hosts the flip-chip device. There are copper-filled TSVs in the cavity to provide the electrical interconnections to the backside of the interposer. Flip-chip solder bumps are electroplated on the copper pillars. Subsequent to the flip-chip assembly process, the device is seated in the cavity entirely. The backside of the flip chip is lower than that of the surface of the interposer. This provides a better environment for further die stacking on the surface of the interposer. The microfabrication process of the proposed silicon interposer with TSVs in cavities is discussed in detail.

Molding Flow Modeling and Experimental Study on Void Control for Flip Chip Package Panel Molding with Molded Underfill Technology

Moldability is a crucial aspect of flip chip technology. It is an increasing challenge to ensure moldability with rapid advances in flip chip technology such as decreasing bump pitch and stand-off height, especially when commercial molded underfill (MUF) is used and, in particular, during panel level molding. One key challenge faced is severe void entrapment beneath the die. Typically, large DOE matrix experiments are used to address this issue, which require significant time and process resources. 3D flow simulation can be used to optimize the process to reduce defects with a smaller number of actual runs. By correlating theoretical and experimental phenomena, flow simulation enhances the understanding of the complex fluid dynamics during the molding process. 3D flow simulation can assist in widening the process window, which is limited by the inherent machine and material challenges. This can be achieved by prediction of the effect of varying design, material, and process parameters on melt front behavior and void locations. 3D mold flow simulation using Moldex3D V10 is used to optimize the MUF transfer molding on selected flip chip devices. This paper proposes and verifies a systematic flow simulation methodology designed to save computational resources by using a three step analysis. The initial step, simplified panel level simulation, is to optimize the process parameters to obtain a balanced melt front. Next, on the package level, we studied the effect of various parameters. This analysis provides a prediction of the void location and an insight into the appropriate parameters to minimize the void problem. The optimized parameters from the preliminary simulation were used as guidelines. For the second step, a full validation was conducted. A complete full panel-level flow model was built, where the process and design parameters adopted in the actual molding were implemented. The actual void location and size from the experiment were captured by scanning acoustic microscope (SAM) machine and parallel lapping (p-lapping). Short shots were also obtained to study the melt front behavior. The panel mold filling simulations showed good correlation with the experimental short shots and actual void locations. The prediction capability is further enhanced by zooming in to the column level, and this enhanced model was able to predict the other lower risk voids away from the main problem areas. This was correlated with actual CSAM data and p-lapping. The 3D flow simulation enhances the understanding of causes of flow imbalance, void signature, void formation, and the effect of varying bump height, die thickness, mold cap thickness, gate height, die orientation, transfer profile, and mold temperature as potential enhancement measures. With a successful correlation between simulation and process data as shown in this paper, we have demonstrated that mold flow simulation is a reliable tool to effectively reduce the design-to-implementation cycle time, identifying potential key problems during actual fabrication and potential solutions to reduce defects.

Extending acoustic microscopy for comprehensive failure analysis applications

In manufacturing of microelectronic components, non-destructive failure analysis methods are important for quality control. These non-destructive methods enable rapid defect localization which then guides micro-structural investigations involving destructive sample preparation. Scanning acoustic microscopy (SAM) is a powerful tool for the inspection of internal structures in optically opaque materials. Depth-specific information can be extracted and applied to create two- and three-dimensional images without the need for time consuming tomographic scan procedures. While traditional SAM imaging of the signal intensity is very valuable, it leaves most of the potential of acoustic microscopy unused. The aim of the current work was to develop comprehensive analysis algorithms to utilize the full potential of SAM and thus to extend the range of its applications. Examples representing different application fields were investigated in the current study. The examples include advanced flip-chip devices, bonded wafer pairs, solder tape connectors of a photovoltaic solar panel and high density chip-to-chip interconnects relevant for 3D integration. Progress achieved during this work can be divided into four categories: Signal Analysis and Parametric Imaging, Signal Analysis and Defect Evaluation, Image Processing and Resolution Enhancement and acoustic GHz microscopy (GHz-SAM). For the first three categories, data acquisition was performed using a commercially available scanning acoustic microscope equipped with several ultrasonic transducers covering the frequency range from 15 to 175 MHz. In the fourth category, data acquisition was performed employing a prototype of a novel acoustic GHz microscopy tool which is currently under development into a commercial system. In the first three categories, recorded acoustic data were subjected to sophisticated algorithms operating in time, frequency and spatial domains for performing signal and image analysis. Acoustic microscopy, combined with such advanced signal and image processing algorithms, proved to be a powerful tool for non-destructive inspection.

On the implementation of computed laminography using synchrotron radiation

Hard x rays from a synchrotron source are used in this implementation of computed laminography for three-dimensional (3D) imaging of flat, laterally extended objects. Due to outstanding properties of synchrotron light, high spatial resolution down to the micrometer scale can be attained, even for specimens having lateral dimensions of several decimeters. Operating either with a monochromatic or with a white synchrotron beam, the method can be optimized to attain high sensitivity or considerable inspection throughput in synchrotron user and small-batch industrial experiments. The article describes the details of experimental setups, alignment procedures, and the underlying reconstruction principles. Imaging of interconnections in flip-chip and wire-bonded devices illustrates the peculiarities of the method compared to its alternatives and demonstrates the wide application potential for the 3D inspection and quality assessment in microsystem technology.

Vibrations in the Flip-Chip Soldering Process

General results are presented for the dynamics of all six degrees of freedom of a rigid flip-chip device connected by an array of melted solder joints to a substrate subjected to small stationary random accelerations. The solder joints are modeled as dissipative fluid members which develop a linear restoring force when displaced in the horizontal or vertical directions. The parameters for this model (stiffness and damping of the melted joints) are obtained experimentally by measuring the resonant behavior of a device oscillating in the out-of-plane direction. A quantitative model is constructed for an arbitrary device for the statistics of the translational degrees of freedom, rotational degrees of freedom, and solder joint deformations.

Surface and Buried Interfacial Structures of Epoxy Resins Used as Underfills Studied by Sum Frequency Generation Vibrational Spectroscopy

Flip chip technology has greatly improved the performance of semiconductor devices, but relies heavily on the performance of epoxy underfill adhesives. Because epoxy underfills are cured in situ in flip chip semiconductor devices, understanding their surface and interfacial structures is critical for understanding their adhesion to various substrates. Here, sum frequency generation (SFG) vibrational spectroscopy was used to study surface and buried interfacial structures of two model epoxy resins used as underfills in flip chip devices, bisphenol A digylcidyl ether (BADGE) and 1,4-butanediol diglycidyl ether (BDDGE). The surface structures of these epoxies were compared before and after cure, and the orientations of their surface functional groups were deduced to understand how surface structural changes during cure may affect adhesion properties. Further, the effect of moisture exposure, a known cause of adhesion failure, on surface structures was studied. It was found that the BADGE surface significantly restructured upon moisture exposure while the BDDGE surface did not, showing that BADGE adhesives may be more prone to moisture-induced delamination. Lastly, although surface structure can give some insight into adhesion, buried interfacial structures more directly correspond to adhesion properties of polymers. SFG was used to study buried interfaces between deuterated polystyrene (d-PS) and the epoxies before and after moisture exposure. It was shown that moisture exposure acted to disorder the buried interfaces, most likely due to swelling. These results correlated with lap shear adhesion testing showing a decrease in adhesion strength after moisture exposure. The presented work showed that surface and interfacial structures can be correlated to adhesive strength and may be helpful in understanding and designing optimized epoxy underfill adhesives.

Mechanical Properties of Flip-Chip Solder Joints Effected by Electromigration

A frequent cause of failure of portable and hand-held devices is an accidental drop to the ground. The effect of electromigration on the mechanical properties of solder joints was discussed in this paper. Without current stressing, the samples were broken in the bulk of solder or at the interface of Al interconnect and solder. If the Al-solder interfacial mechanical strength was improved by changed the interfacial structure or optimized the jointing process, the flip chip devices would show the lonely ductile fracture in the bulk of solder. After electromigration the samples were broken abruptly at the interface near the chip side while the bulk of the solder joints maintained the original shape. Due to the interfacial reaction and the polarity effect of electromigration on the interfaces, a ductile solder joint can become a brittle solder joint. The ductile-to-brittle transition is very sensitive to a high speed shear stress applied to the joints. Because solder alloys are ductile by nature, it is of interest to understand how electromigration can influence the mechanical properties of solder joints’ interfaces and change their ductile nature. Owing to the polarity effect of electromigration, vacancies will accumulate to form voids at the cathode interface of solder joints. Besides, much more intermetallic compound formation at the joint interfaces also caused the ductile-to-brittle transition. Thus the interfaces become more and more brittle with time due to IMC formation or vacancy accumulation from electromigration.

“IC Packaging Trends Causing Concerns in Complete Flux Removal”

The complete cleaning and removal of flux / soil residues under low profile components (especially flip-chip devices) are becoming more critical, especially as the conductor spacing’s decreases and the power increases. The reliability of the circuit can be greatly affected when residues are not completely removed. Flip chip bump pitch and die size push packaging trends resulting in tighter and smaller spaces underneath the devices. A majority of flip-chip assemblers are using water soluble fluxes and they typically use only DI water to remove the flux residues. Because of the tighter spaces and increased I/Os, the complete removal of these water soluble flux residues are becoming more difficult. Due to the ionic nature of water soluble flux residues all residue must be removed to prevent a pathway for electrochemical migration and acceptable bonding of the underfill material. To insure that all of the flux residues are being removed from under the package, cleaning chemistries must be used. Cleaning chemistries provide the polarity and hydrogen bonding forces needed to remove oxidized flux while lowering surface tension to improve penetration under the die. The cleaning agent design must also be matched with the cleaning equipment. To completely remove flux residue under the IC packages, the cleaning equipment’s dynamic energy must also be studied, along with the cleaning chemistry. Additionally, both the cleaning chemistry and equipment must be matched up with the flux residue that is being removed. This paper will evaluate various cleaning chemistries and cleaning equipment that provide the best cleaning performance for very low package stand-offs and tighter pitch devices, as well as the different flux residues and process parameters.

Flip Chip Fine Pitch PBGA Yield Study

With demands for higher electrical performance of Flip Chip Devices, the combined effect of fine bump pitch and thinner substrates impacts the die to substrate bump interface yield at assembly. This study utilizes Surface Evolver and Monte Carlo simulations to study the effects of bump design, warpage, and die size on bump yield loss. While warpage at solidification temperature proves to be the largest contributor to bump yield loss, there are design parameters that can be adjusted to maximize yield at various warpage and die size profiles.