Flip-chip Ball Grid Array Package Research Articles

Electrical Design and Techniques for an Embedded High-Pin-Count LSI Chip Package

In order to achieve the excellent electrical performance, as well as low warpage and high heat removal, electrical design techniques for an ultrathin large-scale integration (LSI) package embedding a high-pin-count LSI chip in the thin package substrate have been developed. The embedded chip package we designed is 27 mm × 27 mm in size and 0.71 mm in thickness with a heat spreader. The package is attained with only three metal layers against the six metal layers of the product flip-chip ball grid array package using the same chip, even though the package size is the same. Although the two power plane layers have been removed from the substrate, the low impedance of the power distribution network is achieved by utilizing many bundles of fine vias. A 0.5-mm-thick Cu plate attached to the LSI chip's backside provides the signal return path, and contributes to the flatness of this thin package. It also effectively removes heat from the chip. In addition, it functioned as a shield component and results in electromagnetic interference suppression. Our design for a fully operative LSI chip with approximately 1500 pins demonstrates excellent electrical performance as well as small thickness, low warpage, and a high rate of heat removal. Function tests using an LSI tester and a PC-like system board successfully demonstrate the outstanding performance of the LSI chip. Finally, the advantage of a heat sink connected to ground plane of the package is discussed. It is found that, for excellent near-field noise suppression effects, the heat sink must be connected to the ground plane.

Isothermal Aging Effects on the Mechanical Shock Performance of Lead-Free Solder Joints

Isothermal aging effects on lead-free solders have been extensively investigated in recent studies. Researches show that aging effects significantly degrade the mechanical properties of lead-free solders. However, limited work has been done on the effects of aging on the board-level dynamic performance of lead-free solder joints, especially for large flip-chip ball grid array (FCBGA) packages. Due to the sensitivity of aging effects on lead-free solders, it is crucial to investigate the aging effects on the board-level dynamic performance of lead-free solders. In this paper, dynamic performance of lead-free solder joints has been characterized and isothermal aging effects have been investigated. It was found that the dynamic shock performance of lead-free FCBGA packages significantly degrades up to 20-35% after aging at elevated temperatures. It was also observed that aging at 100°C shows more severe degradation than aging at 75°C and 150°C. This is an important finding because many electronic products operate in the 100°C range for long periods. The unique finding of aging effects is related to the growth of Cu <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> Sn and Cu <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sub> Sn <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</sub> intermetallics after aging. Even though failure analysis shows mixed failure of pad cratering and intermetallic compound (IMC) failures, the IMC growth is the most sensitive factor contributing to the failure observed.

Development of Large Die Fine-Pitch Cu/Low-$k$ FCBGA Package With Through Silicon via (TSV) Interposer

The continuous push for smaller bump pitch interconnection in line with smaller Cu/low- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> technology nodes demands the substrate technology to support finer interconnection. However, the conventional organic buildup substrate is facing a bottleneck in fine-pitch wiring due to its technology limitation, and the cost of fabricating finer pitch organic substrate is higher. To address these needs, Si interposer with through silicon via (TSV) has emerged as a good solution to provide high wiring density interconnection, and at the same time to minimize coefficient of thermal expansion mismatch to the Cu/low- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> chip that is vulnerable to thermal-mechanical stress and improve electrical performance due to shorter interconnection from the chip to the substrate. This paper presents the development of TSV interposer technology for a 21 × 21 mm Cu/low- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> test chip on flip chip ball grid array (FCBGA) package. The Cu/low- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> chip is a 65-nm nine-metal layer chip with 150-μm SnAg bump pitch of total 11 000 I/O, with via chain and daisy chain for interconnect integrity monitoring and reliability testing. The TSV interposer size is 25 × 25 × 0.3 mm with CuNiAu as under bump metallization on the top side and SnAgCu bumps on the underside. The conventional bismaleimide triazine substrate size is 45 × 45 mm with BGA pad pitch of 1 mm and core thickness of 0.8 mm. Mechanical and thermal modeling and simulation for the FCBGA package with TSV interposer have been performed. TSV interposer fabrication processes and assembly process of the large die mounted on TSV interposer with Pb-free solder bumps and underfill have been set up. The FCBGA samples have passed moisture sensitivity test and thermal cycling reliability testing without failures in underfill delamination and daisy chain resistance measurements.

Simultaneous Characterization of Theta-JC and Theta-JB Using Through-Package 1-D Heat Flow

A new technique is proposed for simultaneous, in-situ characterization of in-package thermal resistances (junction-to-case and junction-to-board) in a single test. A thin resistive heater is patterned on package top surface to establish one-dimensional heat conduction along the package vertical direction. Accompanying temperature rise at the heater is measured using a thermocouple and analyzed to estimate equivalent thermal R-C network model of the package. Due to the one-dimensionality of the probing thermal wave, the derived R-C network model represents physical package thermal structure, enabling simultaneous estimation of both thermal resistances (theta-JC and theta-JB). The proposed technique is validated by measuring theta-JC and JB of an overmolded flip-chip ball grid array package. The proposed method eliminates need for a separate test setup for the characterization of each thermal resistance, enhancing the accuracy and efficiency of the package thermal characterization. In addition, use of the external heater and sensing element, instead of on-chip heater and temperature sensor, enables in-situ thermal characterization of a real package mounted on the set board.

Z-axis Interconnections for Next Generation Packaging

In this paper, the use of electrically conducting adhesives (ECA) to form z-axis interconnections for next generation packaging is discussed. In particular, current efforts related to Z-axis interconnections for device level fabrication, integration, and electrical performance are highlighted. A few optimized ECAs were used for hole fill applications to fabricate Z-axis interconnections in laminates. Conductive joints were formed during composite lamination using the ECA. Around 5,000 to 200,000 through holes in the joining cores, formed by laser or mechanical drilling, and having diameters ranging from 50 μm to 750 μm, were filled with an optimized conducting adhesive. The adhesive-filled joining cores/layers were laminated with circuitized subcomposites to produce a composite structure. As a case study, a variety of z-axis interconnect constructions for a flip-chip plastic ball grid array package, rigid-flex, rigid-rigid, package-interposer-package (PIP), RF structures, and PWBs were fabricated and evaluated at both the subcomposite and composite levels to understand structural and electrical integrity. Electrically, S-parameter measurements showed very low loss at multi-gigahertz frequencies. The losses were low enough to support typical SERDES up to 15 Gbps over 750 mm. The present process allows fabrication of z-interconnect conductive joints having diameters in the range of 55 to 500 μm. The processes and materials used to achieve smaller feature dimensions, satisfy stringent registration requirements, and achieve robust electrical interconnections are discussed.

Coupled Thermal-Stress Analysis for FC-BGA Packaging Reliability Design

In order to improve electronics packaging design, it is important to evaluate the cooling performance and reliability of the electronics packaging structure of a product. To that end, it is necessary to predict the temperature, deformation, and stress distributions of the package under field conditions. In the case of a packaging structure comprising a flip-chip ball grid array package, a heat spreader, thermal grease, a cooling structure, solder joints, and a motherboard, an increase in the contact thermal resistance may occur, depending on the interface contact condition between the cooling structure and the heat-spreader due to the thermal deformation of the package. Contact thermal resistance problems involve the interactive relationship of the thermal and stress distributions. A coupled thermal-stress analysis, with consideration of the time-space variation of contact thermal resistance, was conducted to duplicate the behavior of temperature, deformation, and stress distributions of a flip-chip ball grid array package under field conditions. It was found that: 1) the average contact thermal resistance across the interface between the heat-spreader and the plate fin, which was predicted by the coupled thermal-stress analysis, increased compared to the average contact thermal resistance in the case of uniform contact pressure, and 2) the contact thermal resistance will vary depending on the deformation mode, such as convex upward and downward, due to heat dissipation under field conditions. In addition, a reliability prediction method for thermal fatigue failure of solder bumps based on coupled thermal-stress analysis and statistical and probabilistic methods was proposed in order to select a suitable packaging solution at an early stage of design. It was found that the sensitivity of uncertain variables and the thermal fatigue life distribution of solder joints could change significantly depending on a combination of factors concerning the failure sites of solder bumps and the boundary conditions of the motherboard.

Thermal characteristics evaluation for board-level high performance flip-chip package equipped with vapor chamber as heat spreader

Thermal analysis was performed in this work to compare the thermal performance of a board-level high performance flip-chip ball grid array package equipped with solid Cu or vapor chamber (VC) as the heat spreader and Al-filler gel or In solder as the thermal interface material (TIM). The effect of different heat source sizes was also examined. Numerical results indicate that for the particular test vehicle under a power dissipation of 160 W, the thermal performance is remarkably enhanced by switching TIM from Al-filler gel to In solder while the enhancement by using VC instead of solid Cu heat spreader is only observable when In solder is incorporated. Moreover, the performance of VC gradually enhances then retards as the heat source size decreases. The retardation can be attributed to the more dominant role of die in heat dissipation when the heat source size gradually shrinks.

Effect of glue on reliability of flip chip BGA packages under thermal cycling

Glue is widely used to improve the reliability of ball grid array (BGA) under mechanical shock and vibration. Although it has been demonstrated to have a positive effect on the reliability of BGA under mechanical impact, it can have adverse effects on BGA under thermal cycling. This paper investigates the effect of glue on the reliability of BGA under thermal cycling using both experimental and numerical methods. The digital image correlation (DIC) technique was used to obtain the thermal mechanical behavior of the package. The experimental results explain in detail how the glue negatively affects the reliability of the BGA. Furthermore, a finite element analysis was performed and its results were verified with experimental results. A numerical parametric study was carried out on various mechanical properties, configurations of the glue, and introduction of a stiffener using the validated FEM model. The results show that the reliability of BGA strongly depends on geometries and material properties of the glue. Based on the results, a guideline of glue selection for BGA reliability under thermal cycling is formulated.

Optimization of the Thermomechanical Reliability of a 65 nm Cu/Low-$k$ Large-Die Flip Chip Package

The trend toward finer pitch and higher performance integrated circuit devices has driven the semiconductor industry to incorporate copper and low-k dielectric materials. However, the low-k materials have lower modulus and poorer adhesion compared to the common dielectric materials. Thus, thermomechanical failure is one of the major bottlenecks in the development of Cu/low-k larger-die flip chip packages. This paper describes the optimization of the structural design of Chartered's C65 nm 21 mm times 21 mm die size flip-chip ball grid array package incorporated with fully active and functional ninemetal Cu/low-k layers and 150 mum interconnect pitch. The lowk material used in this paper is nonporous SiCOH with a k value of 2.9. A parametric study using 2-D plane strain finite element analysis was performed to study the effect of various parameters on the reliability of the large-die package in order to arrive at an optimized design. In order to have a simple criterion to predict the reliability of the yet-to-be-built largedie package, reliability tests were carried out on some existing 15 mm times 15 mm die CvJlow-k flip chip packages which were identical to the 21mm times 21mm die package except for the size. The packages were found to pass the reliability tests. 2-D plane strain finite element analyses were then performed on the 15 mm times 15 mm die. The computed delamination stresses at the low-k layer and the strain energy density dissipation per cycle in the critical solder (DeltaW) were then used as a benchmark for the design of a larger flip chip package. The efficacy of the polymer encapsulated dicing lane technology was established. In this paper, the effect of the number of fluorosilicate glass layers, die thickness, substrate thickness, Cu post height, and underfill type on the delamination stresses in the low-k layer and DeltaW were determined. Specimens of the optimized large-die package were then fabricated and subjected to reliability tests. They were all found to pass the reliability tests. From these reliability tests, new benchmark values of the delamination stresses at the low-k layer and DeltaW are obtained, which can be used to aid in the design of large-die Cu/low-k flip chip packages.

Copper pillar bump design optimization for lead free flip-chip packaging

The interfacial delamination between the under bump metallurgy and the aluminum (Al) pad was observed in a copper (Cu) pillar bump evaluation in the work. The finite element analysis was employed to investigate the failure mechanism and the cu pillar bump geometry designed optimization. The finite element simulation result shows that the Cu pillar bump sustains the largest tensile stress at the temperature cycling test. The larger diameter Cu pillar bump can reduce the tensile stress significantly at the high temperature stress environment. Besides, an experiment confirms the finite element simulation result. Furthermore, an underfill with high glass transition temperature (T g) and high modulus also improve the flip-chip ball grid array packaging reliability.

A practical investigation on nickel plated copper heat spreader with different catalytic activation processes for flip-chip ball grid array packages

This study investigates the effects of two different catalytic activation techniques on the thermal performance of the flip-chip heat spreaders. The two activation techniques studied are thin nickel–copper strike and galvanic initiation. Thermal diffusivity and surface roughness of these heat spreaders were studied using the Nano-flash Apparatus and Infinite Focus Microscopy. High temperature storage tests were carried out to investigate the extent of intermetallic diffusion between the nickel and copper layers. The results show that heat spreaders with thin nickel–copper strike catalytic activation technique have a lower thermal diffusivity due to the low thermal conductivity of nickel–copper layer. Moreover, the nickel–copper layers grew thicker from around 0.2 μm at initial time to around 0.55 μm after high temperature storage duration of 168 h. On the other hand, heat spreaders processed using the galvanic initiation technique did not form any nickel–copper intermetallic diffusion layer. As a conclusion, the galvanic initiation technique can potentially provide better thermal performance for heat spreaders used in semiconductor packages.

IMC Growth Mechanisms of SAC305 Lead-Free Solder on Different Surface Finishes and Their Effects on Solder Joint Reliability of FCBGA Packages

Intermetallic compound (IMC) growth behavior of lead-free solder plays an important role in ball grid array (BGA) solder joint reliability for flip chip BGA (FCBGA) packaging applications. The growth mechanism of IMC is reported based on a diffusion model. Thermal treatment such as accelerated thermal cycling (ATC) and isothermal aging exposure also contribute to the growth rate and morphology of lead-free solder IMC. Among the lead-free solder alloys, Sn-3.0wt.%Ag-0.5wt.%Cu (SAC305) solder is a promising substitute for Sn-Pb because of its good mechanical properties and wettability with current surface finishes. After thermal exposure, BGA solder joint reliability is degraded due to IMC formation and growth. In this study, two different thermal treatments, ATC and isothermal aging, and two different pad surface finishes, solder on pad (SOP) and electroless Ni immersion gold (ENIG), are considered in terms of IMC growth rate and mechanical solder joint reliability. An SOP finished interface forms a thin ε-phase Cu3Sn layer and a scallop-like η-phase Cu6Sn5 layer. In contrast, the ENIG finished interface forms a thick (Cu,Ni)6Sn5 IMC layer and prevents overall IMC growth. Different surface finished test vehicles are evaluated in an ATC test in a 0°C to 100°C temperature range and the Ni diffusion layer shows a longer solder joint fatigue lifetime than the nondiffusion barrier interface based on the micro cross-section and dye penetration analysis results. In an isothermal aging test at 100°C and 150°C, the aging temperature and time are valid factors to decide mechanical shock reliability. Interfacial fractures are found in the 100°C aged test vehicle due to easier crack propagation at the interface between the thin Cu3Sn layer and the scallop-like Cu6Sn5 layer based on SEM microstructure analysis results. Finally, this investigation proposes how to improve solder joint reliability and prevent interfacial fracture for SAC305 lead-free application.

Material Solutions for Advanced Thin Packages

This paper describes thermo-mechanical reliability parameters of thin flip-chip ball-grid array packages--warpage at room and reflow temperatures and solder-bump-fatigue during temperature-cycling tests--as calculated using finite element method. Viscoelasticity of the underfill is considered to improve the accuracy of calculations. The parameters obtained considering the viscoelasticity of the underfill are compared with those obtained considering elasticity alone; they are also compared with parameters obtained from experiments. Optimal properties of the underfill are proposed for thinner reliable flip-chip packages. Results of this study also demonstrate that substrates with a smaller coefficient of thermal expansion and with higher stiffness are necessary for thinner reliable flip-chip packages.

Underfill selection methodology for fine pitch Cu/low-k FCBGA packages

A systematic underfill selection approach has been presented to characterize and identify suitable underfill encapsulants for large size flip chip ball grid array (FCBGA) packages. In the selection scheme, a total of six evaluation factors such as fracture toughness, coefficient of moisture expansion, flowability, delamination performance and filler settlement were considered. Driving stresses for package failure were also included as a factor of consideration, which clearly depends on the package size and geometry. Based on the approach adopted, underfill material that is suitable for 35 × 35 mm 2 packages with 15 mm die size and 45 × 45 mm 2 packages with 21 mm die size was selected. Target value for underfill properties has also been revised.

Multiband Electromagnetic-Bandgap Structures for Applications in Small Form-Factor Multichip Module Packages

The design and implementation of package-level electromagnetic-bandgap (EBG) structures is presented. By using spiral-based inductance-enhanced electromagnetic-bandgap structures (IE-EBGs), the relative periodicity for achieving bandgap at extremely low frequencies is substantially reduced in comparison to traditional EBGs. Using both full-wave electromagnetic simulation and experimental characterization, it is demonstrated that this type of structure can exhibit multiple bandgaps, which are individually tunable through variation of the inductance per unit area and/or the unit cell periodicity. Sample structures with dimensions compatible with today's microprocessor packaging technology are designed and fabricated in a multilayer organic flip-chip ball-grid array package substrate. These package-embedded IE-EBGs have unit cell dimensions less than 750 mum and exhibit the first forbidden bandgaps for electromagnetic wave propagation below 10 GHz, which is a frequency band of interest for commercial wireless communication systems.

Comparing the Impacts of the Capillary and the Molded Underfill Process on the Reliability of the Flip-Chip BGA

In the assembly process for the conventional capillary underfill (CUF) flip-chip ball grid array (FCBGA) packaging the underfill dispensing creates bottleneck. The material property of the underfill, the dispensing pattern and the curing profile all have a significant impact on the flip-chip packaging reliability. Due to the demand for high performance in the CPU, graphics and communication market, the large die size with more integrated functions using the low-K chip must meet the reliability criteria and the high thermal dissipation. In addition, the coplanarity of the flip-chip package has become a major challenge for large die packaging. This work investigates the impact of the CUF and the novel molded underfill (MUF) processes on solder bumps, low-K chip and solder ball stress, packaging coplanarity and reliability. Compared to the conventional CUF FCBGA, the proposed MUF FCBGA packaging provides superior solder bump protection, packaging coplanarity and reliability. This strong solder bump protection and high packaging reliability is due to the low coefficient of thermal expansion and high modulus of the molding compound. According to the simulation results, the maximum stress of the solder bumps, chip and packaging coplanarity of the MUF FCBGA shows a remarkable improvement over the CUF FCBGA, by 58.3%, 8.4%, and 41.8% (66 mum), respectively. The results of the present study indicates that the MUF packaging is adequate for large die sizes and large packaging sizes, especially for the low-K chip and all kinds of solder bump compositions such as eutectic tin-lead, high lead, and lead free bumps.

Advanced Packaging: The Redistributed Chip Package

The redistributed chip package (RCP) is a substrate-less embedded chip package that offers a low-cost, high performance, integrated alternative to current wirebond ball grid array (BGA) and flip chip BGA packaging. Devices are encapsulated into panels while routing of signals, power, and ground is built directly on the panel. The RCP panel and signal build up lowers the cost of the package by eliminating wafer bumping and substrates thereby enabling large scale assembly in panel form. The build up provides better routing capabilities and better integration. Also, by eliminating bumping, the device interconnect is inherently Pb-free, and the stress of the package is reduced enabling ultra-low-k device compatibility. The panel is created by attaching the device active side down to a substrate, encapsulating and curing the devices, grinding to desired thickness, and then removing the substrate. Signal, power, and ground planes are created using redistribution-like processing. Multilayer metal RCP packages have passed 40 to 125 C air-to-air thermal cycling and HAST after MSL3/260 preconditioning.

Optimization of board-level thermomechanical reliability of high performance flip-chip package assembly

In this paper, we study board-level thermomechanical reliability of a high performance flip-chip ball grid array package assembly subjected to an accelerated thermal cycling test condition. Different control factors are considered for an optimal design towards enhancement of the thermal fatigue resistance of solder joints. These factors include solder composition, underfill, substrate size, lid thickness, stiffener ring width, test board size, soldermask opening on the substrate side, and pad size on the test board. The shape of solder joints after reflow is estimated using Surface Evolver. The optimal design is obtained using an L 18 orthogonal array according to the Taguchi optimization method. Importance of these control factors on the board-level thermomechanical reliability of the package is also ranked.

Focus on materials

Focus on materials

Global-to-Local Modeling and Experiment Investigation of HFCBGA Package Board-Level Solder Joint Reliability

Due to the high speed and high I/O count requirements for semiconductor packages, thousands of soldered interconnections are indispensable, and this situation renders traditional finite element method (FEM) analysis a formidable challenge. This paper presents a 3D-equivalent global model and local submodeling technique to investigate board-level solder joint reliability under cyclic temperature loading. The equivalent global model is capable of addressing critical solder failure locations. An individual local solder ball is used to predict the number of cycles to failure. The high performance flip-chip ball grid array (HFCBGA) package case was studied with the provided experimental data. According to FEM results, the predicted solder ball life is close to that observed experimentally. Therefore, the global-to-local modeling technique can be concluded to provide an efficient methodology for evaluating very high pin count HFCBGA package reliability.