Flip-chip Ball Grid Array Package Research Articles

Internal Bump Cracking Risk Assessment for Flip Chip Ball Grid Array Package During Board Level Reliability Test Through Finite Element Analysis

The performance of semiconductor devices during board-level reliability (BLR) thermal cycling tests continues to be a concern in different applications. The primary focus of those BLR tests is to evaluate the fatigue life of external solder joints between the package and printed circuit board (PCB). For flip-chip ball grid array (FCBGA) package technology, internal solder bumps can also crack and result in open electrical failure. This type of BLR failure has yet to be widely reported in the literature. This article presents failures due to internal solder bump cracks during the BLR test. Failure analysis (FA) clearly shows the cracking location strongly depends on bump density. Finite Element Analysis (FEA) based simulation is performed to understand the failure mechanism. Unlike the standard BLR modeling approach, which focuses on predicting external solder joint fatigue life with correlated data, simulation here has to capture the entire internal bump pattern in the global BLR model. The need to capture the entirety of the bump scheme poses a significant challenge to managing the global model size with a reasonable meshing count and running time. Therefore, a customized post-process approach is developed to analyze bump density impact and enable design optimization.

Reliability Evaluation of Board-Level Flip-Chip Package under Coupled Mechanical Compression and Thermal Cycling Test Conditions.

Flip Chip Ball Grid Array (FCBGA) packages, together with many other heterogeneous integration packages, are widely used in high I/O (Input/Output) density and high-performance computing applications. The thermal dissipation efficiency of such packages is often improved through the use of an external heat sink. However, the heat sink increases the solder joint inelastic strain energy density, and thus reduces the board-level thermal cycling test reliability. The present study constructs a three-dimensional (3D) numerical model to investigate the solder joint reliability of a lidless on-board FCBGA package with heat sink effects under thermal cycling testing, in accordance with JEDEC standard test condition G (a thermal range of -40 to 125 °C and a dwell/ramp time of 15/15 min). The validity of the numerical model is confirmed by comparing the predicted warpage of the FCBGA package with the experimental measurements obtained using a shadow moiré system. The effects of the heat sink and loading distance on the solder joint reliability performance are then examined. It is shown that the addition of the heat sink and a longer loading distance increase the solder ball creep strain energy density (CSED) and degrade the package reliability performance accordingly.

Development of high performance flip chip ball grid array (FCBGA) packages for automotive application processors

Automobiles have witnessed rapid proliferation of infotainment, driver assistance and autonomous driving features which have led to significant increase in semiconductor content per car. However, this has also required increased integration of device functionality to meet the new automotive requirements for in-vehicle networking, autonomous driving, infotainment, and sensor integration. Advance technology/packages are needed to provide ideal solutions for automotive grade reliability, high electrical performance, and multi-function integration for automotive application processors. To address these requirements, innovative packages including Flip Chip Ball Grid Array (FCBGA) are the potential solutions. In this study FCBGA packages are developed for automotive processor application and qualified for AEC2 qualification tier. To achieve higher performance and reliability, different package substrate materials such as core dielectric and build-up dielectric were evaluated. Mechanical modelling and simulation of package reliability and influence of key material properties such as coefficient of thermal expansion (CTE), modulus of elasticity (E) and glass transition temperature (Tg) was used to provide guidance for the selection of substrate and assembly materials. Developed packages met all the product performance requirements and passed package qual conditions of high temperature storage life (150°C, 500 hours), temperature cycling (-55 °C to 125 °C, 1000 cycles), temperature humidity bias (85 °C, 85% RH, 1000 hours) and board level temperature cycling (-40 °C to 125 °C, 1000 cycles).

Analysis of warpage of a flip-chip BGA package under thermal loading: Finite element modelling and experimental validation

The objective of this study is to investigate warpage of a Flip-Chip Ball Grid Array (FCBGA) package experimentally and numerically. Projection Moiré technique was used to measure full-field warpage during heating experiment from room temperature up to 250 °C. As temperature changes within the FCBGA package, different thermal strains are generated in the package resulting from the mismatch in the Coefficient of Thermal Expansion (CTE) between the constituent material layers. A finite element model and analytical equations based on the classical bending theory were used to analyze the thermally induced deformations of package under test. The results show that a maximum warpage value of 67 μm with a concave or smiling shape occurred at the neighborhood of 70 °C during heating and 87 μm warpage with a convex crying shape at 250 °C by assuming a stress-free temperature at 175 °C. Warpage analysis showed that the studied FCBGA package exhibits a different curvature in the die region at the center of the package compared to the region outside the die. At temperatures higher than 175 °C, a concave or smiling warpage shape was shown in the die region while a convex or crying shape in the region outside the die. In contrast, at room temperature, the die area has a convex shape warpage, while outside this area presented a concave shape.Furthermore, the good agreement between warpage of the studied package from finite element simulation and measurements was achieved thanks to the use of the measured material's thermal-mechanical properties of the substrate and Molding Compound (MC) rather than using datasheet data. In-plane CTE and Young's modulus of the substrate were measured using stereo-digital image correlation. Moreover, temperature dependent Young's modulus of the MC was measured by nanoindentation.

On the influence of lid materials for flip-chip ball grid array package applications

Autonomous driving is a key vehicle capability for future mobility solutions that relies on the reliability of its high-performance vehicle computer. As for any electronics for automotive applications, thermal management is a crucial point. A very extensively employed approach for improving heat removal is the usage of heat spreaders in the form of a package lid, especially for flip-chip applications. The usage of a lid in flip-chip ball grid array (BGA) packages improves heat removal based on the heat spreading capabilities of the lid, and reduces package warpage, since with a lid the package becomes stiffer. However, adding a lid also increases stresses at solder interconnects. When selecting a material for the lid, the most intuitive criterion is to focus on the material’s thermal conductivity. Sometimes overlooked, the coefficient of thermal expansion (CTE) of the lid also plays an important role regarding package warpage and reliability of thermal interface materials (TIM) as well as solder interconnects, such as solder bumps. This work focuses on the influence of different lid materials at package level for flip-chip applications. Consequently, the influence of three alternative materials is investigated and compared to the performance of a standard copper lid. For the quantification of the effects, a validated finite element model of a flip-chip package is presented, with the thermo-mechanical performance of the studied lid materials validated based on package warpage, peel strains and plastic strain energy density at the bumps, as well as on peel and shear strains at the TIM.

Measurement Capability of Laser Ultrasonic Inspection System for Evaluation of Ball-Grid Array Package Solder Balls

Abstract Laser ultrasonic inspection is a novel, noncontact, and nondestructive technique to evaluate the quality of solder interconnections in microelectronic packages. In this technique, identification of defects or failures in solder interconnections is performed by comparing the out-of-plane displacement signals, which are produced from the propagation of ultrasonic waves, from a known good reference sample and sample under test. The laboratory-scale dual-fiber array laser ultrasonic inspection system has successfully demonstrated identifying the defects and failures in the solder interconnections in advanced microelectronic packages such as chip-scale packages, plastic ball grid array packages, and flip-chip ball grid array packages. However, the success of any metrology system depends upon precise and accurate data to be useful in the microelectronic industry. This paper has demonstrated the measurement capability of the dual-fiber array laser ultrasonic inspection system using gage repeatability and reproducibility analysis. Industrial flip-chip ball grid array packages have been used for conducting experiments using the laser ultrasonic inspection system and the inspection data are used to perform repeatability and reproducibility analysis. Gage repeatability and reproducibility studies have also been used to choose a known good reference sample for comparing the samples under test.

Alternative FCBGA Package Solution Evaluation: High-speed Design Optimization and Electrical Characterization of FOBGA

Abstract There are 2 potentially alternative package solutions proposed to replace Flip-Chip Ball Grid Array (FCBGA) with Ajinomoto build-up film (ABF) substrate. First one is ABF-free solution, Flip-Chip Scale Packages (FCCSP) with laminate-based prepreg material. FCCSP is a mature package solution, and there are various prepreg materials which can be selected to match the original ABF characterization. The focused FCBGA size for FCCSP is from 10 mm x 10 mm to 21 mm x 21 mm, and substrate layer count from 1+2+1L to 2+2+2L. The applications cover memory controllers, Wi-Fi processors, and DTV SoCs. The other package solution is Fan-out Ball Grid Array (FOBGA) which is targeting larger FCBGA with high ABF layer count. The focused maximum package size and layer count of FCBGA are 55 mm x 55 mm and 6+2+6L individually. The potential applications are CPUs, AI accelerators, and networking switches which require extremely high electrical performance. The design concept of FOBGA is to redistribute signal bump locations on FO die, and make an ABF substrate layer accommodate more I/O signals to further reduce the layer count of the ABF substrate. The package signal integrity (SI) and power integrity (PI) analyses are performed to validate the electrical performance of proposed package solutions. Finally, we come out with design guidelines of FOBGA to mitigate the performance degradation due to substrate layer reduction.

Influence of moisture concentration and hydrophobic material on induced stress in FCBGA package under reflow

PurposeThis paper focuses on the fluid-structure interaction (FSI) analysis of moisture induced stress for the flip chip ball grid array (FCBGA) package with hydrophobic and hydrophilic materials during the reflow soldering process. The purpose of this paper is to analyze the influence of moisture concentration and FCBGA with hydrophobic material on induced pressure and stress in the package at varies times.Design/methodology/approachThe present study analyzed the warpage deformation during the reflow process via visual inspection machine (complied to Joint Electron Device Engineering Council standard) and FSI simulation by using ANSYS/FLUENT package. The direct concentration approach is used to model moisture diffusion and ANSYS is used to predict the Von-Misses stress. Models of Test Vehicle 1 (similar to Xie et al., 2009b) and Test Vehicle 2 (FCBGA package) with the combination of hydrophobic and hydrophilic materials are performed. The simulation for different moisture concentrations with reflows process time has been conducted.FindingsThe results from the mechanical reliability study indicate that the FSI analysis is found to be in good agreement with the published study and acceptable agreement with the experimental result. The maximum Von-Misses stress induced by the moisture significantly increased on FCBGA with hydrophobic material compared to FCBGA with a hydrophilic material. The presence of hydrophobic material that hinders the moisture desorption process. The analysis also illustrated the moisture could very possibly reside in electronic packaging and developed beyond saturated vapor into superheated vapor or compressed liquid, which exposed electronic packaging to higher stresses.Practical implicationsThe findings provide valuable guidelines and references to engineers and packaging designers during the reflow soldering process in the microelectronics industry.Originality/valueStudies on the influence of moisture concentration and hydrophobic material are still limited and studies on FCBGA package warpage under reflow process involving the effect of hydrophobic and hydrophilic materials are rarely reported. Thus, this study is important to effectively bridge the research gap and yield appropriate guidelines in the microelectronics industry.

Correlation Studies Between Laser Ultrasonic Inspection Data and Finite-Element Modeling Results in Evaluation of Solder Joint Quality in Microelectronic Packages

Abstract Laser ultrasonic inspection (LUI) is a nondestructive and noncontact technique to evaluate the quality of solder ball interconnections in area-array micro-electronic packages. Dual-Fiber Array Laser Ultrasonic Inspection System was demonstrated identifying defects and failures in chip-scale packages, ball grid array packages, and flip-chip ball grid array packages. The location and severity of the defects and failures in packages have been identified accurately using this system. Further, it is important to establish the correlation between LUI results and the severity of the failures for failure mode analysis, which will enable us to eliminate the need for destructive testing and allow the study of failure evolution in a given sample under continued reliability testing. This paper discusses correlation studies between experimental LUI results and finite-element simulation results from the flip-chip ball grid array packages subjected to thermal cycling reliability testing. The correlation equations will help in predicting the severity of the failures at a given number of thermal cycles based on LUI results. Furthermore, the life of the micro-electronic packages can be predicted accurately from LUI results at a fewer number of thermal cycles.

Evaluation of the Quality of BGA Solder Balls in FCBGA Packages Subjected to Thermal Cycling Reliability Test Using Laser Ultrasonic Inspection Technique

In modern integrated circuit (IC) packaging, it is difficult to perceive and evaluate the quality of the solder ball interconnections due to their complex hidden physical configuration and miniaturization. Laser ultrasonic inspection (LUI) technique is a novel, nondestructive, and noncontact method that has achieved great success in evaluating the quality of interconnections in chip-scale and ball-grid array (BGA) packages. In this article, an enhanced dual-fiber array LUI system is used to evaluate the quality of BGA solder balls in advanced industrial flip-chip BGA packages subjected to thermal cycling reliability tests. LUI results are validated with electrical testing, scanning electron microscope (SEM), and dye-and-pry results. LUI results are well correlated with the intermetallic compound cracks in BGA solder balls observed using SEM, and dye-and-pry. This study demonstrates the feasibility of using the LUI system for one of the modern IC packages and the potential to use the LUI system for future advanced IC packages such as 3-D packaging.

Evaluation of FCBGA Package Subjected to Four-Point Bend Reliability Test Using Fiber Array Laser Ultrasonic Inspection System

Unique two-beam laser ultrasonic inspection (LUI) probes were developed for the inspection of the quality of all types of chip packages. Microelectronic assembly houses demand reliable quality inspection tools that can identify all interconnect defects across the wide range of chip packages in order to allow for cost-effective rework (when applicable) and to prevent field failures. LUI is a noncontact, nondestructive, and cost-effective technique that can be used as both an online and offline tool for evaluating the quality of solder ball interconnections. In this paper, the authors present the development and validation of unique two-beam LUI probes. The developed probes were validated by using them to evaluate the quality of large flip-chip ball grid array (FCBGA) packages. These two-beam laser probes produce high-amplitude signal in multilayer packages. The high-amplitude signal, in turn, improves the signal-to-noise ratio, which facilitates the detection of very small defects as well as large defects. FCBGA packages that underwent four-point bending tests were successfully evaluated for defects such as laminate separations, pad cratering, and cracks. Finally, the packages were cross-sectioned for scanning electron microscopy (SEM) imaging to validate the LUI results. Finite-element (FE) simulation of the package with four-point bending loading conditions was also carried out to further validate the LUI results.

Feasibility Studies and Advantages of Using Dual Fiber Array in Laser Ultrasonic Inspection of Electronic Chip Packages

Fabrication and inspection techniques of electronic packages are two key factors influencing a chip’s success in post-Moore’s law era. As the electronic packaging industry rapidly evolves to cope with modern demands, a versatile inspection method for present and future packages is required. One approach is the development of a fiber array laser ultrasonic inspection system as presented in this paper. The new system uses two laser excitation points, allowing higher total energies to be delivered to the chip’s surface without exceeding the thermoelastic regime and causing damage. These beams induce strong ultrasonic waves, which can penetrate deeper and farther into and across a package. As a result, larger and thicker packages can be nondestructively inspected than was previously possible. Flip-chip ball grid array packages of size 52.5 mm $\times52.5$ mm from Cisco were evaluated using this system and compared against a single-beam system. Benefits of the new system include an increase in vibration amplitude due to high laser power, improved signal-to-noise ratio (SNR), an increase in resolution/sensitivity to measure microcracks, and high speed. The new dual-fiber-array system can administer 400-mW power safely, and as a result, the peak-to-peak amplitude of the generated ultrasound is three times that of ultrasound generated from a single laser beam. The SNR of 8:1 is achieved on the current Cisco package with double excitation point sources compared to the SNR of 1:1 that was obtained with a single excitation point source.

Characteristics of Organic-Based Thermal Interface Materials Suitable for High Temperature Operation

Abstract Historically, for semiconductors subject to standard operating temperatures--which tend not to exceed 125°C--the Tg (glass transition temperatures) of the organic packaging materials protecting the chips is usually around 175°C. Given that, when it comes to electronics operating at high temperatures—typically an environment where the ambient temperature exceeds 200°C—the use of organic materials is generally prohibited due to rapid degradation. At those elevated temperatures, the packaging materials selected are generally composed of metals and ceramics but these materials come with their own shortfalls as well as higher material and manufacturing costs. Therefore, it would be desirable if there were ‘ruggedized’ versions of the organic compounds so commonly used in semiconductor packaging but available for more extreme temperatures, both to reduce cost and package footprint. Meanwhile, the demands from recent developments in high performance computing (HPC) and high-speed data networks means a greater need for increased power and thermal dissipation coupled with very large package body sizes to accommodate the high I/O count. The latest in server microprocessor (MPU) products can easily generate up to 300W during operation, and the heat generated must be quickly transported away from chip to prevent the threat of thermal shutdown. The thermal dissipation issue is controlled by the use of heat spreaders and heat sinks, both of which are intended to make contact with the back-side of a flipped MPU via a thermal interface material (TIM), as part of a large die, large body-size flip-chip ball grid array (FCBGA) package. The thermal interface materials discussed here are examples of organic engineered materials that are capable of withstanding higher operating temperatures than typically seen by semiconductors encased in organic-based packaging. This paper will look at the key material and mechanical attributes for a good thermal interface material, examines the pros-and-cons of various thermal interface material formulations, and discusses the factors for reliable thermal dissipation performance.

Compact 60 GHz Phased-Array Antennas With Enhanced Radiation Properties in Flip-Chip BGA Packages

Compact phased-array antennas embedded in flip-chip ball grid array (BGA) packages are proposed to operate over the unlicensed 60 GHz frequency band. Radiation properties are enhanced by designing novel corrugated soft-surface structures and implementing them using the low-temperature co-fired ceramic process with no extra cost and fabrication complexity. This is achieved by adjusting via land diameters of periodic grounded vias in top four layers of the package, which in fact create perfect magnetic boundaries between the phased-array antenna elements to modify the electric near-field distributions and consequently improve far-field characteristics including gain, cross polarization, sidelobe level, and beam steering. Low-loss transitions from flip-chip IC to antenna elements are designed with less than 0.1 dB amplitude and 2° phase imbalance over 50–70 GHz. Prototypes with/without soft-surface structures are fabricated to work with flip-chip ICs with/without switches. A USB-interface adapter and a waveguide-interface module with a compact vertical power combiner are proposed for the first time to experimentally evaluate the phased-array antenna while connected to the flip-chip RF IC. Significant miniaturizations and improvements are achieved over the wide frequency range of 56–67 GHz, demonstrating up to 7 dB reduction in sidelobe level, up to 4 dB reduction in cross polarization, and up to 3 dB enhancement in gain at different directions.

A Novel Channel Characteristics Estimation Methodology for High-Speed SerDes Interface on Flip-Chip Ball Grid Array Packages

This paper develops a systematic method to estimate the channel characteristics of a high-speed serializer/deserializer (SerDes) interface that is implemented on a build-up laminate flip-chip ball grid array (FCBGA) package. A microstrip multisize ring resonator method is developed to determine the extracted dielectric characteristics of a low-loss build-up substrate. The critical dimensions of the measurement structure of a high-speed SerDes interface are determined using scanning electron microscopy to estimate the channel characteristics. Finally, electromagnetic modeling is performed to systematically validate the measured mixed-mode $S$ -parameters with the help of a double-sided probing system. The proposed systematic validation methodology is successfully validated by making the measurements of the high-speed SerDes interface up to 10 GHz.

New Stacked Die Interconnect Technology for High-Performance and Low-Cost FPGA

This article introduces the first comprehensive demonstration of new innovative technology comprising multiple key technologies for highly cost-effective and high-performance Xilinx field programmable gate array (FPGA), which is so-called stack silicon-less interconnect technology (SLIT) that provides the equivalent high-bandwidth connectivity and routing design-rule as stack silicon interconnect (SSI) technology at a cost-effective manner. We have successfully demonstrated the overall process integration and functions of our new SLIT-employed package using Virtex®-7 2000T FPGA product with chip-to-wafer stacking, wafer-level flux cleaning, microbump underfilling, mold encapsulation, and backside silicon removal. Of all technology elements, both full silicon removal process with faster etching and no dielectric layer damage and wafer warpage management after full silicon etching are most crucial elements to realize the SLIT technology. To manage the wafer warpage after full Si removal, a couple of knobs are identified and used such as top reinforcement layer, microbump underfill properties tuning, die thickness, die-to-die space, and total thickness adjustments. It is also discussed in the article how the wafer warpage behaves and how the wafer warpage is managed. New SLIT module shows excellent warpage characteristics of only −30 μm ∼ −40 μm at room temperature (25°C) for 25 mm × 31 mm in size and +20 μm ∼ +25 μm at reflow temperature (250°C). Thermal simulation results shows that thermal resistance of new SLIT package is almost comparable to that of standard 2000T flip-chip ball grid array (FC-BGA) package using through silicon via interposer with standard heat sink configuration and air wind condition. The reliability assessment is now under the study.

An RDL UBM Structural Design for Solving Ultralow-K Delamination Problem of Cu Pillar Bump Flip Chip BGA Packaging

Copper (Cu) pillar bumps tend to induce high thermal–mechanical stress during environmental tests and fabrication processes due to the high hardness of Cu, especially when applied with an ultralow-K (ULK) chip. A previous experiment showed that interfacial delamination was often observed in the ULK layers of conventional Cu pillar bump-type flip chip ball grid array (FCBGA) packages under thermal cycling, where under bump metallurgy (UBM) layers directly sit on the metal pads of silicon chips (herein termed ‘‘direct UBM structure’’). In this study, a UBM pad relocation scheme through redistribution layer (RDL) technology (herein termed ‘‘RDL UBM structure’’) is proposed to relieve the stress or ULK delamination issue. The proposed technique is tested on Cu pillar bump-type FCBGA packages subjected to thermal loading, the effectiveness of which is demonstrated through finite element stress simulation and experimental reliability tests. Simulation results reveal that the RDL UBM structure can greatly reduce the maximum stress in the ULK layers by as much as about 10% to 44%. Besides, it turns out that the Cu pillar bump-type FCBGA packages with the RDL UBM structure show good interconnect reliability performance in terms of thermal cycling, highly accelerated stress, and high-temperature storage.

Failure Analysis of the Solder Joints in Flip-Chip BGA Packages under Free-Drop Test

The failure of plastic ball grid array under intense dynamic loading was studied in the project. This paper presents the drop test reliability results of SnPb flip-chip on a standard JEDEC drop reliability test board. The failure mode and mechanism of planar array package in the drop test was comprehensively analyzed. High acceleration dropping test method was used to research the reliability of BGA (ball grid array) packages during the free-drop impact process. The model RS-DP-03A drop device was used to simulate the falling behavior of BGA chip packages under the real conditions, The drop condition meets the JEDEC22-B111 standards (pulse peak 1500g, pulse duration 0.5 ms) when dropping from the 650mm height . In the testing, according to the real-time changes of dynamic voltage, the relationship between drop times and different phases of package failure was analyzed. With the dye-penetrated method and optical microscopy, it was easy to observe the internal crack and failure locations. The growth mechanism of the cracks in solder joints under the condition of drop-free was analyzed and discussed.

Effect of Surface Morphology on the Corrosion of Electroless Nickel/Immersion Gold Films

Electroless nickel with immersion gold (ENIG) process has been widely used as a surface finishing for PCB (Printed Circuit Board). The ENIG process provides a uniform coating on Cu layer without any complex patterning process, and so it has wide and diverse electronic industrial applications; fine pitch surface mount, ball grid array(BGA), flip chip BGA packages and so on. However, there is a reliability issue in the ENIG process. Many researchers have pointed out that severe corrosion of electroless Ni surface is the one of the major factors to reliability failure. In the extreme case, it is known as the black pad which caused a failure of solder joint. A content of phosphorous higher than Ni-P deposits was detected on the failed pad surface, and galvanic cell formation resulted into the corrosion due to the difference of P concentration. The Ni surface has a mud-cracked appearance and the phosphorous content is abnormally higher (exceeding 10 wt%). Another similar issue related to ENIG process is pad discoloration due to Ni oxidation on the top of ENIG pad. Such discoloration pad is regarded as a failure due to cosmetic reason and a lack of clear standards. Sometimes, it actually leads to high contact resistance due to Ni oxides on the top of ENIG layer. Excessive oxidation of Ni layer may result in the non-wetting of solder to the ENIG layer during the reflow process for solder ball attachment because it is difficult for the flux to remove such excessive oxides. The Ni oxidation may be owing to Ni cation diffusion passing through Au immersion during wet process such as rinsing steps in the downstream process after ENIG treatment, which is an electrochemical phenomenon as well. Here, the pad discoloration of Ni corrosion during Electroless nickel with immersion gold (ENIG) treatment was investigated by SEM, XPS and cross-sectional EDS analysis. The Ni corrosion happened at the nodule boundary for relatively thinner layer whereas the corrosion pits were generated in the thick Ni deposits. The electroless Ni was amorphous structure, which meant that the domain boundary energy between two Ni nodules did not change during Ni growth. However, the cusp stress at the surface intersection of two nodules gradually decreased during Ni growth, and hence the corrosion mode changed from nodule boundary corrosion to pit corrosion. It can be surmised that the nodule boundary corrosion can be suppressed by increasing Ni nucleation as well as Ni thickness.

Analyzing the Impact of Supply Noise on Jitter in GBPS Serial Links on a Merged I/O-Core Power Delivery Network

In this paper, the impact of integrating large number of I/O (Input-Output) and Core power Delivery Network (PDN) on a 6 layers Flip-Chip Ball Grid Array (FCBGA) package is investigated. The impact of core induced supply noise on high-speed I/O interfaces, and high-speed I/O interface's supply noise coupling to adjacent high-speed I/O interfaces' jitter impact are studied. Concurrent stress validation software is used to induce SSO noise on each individual I/O interfaces; and at the same time; periodic noise is introduced from Core PDN into the I/O PDN domain. In order to have the maximum coupling impact, a prototype package is designed to merge the I/O and Core PDN as one while impact on jitter on each I/O interfaces are investigated. In order to understand the impact of the Core to I/O and I/O to I/O noise, the on-die noise measurements were measured and results were compared with the original PDN where each I/O and Core PDN are standalone and isolated are used as a benchmark.