Internal Bump Cracking Risk Assessment for Flip Chip Ball Grid Array Package During Board Level Reliability Test Through Finite Element Analysis

Abstract

The performance of semiconductor devices during board-level reliability (BLR) thermal cycling tests continues to be a concern in different applications. The primary focus of those BLR tests is to evaluate the fatigue life of external solder joints between the package and printed circuit board (PCB). For flip-chip ball grid array (FCBGA) package technology, internal solder bumps can also crack and result in open electrical failure. This type of BLR failure has yet to be widely reported in the literature. This article presents failures due to internal solder bump cracks during the BLR test. Failure analysis (FA) clearly shows the cracking location strongly depends on bump density. Finite Element Analysis (FEA) based simulation is performed to understand the failure mechanism. Unlike the standard BLR modeling approach, which focuses on predicting external solder joint fatigue life with correlated data, simulation here has to capture the entire internal bump pattern in the global BLR model. The need to capture the entirety of the bump scheme poses a significant challenge to managing the global model size with a reasonable meshing count and running time. Therefore, a customized post-process approach is developed to analyze bump density impact and enable design optimization.