Flip Chip Assembly Research Articles

Invar Electroplating for Controlled Expansion Interconnects

The current trends in convergent systems are to pack as many functions – digital, RF, optical, MEMS, LEDs, and other IoT devices – into a single package or module and current methods of metallizing the ever-shrinking components are rapidly becoming insufficient. A new set of metallization material technologies is necessary to meet these increasing expectations, methods that not only work with the substrates and materials of yesterday but are also ready for the future. The copper that is currently the workhorse of interconnect materials has a coefficient of thermal expansion (CTE) of 17 ppm/K while chip substrates’ CTE ranges from 2 to 7 ppm/K. The thermo-mechanical stresses induced in the package from the CTE mismatch between the die, the substrate and the buildup materials result in solder joint failure, die cracking, copper extrusion, delamination of the solder bumps and cracking of the build-up layers, leading to failure of the assemblies. Matching the CTEs of the chips and the substrates is required for future fine-pitch flip chip and wafer level package assembly in order to improve the solder joint reliability and fabricate stress-free 3D multichip systems. NANO3D Systems has developed an electroplating technique to produce uniform, low-internal-stress and controlled-expansion nickel iron alloy (INVAR) films deposited on different substrates, fabricating redistribution layers (RDL), through silicon vias (TSV), pillars, and free standing foils. INVAR electroplating was performed using a proprietary plating solution containing stabilizers that prevent the oxidation of iron, stress-reducers to reduce internal stress, and wetting agents to improve the surface morphology and eliminate pinholes. The thermal (thermal conductivity, linear thermal expansion, specific heat capacity) and mechanical (Young’s modulus, yield strength, tensile strength and internal stress) properties of the INVAR have been studied and demonstrated superior performance compared to currently available similar products. The composition of the INVAR (36 % of Nickel and 64% of Iron) electroplated films has been confirmed by utilizing SEM/EDX and SIMS. Linear thermal expansion of the films was tested using a technique based on bending of bonded layers due to thermal stress. Internal stress was studied using bent strip techniques. The linear thermal expansion down to 0.4±0.1 (x10-6, K-1) has been obtained for the INVAR plated films plated within a process window that corresponded to the lowest internal stress (30±2 (MPa)) and uniform morphology (Ra ~ 2 nm). The mechanical properties of the INVAR foils have been investigated by use of the Instron technique. The tensile strength of 500 ± 60 (MPa), yield strength of 280 ± 50 (MPa) and the ductility of 40 ± 10% have been measured for the pinhole-free INVAR films. The specific heat capacity of 0.45 ± 0.05 (J/gK)was measured by using differential scanning calorimetry (DSC) at 573 K, while thermal conductivity of as-plated INVAR was 43 ± 5 (W/mK). Smooth, uniform and flat RDL & pillars were fabricated by using through resist INVAR plating on silicon wafers. Optical profilometry studies of the morphology and thickness of plated INVAR on the silicon wafers show Ra ~ 2 nm and high thickness uniformity (of about 5 % & 3s). TSV fill of high aspect ratio features (>10:1) was also demonstrated. After being annealed at 300 0C for 2hr, SIMS studies showed no inter-diffusion in copper/Invar bi-layer foils. Trace impurities were <100 ppm in electroplated INVAR films. Analytical methods have been developed for plating solution analysis. UV-VIS and titration are the two main techniques employed for analysis of metals, organic acids, and buffers in solution. Standard curves were created by analyzing solutions with known concentrations of each analyte. Solutions of varying concentrations were prepared for analysis; low control limit (low), target, and upper control limit (high) concentrations. Blank solutions contained all components except for the one of interest. There was also a blank prepared with no metals at all to be used as the reference in UV-VIS analysis. Multiple analyses were collected for the standard solutions in order to perform a statistical analysis and confirm p/t <0.3. Using the standard curves concentrations of unknowns (active bath solutions) were calculated. The plating additives in INVAR electroplating bath such as stress-reducer, stabilizer and wetting agents were monitored by using cyclic voltammetric stripping (CVS) and FTIR techniques.

Rotational solder self-alignment mechanics modeling for a flip chip in the presence of a viscous fluid

Advent of 2.5/3Dimensional (2.5/3D) integration using through-silicon vias (TSVs) enables the formation of high signal bandwidth, fine pitch, and short-distance interconnections in stacked dies but the new package configuration poses technical challenges in package assembly process. To pace industry demands, a new alternative, Thermal Compression Bonding (TCB), to the conventional Flip Chip on Board (FCOB) process has been being developed for the 3D stacking. Among process materials, epoxy flux (or no-flow underfill) draws high attention again due to its technical advantages in both TCB and mass reflow process. The conventional mass reflow with epoxy flux could provide outstanding benefits to 2.5D package assembly process. The new Low Cost High Throughput Flip Chip Assembly process is one such process requiring fewer processing steps, lower cycle times, and lower cost. In this new process, underfill is dispensed prior to chip placement, and solder reflow and underfill cure occur simultaneously. This reduces the cycle time required for manufacture; however, the presence of a viscous underfill affects the chips' capacity for self-alignment. In a companion study, self-alignment for a flip chip undergoing rectilinear translation was analyzed. This paper applies an equivalent analysis process to a flip chip undergoing rotation in the presence of a viscous underfill. Details of the modeling process are presented along with parametric studies and contrasted against pure translation case. Conditions and process parameters which are more conducive to realignment and those hampering realignment are presented.

Recent Advances and New Trends in Flip Chip Technology

Recent advances in flip chip technology such as wafer bumping, package substrate, flip chip assembly, and underfill will be presented in this study. Emphasis is placed on the latest developments of these areas in the past few years. Their future trends will also be recommended.

Demonstration of Optical Transmission at Bit Rates of Up to 321.4 Gb/s Using Compact Silicon Based Modulator and Linear BiCMOS MZM Driver

We have designed and tested a compact flip-chip assembly that combines the photonic and electrical functionality of a Silicon Photonic modulator and a SiGe BiCMOS MZM-driver. This forms a basis for low-cost advanced optical transceivers.

Thermal stress analysis of the low-k layer in a flip-chip package

The structural integrity on low-k layers is a major reliability concern on three-dimensional packaging technology. The low-k material used in dies has a reduced stiffness and adhesion strength to the barrier materials, which makes the back-end-of-line (BEOL) structure much more vulnerable to the externally applied thermal stress during the flip-chip packaging. This thermal stress can cause a serious impact on the reliability and yield of electronic components, and hence the stress optimization is required. This paper aims to create an equivalent thermal stress model to evaluate the stress conditions in different low-k layers generated during the assembly. The model has only one sub-model and is verified by the flip-chip assembly of a 40nm technology node chip. It is shown that this thermal stress model has the potential to predict the stress variation tendency in the different BEOL layers and hence can be used for the chip packaging interaction study.

Effect of multiple flip-chip assembly on the mechanical reliability of eutectic Au–Sn solder joint

Eutectic Au–Sn solder has widely been used for high temperature bonding since it enables fluxless soldering and provides mechanically stable solder joint. However, effect of multiple bonding process on the mechanical reliability has not been studied in detail. In this study, microstructure evolution of Au–Sn solder joint and its effect on mechanical reliability were systematically investigated. During the multiple reflow process, the eutectic phase gradually transformed into ζ phase, which resulted in loss of solderable area. The phenomenon turned out to be responsible for degradation of bonding strength of the solder joint.

Fabrication of bottom-emitting organic light-emitting diode panels interconnected with encapsulation substrate by Au[sbnd]Au flip-chip bonding and capillary-driven filling process

We present fabrication and testing of bottom-emitting organic light-emitting diode (OLED) panels based on flip-chip assembly and non-destructive scanning. In this method, the OLED and electric circuits are fabricated on separate substrates and interconnected by low temperature assembly to create a high-performance bottom-emitting OLED including other functions such as thin-film transistor (TFT) circuits. The low temperature assembly process consists of two steps. First, an OLED substrate and encapsulation glass with circuits are bonded at 100°C via AuAu bond. Encapsulation glass is utilized for the functional substrate with circuits. Next, the bonded panel is sealed by capillary underfill within and by applying and curing seal materials to the panel edge. The fabricated OLED was non-destructively evaluated by scanning acoustic microscopy (SAM). The SAM image shows all φ500μm Au bumps were bonded to Au pads, indicating that OLED and encapsulation substrates were assembled. Electroluminescence of the OLED was demonstrated by applying voltage. Stable current-luminance characteristics were obtained for the fabricated OLED with an operating voltage of 3.25V. The results indicate that the proposed fabrication is available for bottom-emitting OLED controlled by TFT circuits. In future, the assembly process can be widely applied to other flexible organic electronic devices with roll assembly by altering OLED or circuits with other devices because this is a simple pressure method with low temperature, achieving encapsulation at same time.

A Self-Aligning Flip-Chip Assembly Method Using Sacrificial Positive Self-Alignment Structures

A self-aligning flip-chip assembly method is described. The method is capable of correcting up to 150 $\mu \text{m}$ (five times the radius of solder balls used) of initial misalignment during flip-chip assembly. Critical components of the self-alignment are four polymeric positive self-alignment structures (PSASs), which are fabricated on a substrate, and four inverted pyramid pits, which are etched on a silicon chip in corresponding positions. The PSAS is removed using solvent after the assembly. Resistance of the solder joints is measured to be below 9 $\text{m}\Omega $ .

Advancements in Flip Chip Assembly Equipment and Processes

High I/O devices such as microprocessors, applications processors and field programmable gate arrays have transitioned from wire bonding to flip chip interconnect as the I/O densities have increased above 2000. As the bump pitch shrinks the standard process flow for production flip chip processes is challenged. As the bump pitch continues to shrink the accuracy of standard flip chip bonders is not adequate for the fine pitch packages of tomorrow. The options to resolve this issue are extending the accuracy for standard flip chip bonders or moving the assembly of these packages to the inherently more accurate thermo-compression bonders. This paper will discuss the pros and cons of each approach along with showing data which indicates what accuracies are actually required. Although substrate manufacturers have developed low CTE designs which mitigate the warpage caused by the mismatch between the Si die and the substrate as the assembled package travels through the reflow oven, warpage at finer pitches is becoming more and more difficult to control in flip chip processes. Thermocompression (TC) bonding is seen as the next-generation packaging technology that will resolve this issue through local reflow of the solder and elimination of the reflow oven. Despite the tremendous technical and quality advantages of TC bonding, adoption has been limited by the relatively low throughput of the first generation thermocompression bonders. In this paper we describe bonding results obtained with an innovative flip chip bonding method to optimize the process to dramatically improve the throughput by applying flux directly to the substrate rather than dipping the pillars in a bath. A study of this process and comparison of various methods of accomplishing it along with their related costs are discussed in the paper. A second large productivity improvement that is promising by eliminating the need for cooling the die before transferring die that has pre-applied underfill film laminated to it is also studied with productivity models developed. Finally a unique equipment concept for managing the transition from mass reflow to thermo-compression bonding will be presented.

A 3-Phase Resonant Switched Capacitor Converter Delivering 7.7 W at 85% Efficiency Using 1.1 nH PCB Trace Inductors

In recent years, there has been a push towards high-density and monolithic DC-DC converters to support applications such as performance and mobile computing, consumer electronics, and renewable energy. Switched capacitor (SC) converters have started to gain traction for a number of these applications, but are still subject to fundamental limitations that drive them towards expensive process options and high switching frequencies. Variable regulation is challenging with the SC approach, and comes at the cost of lower power density and efficiency. This work presents a resonant switched capacitor (ReSC) topology that addresses some of these challenges by introducing a small amount of inductance in series with the flying capacitor, eliminating charge-sharing losses and thus allowing efficient operation in a low-cost process option. The three-phase interleaved topology can deliver up to 7.7 W at 85% efficiency (power density of 0.91 W/mm $^{2}$ or 6.4 kW/in $^{3}$ ) using a bootstrapped n-channel power train and single-digit nH inductors embedded in a flip-chip assembly. We also present the first implementation of efficient, fully-variable conversion ratios in a silicon ReSC integrated circuit without reconfiguration or gain-hopping .

Flip-chip assembly of VCSELs to silicon grating couplers via laser fabricated SU8 prisms.

This article presents the flip-chip bonding of vertical-cavity surface-emitting lasers (VCSELs) to silicon grating couplers (GCs) via SU8 prisms. The SU8 prisms are defined on top of the GCs using non-uniform laser ablation process. The prisms enable perfectly vertical coupling from the bonded VCSELs to the GCs. The VCSELs are flip-chip bonded on top of the silicon GCs employing the laser-induced forward transfer (LIFT)-assisted thermocompression technique. An excess loss of < 1 dB at 1.55 µm measured from the bonded assemblies is reported in this paper. The results of high speed transmission experiments performed on the bonded assemblies with clear eye openings up to 20 Gb/s are also presented.

Cost Analysis of Flip Chip Assembly Processes: Mass Reflow with Capillary Underfill and Thermocompression Bonding with Nonconductive Paste

Many factors affect the selection of the assembly and interconnect processes used to package a die. For example, the size of the die and package, the type of substrate, and the number of IOs all must be considered. In this paper, two processes are compared: a flip chip process using mass reflow with capillary underfill versus a flip chip thermocompression bonding process using nonconductive paste. Activity based cost modeling is used for the analysis. Both of the process flows are presented in detail, then multiple cost comparisons are presented. Examples of the variables that will change are package size, material cost, and equipment cost. In most cases, the bonding and material portions of the process flows are focused on rather than the entire assembly and substrate processes—this allows for a better analysis of particular details. Conclusions are drawn about which design scenarios are suitable for each process flow. Key cost drivers that may affect future cost comparisons as the technologies advance are also indicated.

Design of Filled One Step Chip Attach Materials (OSCA) for Conventional Mass Reflow Processing: Rheology Considerations for Jet Dispensing and Die Placement

One step chip attach materials (OSCA) are dispensable polymeric materials for flip chip assembly, which are designed to flux metallic interconnections and subsequently turn into an underfill upon curing. OSCA materials enable a drastic simplification of the assembly process by combining the reflow, flux residue cleaning and capillary underfilling steps used in traditional die attach processing into a single step. A key challenge when designing filled OSCA materials for conventional mass reflow processing (OSCA-R) is to ensure that the materials have a process-friendly rheological design allowing seamless integration with jet dispensing equipment and allowing for accurate die placement. This paper presents research results and design concepts for OSCA-R materials focused on understanding the impact of filler loading, size, type and surface chemistry on rheology and the relationships with jet dispensing performance, die placement and reliability performance for test vehicles constructed with silicon and organic substrates.

HIGH DATA RATE SILICON PHOTONIC - CMOS ELECTRONIC MODULES USING COPPER MICROBUMPS

Achieving high data speed (typically Nx25 Gbps) compact optoelectronic modules is now made possible by using Photonic Integrated Circuits (PIC) combined with CMOS electronic drivers. Among the techniques that can be used to combine both circuits, flip-chip assembly based on micro-bumps shows several advantages, for example low RF parasitics and high density compared to wire bonding. Using this technique, it is possible to build low consumption photonic receivers working at 25 Gbps.

Study of Techniques for Flip-Chip Bonding to Organic Substrates for Low-Power Applications

This paper deals with the study of technologies for flip-chip assembly of CMOS integrated power converters on standard FR4 organic substrates. Tests for the characterization of commercially available technologies for microassemblies, such as anisotropic adhesive bonding, thermocompression bonding, thermosonic/ultrasonic bonding, and solder bonding, are carried out. The aim of this paper is to determine the most suitable flip-chip bonding technology for power CMOS circuits with more than 50 pads. First, the coupled design of the CMOS chip and the corresponding substrate dedicated to low-power microconversion (10 W) is presented. It is shown that the parasitic resistances and inductances of the interconnections increase the conduction and switching losses of the device. This leads to a temperature rise, which can limit the operating ratings of the circuit. The experimental results are provided to evaluate each technology for flip-chip assembly.

The size effect on intermetallic microstructure evolution of critical solder joints for flip chip assemblies

Purpose – The purpose of this paper is to study the intermetallic compound (IMC) thickness, composition and morphology in 100-μm pitch and 200-μm pitch Sn–Ag–Cu (SAC305) flip-chip assemblies after bump reflow and assembly reflow. In particular, emphasis is placed on the effect of solder joint size on the interfacial IMCs between metal pads and solder matrix. Design/methodology/approach – This work uses 100-μm pitch and 200-μm pitch silicon flip chips with nickel (Ni) pads and stand-off height of approximately 45 and 90 μm, respectively, assembled on substrates with copper (Cu) pads. The IMCs evolution in solder joints was investigated during reflow by using 100- and 200-μm pitch flip-chip assemblies. Findings – After bump reflow, the joints size controls the IMC composition and dominant IMC type as well as IMC thickness and also influences the dominant IMC morphology. After assembly reflow, the cross-reaction of the pad metallurgies promotes the dominant IMC transformation and shape coarsened on the Ni pad interface for smaller joints and promotes a great number of new dominate IMC growth on the Ni pad interface in larger joints. On the Cu pad interface, many small voids formed in the IMC in larger joints, but were not observed in smaller joints, combined with the drawing of the IMC growth process. Originality/value – With continued advances in microelectronics, it is anticipated that next-generation microelectronic assemblies will require a reduction of the flip-chip solder bump pitch to 100 μm or less from the current industrial practice of 130 to150 μm. This work shows that as the packaging size reduced with the solder joint interconnection, the solder size becomes an important factor in the intermetallic composition as well as morphology and thickness after reflow.

Reliability Assessment of Flip-Chip Assembly of Al Bumps

This article reports on a flip-chip bonding technology using an Al bump at high temperatures, such as for SiC semiconductors. In recent years, double-sided mounting structures have been proposed for purposes of miniaturization and low inductance. The surface-mounting method requires durability against high temperatures. We propose a new technique for the flip-chip bonding of an Al bump made from bonding wire. The recrystallization temperature of Al is under 250°C. As a result, there is an expectation of mitigating mechanical stress between the chip and the bonded substrate. We conducted a high-temperature aging test at 250°C for 3,000 h and a thermal shock test between −40°C and 250°C for 3,000 cycles. Results indicate that the shear strength of the Al bump meets the requirements specified in the IEC60749-19 guideline up to 2,000 cycles at room temperature.

Vacuum-based picking-up of thin chip from adhesive tape

The reliable picking-up of thin chip using the vacuum sorption determines the success rate of flip chip assemblies from donor tape to receptor substrate. An analytical solution to model the chip–adhesive–tape structure with vacuum loads is introduced to understand the fracture mechanism of chip picking-up. The critical process parameters (the length of bonded region, vacuum strength, and pick-up displacement, etc.) are investigated. Theoretical predictions are used in combination with virtual crack-closure-based finite-element technique to reveal the detaching behavior between the chip and the adhesive tape. The results show that the length of the bonded region should be controlled less than 40% of chip length to eliminate the effects of chip thickness, and the higher vacuum strength acting on the adhesive tape is able to accelerate the detachment of the chip from the adhesive tape. In particular, a process window is proposed to enhance the reliability and efficiency of picking-up for a thin chip.

Design of Filled One Step Chip Attach Materials (OSCA) for Conventional Mass Reflow Processing: Curing Kinetics and Solder Reflow Aspects

One step chip attach materials (OSCA) are dispensable polymeric materials for flip chip assembly, which are designed to flux metallic interconnections and subsequently turn into an underfill upon curing. OSCA materials enable a drastic simplification of the assembly process by combining the reflow, flux residue cleaning and capillary underfilling steps used in traditional die attach processing into a single step. A key challenge when designing OSCA materials for conventional mass reflow processing (identified as OSCA-R) is timing the cure kinetics with the fluxing and soldering sequences during reflow processing. OSCA-R materials must also have a process-friendly rheological design that integrates seamlessly with standard dispensing equipment and enables the filler loading levels required for customized thermal conductivities. The consideration of the interactions between the filler particles and the organic portion of OSCA materials is critical for first achieving fluxing and interconnection during reflow and second curing the material to develop target thermo mechanical properties for reliability such as Tg, TC, CTE modulus and adhesion after reflow. This paper presents research focused on understanding the impact of filler loading, size, type and surface chemistry on curing, fluxing and interconnection kinetics during reflow processing measured by thermal and rheological methods. Preliminary results indicate the presence of chemical interactions between the filler and organic formulations, as well as complex physical interactions which need to be considered in the design of OSCA-R materials for a device assembly using conventional mass reflow processing.

A Random Stimulation Source for Evaluating MEMS Devices using an Exact Solvable Chaotic Oscillator

MEMS devices are nearly ubiquitous, with applications ranging from automobiles to toys, medical equipment to missiles, and cell phones to industrial equipment. At the microscale, fabrication tolerances are significantly less precise than at the scale of traditional machining techniques. This can result in significant differences in the operating characteristics between otherwise identical MEMS devices. A wide bandwidth random excitation source is ideal for evaluating these components, whether used as the forcing function for an electromechanical shaker employed to measure transmissibility, or as a voltage source to evaluate actuator structure resonances and instabilities. An electronic chaotic oscillator provides an ideal wide bandwidth voltage source which is provably random from first principles and may be simply integrated for the aforementioned MEMS testing. This type of system is easily integrated through standard Si MEMS processes and readily lends itself to application as a built-in-self test (BIST) component. These systems guarantee uniform frequency content from D.C. up to 100kHz due to their characteristically random behavior and serve as a strong candidate for providing uniform spectral density to a device under test. The proposed system is a simple, electronic circuit that creates a random, wideband excitation voltage for observing characteristics of MEMS devices. This functionality is achieved by the analog, digital or mixed signal computation of nonlinear differential equations that describe various exactly solvable chaotic systems. By creating Si microsystems which perform these computations, these test sources may be readily fabricated as integrated BIST components for MEMS devices or fabricated separately and integrated by flip chip assembly techniques. Furthermore, by considering the iterated map of this particular category of stimulation source, a direct and easy measurement of the stimulation entropy may be monitored and corrected. This work begins as a theoretical treatment involving the Nonlinear Dynamics of these types of systems including chaotic systems which permit closed form solutions. These systems are described classically through nonlinear differential equations and intuitively through iterated maps. These techniques reveal inherent methods for entropy measurement in these sources which may be implemented and controlled easily using electronic circuits. Subsequently, the simulation, circuit design methodology, circuit simulation, fabrication, testing and hardware verification of these wideband chaotic sources is presented. The development of this work delineates simple, wideband electronic testing circuits which may be fully integrated with MEMS devices using standard Si MEMS processes. The resulting microsystem may be used as the forcing function when measuring transmissibility of MEMS devices, or as a BIST element to evaluate MEMS microstructure characteristics through direct microelectronic fabrication or flip chip integration.