Thermal stress analysis of the low-k layer in a flip-chip package

Abstract

The structural integrity on low-k layers is a major reliability concern on three-dimensional packaging technology. The low-k material used in dies has a reduced stiffness and adhesion strength to the barrier materials, which makes the back-end-of-line (BEOL) structure much more vulnerable to the externally applied thermal stress during the flip-chip packaging. This thermal stress can cause a serious impact on the reliability and yield of electronic components, and hence the stress optimization is required. This paper aims to create an equivalent thermal stress model to evaluate the stress conditions in different low-k layers generated during the assembly. The model has only one sub-model and is verified by the flip-chip assembly of a 40nm technology node chip. It is shown that this thermal stress model has the potential to predict the stress variation tendency in the different BEOL layers and hence can be used for the chip packaging interaction study.