Flexible Interconnection Network Research Articles

Conditional diagnosability of arrangement graphs under the PMC model

Processor fault diagnosis has played an important role in measuring the reliability of a multiprocessor system, and the diagnosabilities of many well-known multiprocessor systems have been investigated. The conditional diagnosability has been widely accepted as a measure of diagnosability by assuming an additional condition that any fault-set can't contain all the neighbors of any node in a multiprocessor system. This paper considers the conditional diagnosability of an (n,k)-arrangement graph An,k, a flexible interconnection network model for multiprocessor systems, under the classical PMC diagnostic model, and determines that the conditional diagnosability of An,k(k≥2,n≥k+2) is (4k−4)(n−k)−3, which is about four times its traditional diagnosability.

OCEAN, a flexible adaptive Network-On-Chip for dynamic applications

The dynamic and partial reconfiguration of FPGAs enables the dynamic placement of applicatives tasks in reconfigurable zones. However, the dynamic management of the tasks impacts the communications since they are not present in the FPGA during all computation time. So, the task manager should ensure the allocation of each new task and their interconnection which is performed by a flexible interconnection network. In this article, various interconnection networks are studied. Each architecture is evaluated with respect to its suitability for the paradigm of the dynamic and partial reconfiguration in FPGA implementations. This study leads us to propose the OCEAN network that supports the communication constraints into the context of dynamic reconfigurations. Thanks to a generic platform allowing in situ characterizations of network performances, fair comparisons of various Networks-On-Chip can be realized. The FPGA and ASICs implementations of the OCEAN network are also discussed.

Hierarchical Dual-Net: A Flexible Interconnection Network and its Routing Algorithm

In this paper, we propose a flexible interconnection network, called hierarchical dual-net (HDN), with low node degree and short diameter for constructing a large scale of supercomputer. The HDN is constructed based on a symmetric product graph (base network). A k -level hierarchical dual-net, HDN( B,k,S ), contains (2 N 0 ) 2 k /(2 × Π k i =1 s i ) nodes, where S ={ G ' 1 , G ' 2 ,..., G ' k }, G ' i is a super-node and s i = | G' i | is the number of nodes in the super-node at the level i for 1 ≤ i ≤ k , and N 0 is the number of nodes in the base network B . The node degree of HDN( B,k,S ) is d 0 +k , where d 0 is the node degree of the base network. The HDN structure is better than existing networks such as hypercube and 2D/3D torus with respect to the degree and diameter. Another benefit of the HDN is that we can select suitable super-nodes to control the growing speed of the number of nodes for constructing a supercomputer of the desired scale. We investigate the topological properties of the HDN and compare them to that of other networks and give efficient routing and broadcasting algorithms for the hierarchical dual-net.

Scalable Photonic Interconnection Network With Multiple-Layer Configuration for Warehouse-Scale Networks

A scalable and flexible photonic interconnection network architecture suitable for warehouse-scale networks is proposed. The architecture comprises three functional layers: physical, optical, and logical layers. The network topologies achieved at the layers are tree in the physical layer; hypercube in the optical layer; and relatively lower dimensional topologies like two-dimensional mesh, tree, and ring in the logical layer. The application of the appropriate network configuration in each layer by making good use of wavelength division multiplexing technology realizes a truly scalable and flexible network. Evaluation of the physical link requirements reveals the scalability of the proposed network architecture.

Flexible Interconnection Network for Dynamically and Partially Reconfigurable Architectures

The dynamic and partial reconfiguration of FPGAs enables the dynamic placement in reconfigurable zones of the tasks that describe an application. However, the dynamic management of the tasks impacts the communications since tasks are not present in the FPGA during all computation time. So, the task manager should ensure the allocation of each new task and their interconnection which is performed by a flexible interconnection network. In this article, various communication architectures, in particular interconnection networks, are studied. Each architecture is evaluated with respect to its suitability for the paradigm of the dynamic and partial reconfiguration in FPGA implementations. This study leads us to propose the DRAFT network that supports the communication constraints into the context of dynamic reconfiguration. We also present DRAGOON, the automatic generator of networks, which allows to implement and to simulate the DRAFT topology. Finally, DRAFT and the two most popular Networks-on-Chip are implemented in several configurations using DRAGOON, and compared considering real implementation results.

A defect-tolerant reconfigurable nanoarchitecture design for multimedia applications

In this paper, a defect-tolerant reconfigurable multimedia computing architecture for nanotechnologies is proposed. The reconfigurable nanoarchitecture is composed of the array-based function units, the flexible interconnection networks, and the on-chip memories. With these components, the architecture can perform not only 8-, 16-, 32-, and 64-bit simple operations but also some novel operations flexibly. The defect-tolerant reconfigurable nanoarchitecture also incorporates a high communication bandwidth interconnection networks that enables it to easily route around defects, has significant implications for any nanoscale multimedia computations. The kernel component of the reconfigurable computing (RC) engine is the general-purpose processing cluster (GPPC) array, which performs the data-parallelism operations efficiently using the SIMD instructions. For the efficient connectivity, the inter-GPPC-row reconfigurable network is also proposed to achieve the requirements of high flexibility, low complexity, small area, and short network delay. Owing to flexible reconfiguration, multimedia applications can be performed efficiently on the proposed defect-tolerant reconfigurable nanoarchitecture. This is the key to enabling the design of robust nanosystem.

Photonic Combinatorial Network for Contention Management in 160 Gb/s-Interconnection Networks Based on All-Optical 2$\,\times\,$2 Switching Elements

A modular photonic interconnection network based on a combination of basic 2times2 all-optical nodes including a photonic combinatorial network for the packet contention management is presented. The proposed architecture is synchronous, can handle optical time division multiplexed (OTDM) packets up to 160 Gb/s, exhibits self-routing capability, and very low switching latency. In such a scenario, OTDM has to be preferred to wavelength division multiplexing (WDM) because in the former case, the instantaneous packet power carries the information related to only one bit, making the signal processing based on instantaneous nonlinear interactions between packets and control signals more efficient. Moreover, OTDM can be used in interconnection networks without caring about the propagation impairments because of the very short length (<100 m) of the links in these networks. For such short-range networks, the packet synchronization can be solved at the network boundary in the electronic domain without the need of complex optical synchronizers. In this paper, we focus on a photonic combinatorial network able to detect the contentions, and to optically drive the contention resolution block and the switching control block. The implementation of the photonic combinatorial network is based on semiconductor devices, which makes the solution very promising in terms of compactness, stability, and power consumption. This implementation represents the first example of complex photonic combinatorial network for ultrafast digital processing. The network performance has been investigated for bit streams at 10 Gb/s in terms of bit error rate (BER) and contrast ratio. Moreover, the suitability of the 2times2 photonic node architecture exploiting the earlier mentioned combinatorial network has been verified at a bit rate up to 160 Gb/s. In this way, the potential of photonic digital processing for the next generation broad band and flexible interconnection networks has been demonstrated.

A Cost Effective Interconnection Network for Reconfigurable Computing Processor in Digital Signal Processing Applications

In this paper, a novel cost effective interconnection network for two-way pipelined SIMD-based reconfigurable computing processor is proposed. Our reconfigurable computing engine is composed of the SIMD-based function units, flexible interconnection networks, and two-bank on-chip memories. In order to connect the function units, the reconfigurable network is proposed to connect all neighbors of each function unit. The proposed interconnection network is a kind of full and bidirectional connection with the data duplication to perform the data-parallelism applications efficiently. Moreover, it is a multistage network to accomplish the high flexibility and low hardware cost.

A Reconfigurable Computing Processor Core for Multimedia System-on-Chip Applications

In this paper, a reconfigurable computing processor core for multimedia system-on-chip (SOC) applications is proposed. The reconfigurable computing processor comprises two-way single instruction stream multiple data stream (SIMD) based function units, flexible interconnection networks, two instruction caches, and two data caches. Every function units receives the instructions to perform three pipelining stages of operations to increase the throughput rate. With flexible interconnection networks and re-configurability, the reconfigurable computing processor core can not only perform 8-, 16-, 32-, and 64-bit simple operations but also perform some complex operations. In addition, the very large scale integration (VLSI) architecture has been implemented in 0.18 µm complementary metal oxide semiconductor (CMOS) process. Because of these features, the proposed reconfigurable architecture offers a feasible solution for multimedia SOC applications.

Experimental parallel implementation of a wavelet-based still image encoder

A still image encoder implementation is presented for a multi-DSP system called PARNEU, which has previously been developed for neural network and signal processing applications. The core of the implementation is based on experimental mappings of discrete wavelet transform (DWT) on the parallel processor architecture. PARNEU has a flexible interconnection network architecture with message passing, which allows adding more processing units (PUs) to the system whenever more computational power is needed. Program code can be written to adapt to the number of PUs. This is utilized in the presented encoder implementation with emphasis on load balancing among processors as well as on balance between communication and computation. Performance of the implementation is measured with a scaleable number of processors and compared to a sequential reference implementation. Results show that the DWT phase can be efficiently parallelized on PARNEU with 95.6% of its time spent on true parallel computation. The overall speedup with four processors is 2.25, which could be improved by further optimization of an adaptive scanning phase of the encoder.

Architectural factors influencing the reliability of fault-tolerant VLSI arrays

Current trend in VLSI technology is toward highly modular structures in which identical Processing Elements (PE) are connected in a regular lattice. Enhancement of the operational reliability of these VLSI devices is obtained by means of fault-tolerance. Fault-tolerance is achieved incorporating spare PE's into the array and designing a flexible interconnection network which is able to support the reconfiguration of the array in the presence of a fault. This paper discusses how architectural related factors influence the configuration and the technology of the device, and how these factors can be accounted for in a predictive reliability model.