Experimental parallel implementation of a wavelet-based still image encoder

Abstract

A still image encoder implementation is presented for a multi-DSP system called PARNEU, which has previously been developed for neural network and signal processing applications. The core of the implementation is based on experimental mappings of discrete wavelet transform (DWT) on the parallel processor architecture. PARNEU has a flexible interconnection network architecture with message passing, which allows adding more processing units (PUs) to the system whenever more computational power is needed. Program code can be written to adapt to the number of PUs. This is utilized in the presented encoder implementation with emphasis on load balancing among processors as well as on balance between communication and computation. Performance of the implementation is measured with a scaleable number of processors and compared to a sequential reference implementation. Results show that the DWT phase can be efficiently parallelized on PARNEU with 95.6% of its time spent on true parallel computation. The overall speedup with four processors is 2.25, which could be improved by further optimization of an adaptive scanning phase of the encoder.