Flat Package Research Articles

Determination of the Strength of L-Type Corner Joints Obtained from Wood-Based Board Materials Using Different Joining Techniques

Abstract Flat pack (ready-to-assemble, knockdown) furniture has become the most extensive furniture model produced with the development of wood-based board materials technology. It is especially preferred in the building industry as a model suitable for mass production. In this study, the resistances of dowels and screws, which are used in a widespread manner as joining material at the corners of ready-to-assemble furniture, were investigated against tensile and compression resistances in the diagonal direction. Chipboard (CB), medium-density fiberboard, and gaboon mahogany plywood (GMP), 14, 16, and 18 mm thick, were used in this study. Dowel + screw, screw, screw + polyvinyl acetate (PVAc) adhesive, and screw + polyurethane (PUR) adhesive joining were implemented for the L-type corner models obtained from wood-based board materials. According to the results obtained, the highest moment-carrying capacity values in the L-type corner joining were provided in the 18-mm GMP board joined with screw + PVAc adhesive and screw + PUR adhesive for both tests. The joining made without adhesive and the CB materials produced the lowest moment-carrying capacity values.

Reliability Performance of Palladium Coated Copper Wire in High Temperature Bake at Extreme Durations

New automotive requirements expect plastic packages to survive higher operating temperatures with extended thermal duration. Further module integration and more stringent environmental requirements push modules and thus plastic packages closer to the heat source. As such, new mission profiles include more than 3500 total hours at 150°C, or 1000 total hours at 175°C. To satisfy new automotive requirements, plastic packages must meet AEC Grade 0 or higher. Therefore, there is a need to evaluate the wire bond interconnect reliability to 2X AEC Grade 0 to assess the interconnect robustness. Palladium coated copper wire (Pd-Cu) was selected to be the wire of choice on aluminum bond pad for high reliability. Low Profile Quad Flat Pack with Exposed Pad (LQFP-EP) packages wire bonded with 20 micron Pd-Cu wire were submitted to high temperature baking (HTB) at 150°C and 175°C for 4032 and 2016 hours, respectively. This paper will discuss the results of electrical test, package deprocessing and wire pull testing, and cross-sectioning through the ball bonds to examine the welding region. Cu voiding within the bulk of the Cu ball bond, specifically close to the capillary chamfer squeezed region on top of the squashed ball, and at the ball edge interfacing with the intermetallic compound was found predominantly at 175°C bake. A trace of Sulfur was found inside the Cu corroding region. Sulfur compounds in mold compounds were examined. EFO current settings were evaluated in order to reduce the propensity to Sulfur corrosion in the Pd-Cu bond balls. Cu voiding is considered as cosmetic defect as it did not lead to electrical failures even at 2X AEC Grade 0 durations. Pd-Cu wire on aluminum bond pad forms very robust and reliable interconnect in extended thermal aging condition, including 4032 hour HTB-150°C and 2016 hour HTB-175°C, making it suitable for more demanding automotive mission profiles.

Study on reliability of PQFP assembly with lead free solder joints under random vibration test

Harsh solder joint reliability testing is needed for high frequency vibration requirements particularly for automotive electronics. In this study, the solder joint reliability for the plastic quad flat package (PQFP) which was mounted on the printed circuit board (PCB) using 95.5Sn–3.8Ag–0.7Cu lead-free solder was investigated using the random vibration test. A high-speed camera was used to capture dynamic response of the PCB and PQFP lead during the random vibration test. The displacement measurement result was used in finite element analysis (FEA) as an input displacement loading to evaluate the stress–strain behavior of the PQFP lead and solder joint. Fatigue life prediction for the copper (Cu) lead and PQFP solder joint was carried out using three different cycle-counting methods and the Miner's law. It was shown that solder fatigue failure is more critical than Cu lead failure for the PQFP assembly under the random vibration test.

Upscreening of LED COTS for space science applications

An upscreening flow has been defined and applied to COTS LED components. It was made possible by the transparent flat glass packaging of the LED, enabling direct visibility of the assembly up to the epitaxy interface through the transparent sapphire substrate.

자동차 전장품용 무연솔더 접합부의 시리즈 시험 유효성

Abstract Due to environmental regulations (RoHS, WEEE and ELV) of the European Union, electronics and auto-motive electronics have to eliminate toxic substance from electronic devices and system. Specifically, reli-ability issue of lead-free solder joint have an increasing demand for the car electronics caused by ELV banning. The authors prepared engine control unit and cabin electronics soldered with Sn-3.0Ag-0.5Cu (SAC305). To compare with the degradation characteristics of solder joint strength, thermal cycling test (TC), power-thermal cycling test (PTC) and series tests were conducted. Series tests were conducted for TC and PTC combined stress test using the same sample in sequence and continuously. TC test was per-formed at -40~125 ℃ and soak time 10 min for 1000 cycles. PTC test was applied by pulse power and full function conditions during 100 cycles. Combined stress test was tested in accordance with automotive company standard. Solder joint degradation was observed by optical microscopy and environment scanning electron microscopy (ESEM). In addition, to compare with deterioration of bond strength of quad flat pack-age (QFP) and chip components, we have measured lead pull and shear strength. Based on the series test results, consequently, we have validated of series test method for lifetime and reliability of Pb-free solder joint in automotive electronics.Key Words : Pb-free solder, Solder joint, Series reliability, Automotive electronics, DegradationISSN 1225-6153Online ISSN 2287-8955

Micro packaged MEMS pressure sensor for intracranial pressure measurement**Project supported by the National Natural Science Foundation of China (Nos. 61025021, 61434001), and the ‘Thousands Talents’ Program for Pioneer Researchers and Its Innovation Team, China.

This paper presents a micro packaged MEMS pressure sensor for intracranial pressure measurement which belongs to BioMEMS. It can be used in lumbar puncture surgery to measure intracranial pressure. Miniaturization is key for lumbar puncture surgery because the sensor must be small enough to allow it be placed in the reagent chamber of the lumbar puncture needle. The size of the sensor is decided by the size of the sensor chip and package. Our sensor chip is based on silicon piezoresistive effect and the size is 400 × 400 μm2. It is much smaller than the reported polymer intracranial pressure sensors such as liquid crystal polymer sensors. In terms of package, the traditional dual in-line package obviously could not match the size need, the minimal size of recently reported MEMS-based intracranial pressure sensors after packaging is 10 × 10 mm2. In this work, we are the first to introduce a quad flat no-lead package as the package form of piezoresistive intracranial pressure sensors, the whole size of the sensor is minimized to only 3 × 3 mm2. Considering the liquid measurement environment, the sensor is gummed and waterproof performance is tested; the sensitivity of the sensor is 0.9 × 10−2 mV/kPa.

Research on Delamination of Plastic Packaging Device during Reflow Soldering

Due to the application of lead-free solders, the quality and reliability of plastic packaging device are influenced by the increase of reflow temperature. In this paper, a low-profile quad flat package (LQFP) is chosen to illustrate the interface deformation during reflow soldering. The stress analysis theory and the finite element analysis (FEM) simulation are introduced in this paper. By means of finite element software, the distribution of hygrostress, thermal stress and the deformation of device on the printed circuit board (PCB) are analyzed and calculated under different temperature. The relationship between delamination length and deformation is given. The simulation results show that the warping phenomenon is found at the apex angle of the device; delamination is easily produced in the interfaces between different materials by thermal stress, and possibly leads to the device failure.

An Integrated 700–1200-MHz Class-F PA With Tunable Harmonic Terminations in 0.13-$\mu$m CMOS

A fully integrated class-F power amplifier (PA) with reconfigurable harmonic termination over a wide range of frequencies is presented. Reconfigurability is achieved by utilizing on-chip transformers as part of the output matching network. In addition, a stacked transistor architecture was used to boost the output power. The PA was fabricated in a 0.13- μm CMOS process and packaged in a 20-pin quad flat no-leads package. It was configured to operate at 700, 900, and 1200 MHz with a maximum measured saturated output power of +24.6 dBm with a power-added efficiency of 48.3%. The measured gain was 16.5 dB and was flat over the entire bandwidth. The total chip area, including pads, is 1.5 mm × 1.5 mm.

Laser beam scanning system for irradiation in an external quadrangular form for soldering of quad flat package IC

We propose a new soldering process and a system for a quad flat package IC (QFP-IC). The incident line-formed laser beam converted by this system can realize an external quadrangular form line for the non-contact regional heating, to provide thin and light weight electronic packages as required. The laser beam pumped by an yttrium aluminum garnet (YAG) laser oscillator is split into four beams. Using a galvano motor, which can scan the reflection mirror with high frequencies, the laser beam can change the heating line. The soldering time for QFP-IC of 100 pins with the 0.65 mm pitch was 6 s. As the regional heating just only junctions, the temperature in the resin package was lower than 141 °C after solder fusion. From the experimental result, it is confirmed that this method is less damage to a resin package than a conventional whole heating method.

An internal ALD-based high voltage divider and signal circuit for MCP-based photodetectors

We describe a pin-less design for the high voltage (HV) resistive divider of the all-glass LAPPDTM 8in.-square thin photodetector module. The divider, which distributes high voltage applied to the photocathode to the two micro-channel plates (MCPs) that constitute the amplification stage, is comprised of the two MCPs and three glass mechanical spacers, each of which is coated with a resistive layer using atomic layer deposition (ALD). The three glass grid spacers and the two MCPs form a continuous resistive path between cathode and anode, with the voltages across the MCPs and the spacers determined by the resistance of each. High voltage is applied on an external tab on the top glass window that connects to the photocathode through the metal seal. The DC ground is supplied by microstrips on the bottom glass plate that form the high-bandwidth anode. The microstrips exit the package through the glass-frit seal of the anode base-plate and the package sidewall. The divider is thus completely internal, with no HV pins penetrating the low-profile flat glass package. Measurements of the performance of the divider are presented for the 8in.-square MCP and spacer package in a custom test fixture and for an assembled externally pumped LAPPDTM prototype with an aluminum photocathode.

Simulation on Phase Change Thermal Storage Panel Based on Capillary Network

Storage technology has the advantage to solve the problem of the not matching in time and space of energy's supply and demand, making it an effective way to the rational use of resources and reducing environmental pollution. What is used in this paper is a regular flat phase change heat storage module packaging with capillary network and phase change material. In this paper, the software Fluent was used to simulate the impact factors and the ways to enhance heat transfer in the process of phase change. The simulation result indicates that: ▪ During the melting process, because of the influence of natural convection, the top of phase change regional melts faster, the temperature contour ramp to top. ▪ The higher the horizon is, the temperature contour is more stable. ▪ Natural convection play different role in the melting and solidification process, which accelerated melting rate in the melting process, and slowed down in solidification. The surface temperature of phase change thermal storage panel will be maintained at 26.5°C, within the limits of human body comfort and is able to improve the air temperature within a certain space.

Wire sweep improvement study of multi-tier palladium–copper wire bonding on low-quad flat package using low-alpha green mould compound

In this paper, a short-shot mould study is performed on device M in order to understand the mould-filling patterns during mould encapsulation. The wire sweep performance is evaluated for two die thicknesses, wire loop heights and various moulding compounds. Moreover, the actual length of worst swept wire is measured using various methods. Designing of experiment with four factors and three centre points is conducted on device M, which is encapsulated with low-alpha compound. The prediction profiles show that reducing the transfer time will reduce the wire sweep percentage. It is also noteworthy that wire sweep performance is strongly related to wire loop height. In addition, a thicker die gives better wire sweep performance as compared to 7 mils die, whereas decreasing the wire loop height decreases the wire sweep percentage. It can be deduced that optimum compound properties, lower wire loop height and optimum moulding parameters are the essential factors that will improve the wire sweep performance during the mould encapsulation process.

Whisker Formation on SAC305 Soldered Assemblies

This article describes the results of a whisker formation study on SAC305 assemblies, evaluating the effects of lead-frame materials and cleanliness in different environments: low-stress simulated power cycling (50–85°C thermal cycling), thermal shock (–55°C to 85°C), and high temperature/high humidity (85°C/85% RH). Cleaned and contaminated small outline transistors, large leaded quad flat packs (QFP), plastic leaded chip carrier packages, and solder balls with and without rare earth elements (REE) were soldered to custom designed test boards with Sn3Ag0.5Cu (SAC305) solder. After assembly, all the boards were cleaned, and half of them were recontaminated (1.56 µg/cm2 Cl−). Whisker length, diameter, and density were measured. Detailed metallurgical analysis on components before assembly and on solder joints before and after testing was performed. It was found that whiskers grow from solder joint fillets, where the thickness is less than 25 µm, unless REE was present. The influence of lead-frame and solder ball material, microstructure, cleanliness, and environment on whisker characteristics is discussed. This article provides detailed metallurgical observations and select whisker length data obtained during this multiyear testing program.

Full Chip-Package-Board Co-Design of Broadband QFN Bonding Transition Using Backside via and Defected Ground Structure

A complete chip-package-board co-design of bonding transition for a quad flat pack nonlead (QFN) package was conducted from dc to millimeter wave frequencies. First, two ground paths in parallel were used to improve the operating frequency of the commercially available QFN to 50 GHz. Owing to its rectangular cross section, ribbon bond has a better form factor than the corresponding round wire bond with the same dc resistance; it is therefore more effective in impedance matching, and can carry more current at high frequencies. Ribbon bonds were utilized to improve incrementally the frequency performance. Applying the -1.5-dB rule for |S 21 | and the -10-dB rule for |S 11 |, improvements are found to be 1.7 and 3.2 GHz, respectively. Second, QFN frequency performance was significantly improved by using an embedded DGS on the PCB. At 50 GHz, the transition was found to be excessively capacitive. A high-impedance DGS, being inductive itself, was used to compensate for the capacitive nature of the transition. The lumped element approach was taken to provide the background rationale how a DGS on the PCB ground can be adequately used to reduce the capacitive nature of the transition around 50 GHz. Indeed, from simulation at 50 GHz, utilizing the DGS helped to improve the impedance matching, and reduce the insertion loss, further extending the range of operating frequencies. Later, a full wave simulation of the DGS-compensated transition was conducted and the transition was experimentally validated. The full-wave simulated and experimentally obtained results are in good match. From measurements, when the DGS is used, the -1.5-dB rule for |S 21 | and the -10-dB rule for |S 11 | enable the QFN package to achieve the bandwidth up to 62.3 and 66 GHz, respectively.

The effects of wire geometry and wire layout on wire sweep performance using LQFP packages in transfer mold

Transfer molding is the most effective method for molding encapsulation for semiconductor packaging due to low maintenance cost and high production yield. Wire sweep is a critical moldability issue as excessive wire sweep will contact neighbouring wires, causing electrical short that consequently leads to electrical failure of the package. Wire sweep characterization was carried out with various wire locations, mold flow directions, wire lengths, wire pitches and wire angles on Low Quad Flat Packages (LQFP). JMP statistical analysis was performed to determine the significant factors and correlations of wire sweep performance. It was found that wire length has the most significant correlation with wire sweep percentage. The four wires, two at the bottom-left and top-right (and hence designated as corner 2 and 4, respectively) exhibited the worst wire sweep when the mold gate was located at the top-left corner of the package. The wire sweep performance of seven wire layouts with varying wire lengths were also investigated. The results have revealed and proven that the two wires (corner 2 and 4, respectively) exhibited a higher wire sweep percentage. Overall, it was found that wire X4 has the highest wire sweep deflection.

Planar Differential Antenna Design and Integration With Pulse Radar Microchip Sensor

This paper reports the design and integration of a novel planar antenna on FR4 substrate with a system-on-a-chip ultra wideband pulse radar in 90-nm CMOS technology packaged in a 32 pin quad flat no-lead package, allowing the implementation of a short-range pulse radar sensor for biomedical applications. Functional tests have shown that the pulse radar sensor detects three targets with different areas (26 × 26, 13 × 26, and 13 × 13 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ) for front-back movements up to 2 cm around a distance of 70 cm. Field operational tests show that the radar sensor allows the contactless detection of the respiratory rate of the persons under test, be they adult (both genders) and infant, for sub-centimeter chest movements up to a distance of 45 cm from the radar sensor.

Microstructures and fatigue life of SnAgCu solder joints bearing Nano-Al particles in QFP devices

Microstructures and fatigue life of SnAgCu and SnAgCu bearing nano-Al particles in QFP (Quad flat package) devices were investigated, respectively. Results show that the addition of nano-Al particles into SnAgCu solder can refine the microstructures of matrix microstructure. Moreover, the nano-Al particles present in the solder matrix, act as obstacles which can create a back stress, resisting the motion of dislocations. In QFP device, it is found that the addition of nano-Al particles can increase the fatigue life by 32% compared with the SnAgCu solder joints during thermal cycling loading.

Modelling of solid and hollow voussoir FlexiArch systems

This paper investigates the use of solid and hollow core voussoir blocks in an innovative FlexiArch bridge system. The system is formed from precast concrete voussoirs connected by a polymeric reinforcement, enabling the arch to be built and transported as a flat pack and lifted into shape after delivery to site, thus avoiding the use of centring for construction. This research is novel in that it trials and compares the use of hollow core and solid FlexiArch rings in third-scale models with granular backfill. The use of hollow core voussoirs reduces the loading on the polymeric reinforcement during construction and should allow for increased spans. This paper presents the test results of two similar third-scale 5 m × 2 m (span × rise) arch systems, using both solid and hollow construction. The use of hollow core voussoir blocks reduces the weight of the system. Non-linear finite-element analysis (NLFEA) has been used to further compare arch behaviour and the thrustline position.

An Improved Quad Flat Package for High Frequency SiP Applications

This paper describes four cascade coplanar transmission line structures built into the quad flat pack (QFP) lead frame for high-frequency system in package (SiP) applications. Adjacent ground leads are used to provide return paths in a coplanar configuration, thereby minimizing impedance mismatch. Due to the complexity level in QFP structure, full-wave electromagnetic simulations have been performed to extract the S-parameter. Time Domain Reflectometry (TDR) is also used to help in understanding the contributing to the SiP structure. The SiP has also been fabricated and good correlation with electromagnetic simulations is also achieved.

Self-aligned flat ultra-thin chip package for flexible circuits

Purpose – Ultra-thin chip packaging (UTCP) is one of the flexible assembly technologies, by which thinned dies are encapsulated inside spin-coated dielectric films. For sake of higher density integration and bending stress suppression, two UTCPs can be stacked vertically. The purpose of this paper is to present an improved UTCP process flow to embed thinned chip in a symmetric dielectric sandwich for a flat topography. The UTCP flat top surface is suitable for metallization and further 3D stacking. Design/methodology/approach – In the new process, a central photosensitive polyimide film is introduced, in which a cavity is made for the embedded chip. The cavity is defined by lithography using the chip itself as a photo-mask. In this way, the cavity size and position is self-aligned to the chip. The chip thickness is compensated by the surrounding central layer, and a UTCP with flat topography (flat UTCP) is realized after top dielectric deposition. Findings – A batch of daisy chain test vehicles was produced. The feasibility of the process flow is verified by optical and electrical measurements. The result shows 100 percent yield, which is much better than previous work. A thermal humidity test showed no significant degradation of the flat UTCPs after 1,000 hours. Originality/value – High yield fabrication of flat UTCP is first shown. An innovative self-alignment lithography step is introduced to make a cavity in dielectric for chip thickness compensation by using the chip itself as a photo-mask.