Flatband Voltage Shift Research Articles

Photo-induced effects in organic thin film transistors based on dinaphtho [2,3-b:2′,3′-f] Thieno[3,2-b′] thiophene (DNTT)

Abstract We have investigated the photoresponse of organic thin film transistors (OTFTs) based on evaporated films of dinaphtho [2,3-b:2′,3′-f] thieno[3,2-b'] thiophene (DNNT) as the active semiconductor and spin-coated polystyrene as the gate insulator. Both during illumination and in subsequent measurements in the dark after long periods under illumination, transfer characteristics shift to more positive gate voltages. The greatest photoresponse was achieved at 460 nm, near the absorption maximum of DNTT. The maximum photosensitivity and photoresponsivity measured were ∼104 and 1.6 A/W respectively. The latter is the highest reported for an organic semiconductor on a polymeric gate insulator and by suitable adjustments to device geometry could be increased to match the highest reported, ∼105 A/W, for organic semiconductors. Weaker responses were also obtained when exposed to light from the long-wavelength tail in the absorption spectrum. At these longer wavelengths, the response arises entirely from a shift in flatband voltage caused by deep interface trapping of photo-generated electrons. At 460 nm, however, the positive shift, ΔVON, in turn-on voltage is much greater than the shift, ΔVT, in threshold voltage suggesting that ∼3.5 × 1011 electrons/cm2 are trapped at the interface at the start of the gate voltage sweep, but ∼60% are neutralised by holes from the channel as the device begins to turn on. While the resulting change in subthreshold slope could be interpreted as a change in the density of states (DoS) in the DNTT, this is discounted. Gate bias stress measurements made under illumination, reveal that positive bias enhances interface electron trapping while negative bias reduces the effect owing to the simultaneous trapping of holes from the accumulation channel.

Correlation between memory characteristics and energy band bending resulted from composition distribution of trapping layer for charge trap memory

Charge trap memory devices with ZrxSi1–xO2 films as charge trapping layer consisting of nine [(ZrO2)m(SiO2)n(ZrO2)m(SiO2)n] units have been fabricated and investigated. The composition distribution was modulated by controlling the m and n values in each unit. It is observed that the variation of composition distribution can induce the energy band bending and additional potential barrier, which significantly improve the program/erase speed and data retention characteristics as well as extending the temperature insensitive range. When the effective potential barrier including classic potential barrier and additional potential barrier is 1.52 eV, the memory device exhibits a lower charge loss of 4.5% at 200 °C over a period of 104 s, a wider temperature insensitive range of 20 °C–111 °C, and a faster program time of 4.0 × 10−5 s achieving +6 V flat band voltage shift. The effective potential barrier values should be in the range of 1.52–1.36 eV, taking into consideration the trade-off between the retention and program/erase speed. The additional potential barrier can increase the electron tunneling distance in the directions of tunneling layer and blocking layer, giving rise to recapture process and temperature insensitive of retention characteristics. In addition, the additional potential barrier decreases the electron tunneling distance arriving trapping layer conduction band, improving the program speed. The results provide a reference to trapping layer composition distribution for future charge trap memory applications.

Influence of carbon impurities and oxygen vacancies in Al2O3 film on Al2O3/GaN MOS capacitor characteristics

Effects of carbon impurities and oxygen vacancies in Al2O3 film on the characteristics of Al2O3/GaN MOS capacitors were studied using the different atomic layer deposition (ALD) precursor and high-pressure water vapor annealing (HPWVA). Trimethyl aluminum (TMA: Al(CH3)3) and dimethyl aluminum hydride (DMAH: Al(CH3)2H) were used as ALD precursors to control the carbon impurities. On the other hand, oxygen vacancies in Al2O3 film were suppressed using the HPWVA. The DMAH precursor reduced the concentration of carbon impurities in the ALD Al2O3 film. It was found that the interface trap density (Dit) was mainly affected by the carbon impurities rather than the oxygen vacancies at the Al2O3/GaN interface. On the other hand, voltage stress induced flat band voltage (VFB) shift was attributed to both the carbon impurities and the oxygen vacancies.

Bias and related stress effects in organic thin film transistors based on dinaphtho [2,3-b:2′,3′-f] thieno[3,2-b] thiophene (DNTT)

Abstract The effects of bias stress are investigated in organic thin film transistors based on the small molecule dinaphtho [2,3-b:2′,3′-f] thieno[3,2-b]thiophene (DNTT) as the semiconductor and polystyrene as the gate insulator, with measurements carried out over a range of temperature and relative humidity. The threshold voltage always shifted in the direction of the applied gate voltage with the effect decreasing as the drain voltage became more negative. In both linear and saturation regimes, the threshold voltage shift followed a stretched exponential dependence on time. Contrary to most previous reports, the threshold voltage after long stress times, asymptotes to a value well below the applied gate voltage. This suggests that the interface trap density in our devices is lower than in previous reports, placing a limit on the shift in flat-band voltage. Bias stress enhances an underlying shift in threshold voltage already caused by increasing relative humidity although under saturation bias stressing the enhancement is minimal. On increasing temperature, bias stress also increases an underlying shift present in the absence of stressing. Stretched exponential fits to the time-decay of drain current indicate an increasing interface trap concentration as temperature increases, but with a shorter trapping time. In all cases, the density of states in DNTT extracted using the Grunewald approach exhibits similar behaviour. As there is no change in the hole mobility, the weak features appearing at the deeper states are unlikely to be related to DNTT. Rather, as the device turns on and the Fermi level at the semiconductor/insulator interface moves down in the bandgap, the flat-band voltage changes in response to changes in electron/hole occupancy of interface states.

High capacity organic memory structures based on PVP as the insulating layer

The electrical behaviour of organic memory structures based on gold nanoparticles (AuNPs) and poly 4-vinylphenol as the gate dielectric are reported in this work. Metal–insulator–semiconductor (MIS) and thin film transistor structures were used to fabricate the control and memory devices. The drain and source electrodes were fabricated by evaporating 50 nm gold, and the gate electrode was made from 50 nm-evaporated aluminium on a clean glass substrate. Thin films of AuNps embedded within the insulating layer were used as the floating gate. All memory devices exhibited clear hysteresis in their electrical characteristics [capacitance–voltage (C–V) for MIS structures as well as output and transfer characteristics for transistors]. Both structures were shown to produce reliable and large memory windows by virtue of high capacity. The hysteresis in the output and transfer characteristics and shifts in the threshold voltage of the transfer characteristics as well as flat-band voltage shift in the MIS structures were attributed to the charging and discharging of the AuNPs floating gate. Memory window of 38 V was achieved by scanning the applied voltage of the MIS structure between 40 and − 40 V. Similarly, a memory window of 27 V was achieved for the TFT-based memory structure. Under an appropriate gate bias of 1 s pulses, the floating gate is charged and discharged, resulting in significant threshold voltage shifts. Pulses of as low as 5 V resulted in a clear write and erase states.

Colloidal Synthesized Cobalt Nanoparticles for Nonvolatile Memory Device Application

Colloidal synthesized metal nanoparticles (NPs) have great potential to be utilized as economically viable and efficient charge storage floating gate for the non-volatile memory (NVM). Present research work focuses on the NVM device application of colloidal synthesized cobalt (Co) NPs using simple spin coating process. The metal-oxide-semiconductor (MOS) NVM capacitor devices with and without Co-NPs of average size of 5 nm have been fabricated. The MOS NVM and control devices have tunnel oxide (SiO2) thickness of 3.9 nm grown using rapid thermal processing and control dielectric (Al2O3) thickness of 10 nm deposited using atomic layer deposition. Colloidal synthesized Cobalt (Co) NPs deposition over silicon dioxide wafer has been done using optimized spin coating process. Electrical characterization of fabricated devices has been done using proxima B1500 semiconductor device parameter analyzer. Capacitance-voltage (C-V) characteristics of fabricated MOS NVM device shows a large flat band voltage shift ( $\Delta {V}_{{fb}}$ ) of around 8.00 V after applying a sweep voltage of −6 V to +6 V and then +6 V to −6 V in C-V response curves. Where, the control device shows negligible $\Delta {V}_{fb}$ in comparison to MOS NVM device. The program and erase characteristics of the fabricated device have also been studied by Fowler–Nordheim tunneling, resulting in 2.31-V memory window for program/erase pulse of ±5 V. The retention capability has been studied by capacitance versus time (C-t) characteristics. This shows a fairly steady C-t response, indicating strong retention capability of fabricated device.

Fixed Charge Control of Silylated Surface for Stiction-Free Drying with Surface Energy Reduction Process

Recently, a surface energy reduction process (SERP) for stiction-free drying is used for a high aspect pattern structure like shallow trench isolation (STI). The key technology of SERP is trimethylsilyl (TMS) groups termination of the device surface. To explain the electrical influence of TMS groups was found acceptable by measuring the planar capacitor flat-band voltage shift, and the threshold voltage characteristics of 1x-nm node MOS transistors.

Metal work function engineering on epitaxial (100)Ge and (110)Ge metal-oxide-semiconductor devices

Capacitance-voltage characterization of epitaxial n-type (100)Ge and (110)Ge metal-oxide-semiconductor capacitors (MOSCs) was performed using two work function Al and Pt gate metals to evaluate the orientation effect on flat-band voltage (VFB) shift, Fermi level pinning factor (S), and interface induced defects (Dit). These epitaxial (100)Ge/AlAs/GaAs and (110)Ge/AlAs/GaAs heterostructures were grown in-situ using two separate molecular beam epitaxy (MBE) chambers. A VFB shift of >700 mV, S > 0.5, and Dit value of ~ 6 × 1011 cm−2 eV−1 in the energy range of 0.05 eV to 0.3 eV below the conduction band, have been demonstrated from epitaxial n-type (100)Ge and (110)Ge surfaces, which are comparable to the reported bulk Ge MOS-C values, suggesting a robust MOS-C developed process as well as device quality epitaxial (100)Ge and (110)Ge layers on GaAs substrates using an AlAs intermediate buffer. Thus, the metal work function engineering on device-quality MBE grown crystallographically oriented Ge materials, can offer a promising path for extending the performance and application of Ge-based field-effect transistors for low-power devices.

Experimental Extraction of the Charge Centroid of Holes Trapped in Metal–Oxide–Nitride–Oxide–Semiconductor Memories

In metal-oxide-nitride-oxide-silicon (MONOS)-type memories with an ultrathin tunnel oxide film, electrons and holes are injected from the silicon substrate to the silicon nitride charge trapping film owing to the quantum mechanical tunneling and are trapped in the film. In the previous studies, the constant-voltage carrier injection method has been used to determine the charge centroid of trapped carriers [1-4]. This method requires the application of an auxiliary pulse before injecting carriers. To determine the auxiliary pulse level, another set of measurements of the programming and erasing characteristics is needed in preliminary step. Such a sequence would generate an error in the charge centroid estimation due to the variation of the programming and erasing characteristics among individual memory elements. Therefore, we have developed the constant-current carrier injection (CCCI) method which does not require the application of the auxiliary pulse and any additional measurements [5]. The CCCI method is effective to obtain the accurate charge centroid of trapped carriers. On the other hand, these two methods can be used only in the case that the number of carriers passing through the silicon nitride film during the carrier injection is negligible as compared to that of carriers trapped in the nitride film. Therefore, neither of the two methods is usable with high gate voltages which induce a large number of carriers passing through the nitride film. In the present work, in order to obtain the charge centroid of holes trapped in the silicon nitride film at high gate voltages, we proposed a method based on the analysis of Fowler-Nordheim (F-N) tunneling current through the blocking oxide film. We determined the charge centroid and the density of holes trapped at high gate voltages by means of the proposed method and the CCCI method. Memory capacitors with the blocking oxide (SiOx)/silicon nitride/tunnel oxide stacked films were used in this work. A tunnel oxide film of 2.4 nm in thickness was grown by rapid thermal oxidation of silicon. A 30.4-nm-thick silicon nitride film was deposited at 600 °C in an LPCVD reactor. A blocking oxide film of 17.2 nm in thickness was grown at 400 °C using a PECVD method. The thickness of the blocking oxide film was designed to be sufficiently thick for electrons to obey the F-N tunneling mechanism and to gain a high kinetic energy in the oxide film. High-energy electrons entering the nitride film from the blocking oxide film would pass through the nitride film without interaction with nitride trap centers. Figure 1 shows the charge centroid of holes trapped in the nitride film, which was obtained by means of the analysis of F-N current under negative gate bias and the CCCI method. The charge centroid of trapped holes was initially located near the middle of the nitride film, and moved toward the blocking oxide-nitride interface as the flat-band voltage shift ΔVfb,h increased. Finally, the charge centroid reached 2.3 nm from the blocking oxide-nitride interface after the ΔVfb,h value was saturated. We also have estimated the density of trapped holes. A maximum of the density of trapped holes was determined to be 1.0×1013 holes/cm2 by means of the analysis of F-N tunneling current. The proposed method is useful to determine the maximum density of trapped holes which the charge trapping film in MONOS-type memories can achieve. Acknowledgment- We would like to express gratitude to S. R. A. Ahmed, K. Kato and H. Koizumi for their valuable discussions. This work was partly supported by JSPS KAKENHI Grant Number 26420280.

Experimental Extraction of the Charge Centroid of Holes Trapped in Metal–Oxide–Nitride–Oxide–Semiconductor Memories

To obtain the charge centroid of holes trapped in the silicon nitride film in the metal-oxide-nitride-oxide-silicon (MONOS)-type memory, we proposed a method based on the analysis of Fowler-Nordheim (F-N) tunneling current through the blocking oxide film. The charge centroid and the density of holes captured by empty trap centers in the silicon nitride film at high gate voltages were determined by means of the proposed method. The charge centroid of holes trapped in the silicon nitride film moved from the middle of the film toward the blocking oxide-silicon nitride interface as the flat-band voltage shift increased. Finally, the charge centroid reached 2.5 nm from the interface. We also have shown that the density of trapped holes was saturated at 1.0×1013 holes/cm2 after a sufficient number of holes were injected. The proposed method is useful to analyze the charge trapping phenomena in MONOS devices.

Visible-light enhanced charge storage characteristics of amorphous Ni-doped HfO2 films

Photo-induced changes of capacitance–voltage curves for amorphous Ni-doped HfO2 films are probed under different visible light illumination conditions. The illumination-induced minority carriers injection effect enhances the negative shift of flat band voltage, and results in a significant enlargement of memory window. This enlargement exhibits negligible dependence on light wavelength but strong dependence on light intensity in the visible light region. A large memory window width of 6.12 V is obtained under illumination using 650 nm red light with an intensity of 5 mW cm−2. Acceptable endurance and retention properties show potential applications on new-type photosensitive nano-floating-gate nonvolatile memory devices.

Charge Trapping in Al2O3/$\beta$ -Ga2O3-Based MOS Capacitors

Trapping characteristics of MOS structures with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\beta $ </tex-math></inline-formula> -Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> substrates and Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> gate dielectrics are evaluated via constant-voltage stress and X-ray irradiation. Traps that affect bias-induced charging are located primarily in the Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> dielectric layer, and are distributed broadly in time and/or energy. Stress-induced flatband voltage shifts are reduced by N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> annealing. Trap-assisted tunneling is shown to be responsible for the observed gate leakage. Hole trapping in the Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> dielectric layer dominates device radiation response. The relatively modest radiation-induced charge trapping observed in these devices is promising for the potential future use of Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> / <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\beta $ </tex-math></inline-formula> -Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> devices in a space environment.

Graphene quantum dots as charge trap elements for nonvolatile flash memory

In this study, we investigated the charge storage properties of graphene quantum dots (GQDs) by embedding them between poly(methylmethacrylate) (PMMA) sheets as control and tunneling dielectric layers in a silicon metal-oxide-semiconductor-based nonvolatile memory device (Ag-Pd/PMMA/GQDs/PMMA/Si). The conduction mechanism through the gate dielectric stack embedded with GQDs could be explained by Fowler Nordheim (F–N) tunneling. The GQDs trapped electrons to yield a maximum memory window of ∼5.45 V (at ± 7 V) with a low leakage current density. A control experiment without GQDs obtained very low hysteresis (∼7 mV) even when the gate voltage was swept from +8.5 V to –8.5 V. Thus, the memory window obtained in the present study originated from the GQDs and not from the trapped states in the PMMA/Si interface. The maximum charge density was determined as 12.1 × 1011 cm−2, which is comparable to or even better than that found in conventional semiconductor devices. The endurance and charge retention characteristics were examined to assess the reliability of device operation when the devices were put under a constant stress of ±12 V. The flat-band voltage shifts were determined as 0.16 V and 0.23 V during the programming and erasing operations, respectively, and the charge loss was only ∼14.9% even after 105 s, thereby demonstrating the excellent charge confinement property of the GQDs.

Non-volatile memory and negative photoconductivity in a metal-insulator-semiconductor diode with embedded Co nanoparticles

We describe a new metal-insulator-semiconductor (MIS) device in which cobalt based nano particles (NPs) in a core-shell structure (Co–core and Co3O4-shell) are embedded between a thermally grown SiO2 layer and a HfO2 film deposited by atomic layer deposition. Two additional structures were prepared for comparison. One had no NPs and the other included the Fe NPs, prepared using the same procedure as used for the Co film. All devices exhibited the classic behavior of a voltage variable MIS capacitor with or without a large hysteresis as in non-volatile memory (NVM) systems. However, only the device with the Co core-shell structure exhibits a negative photoconductivity (NPC) effect as well as NVM capabilities in both the capacitance-voltage (C-V) and current-voltage (I-V) characteristics. The dependence of C-V and current voltage I-V characteristics on illumination intensity and wavelength (from ultraviolet to near infrared) as well as on temperature was characterized. Illumination enhances the NPC effect as well as the flat-band voltage shift determined from C-V characteristics and hence the memory width. Illumination in the wavelength range of 735–780 nm caused a current decrease, at a given voltage, by up to a factor of two. The NPC effect stimulates an annihilation of the stored charges and therefore erases the system instantly at a small applied bias. The main cause of the NPC effect under illumination is the photo excitation of supplementary trap channels in the Co3O4 shell, which lowers the free carrier density and hence the conductivity of the MIS structure.

Study on NO Passivation on the Near Interface Electron and Hole Traps of n-Type 4H-SiC MOS Capacitors by Ultraviolet Light

The characteristics of near interface electron and hole traps in n-type 4H-SiC MOS capacitors with and without nitric oxide (NO) passivation have been systematically investigated. The hysteresis of the bidirectional capacitance-voltage (C-V) and the shift of flat band voltage (Vfb) caused by bias stress (BS) with and without ultraviolet light (UVL) irradiation are used for studying the influence of near interface electron traps (NIETs) and near interface hole traps (NIHTs). Compared with Ar annealed process, NO passivation can effectively reduce the density of NIETs, but induce excess NIHTs in the SiC MOS devices. What’s worse is that part of the trapped hole cannot be released easily from the NIHTs in the NO annealed sample, which may act as the positive fixed charge and induce the negative shift of threshold voltage.

Radiation Hardness for Silicon Oxide and Aluminum Oxide on 4H-SiC

The radiation hardness of two dielectrics, SiO2 and Al2O3, deposited on low doped, n-type 4H-SiC epitaxial layers has been investigated by exposing MOS structures involving these materials to MeV proton irradiation. The samples are examined by capacitance voltage (CV) measurements and, from the flat band voltage shift, it is concluded that positive charge is induced in the exposed structures detectable for fluence above 1×1011 cm-2. The positive charge increases with proton fluence, but the SiO2/4H-SiC structures are slightly more sensitive, showing that Al2O3 can provide a more radiation hard passivation, or gate dielectric for 4H-SiC devices.

Characterization of bulk traps and interface states in AlGaN/GaN heterostructure under proton irradiation

This paper provides a systematic study on the bulk traps and interface states in a typical AlGaN/GaN Schottky structure under proton irradiation. After 3 MeV proton irradiation with a dose of 5 × 1014 H+/cm2, a positive flat band voltage shift of 0.3 V is observed according to the capacitance-voltage (C-V) measurements. Based on this, the distribution of electrons across AlGaN and GaN layers is extracted. Associated with the numerical calculation, direct experimental evidences demonstrate that the bulk traps within the AlGaN layer dominate the carrier removal effect under proton irradiation. Furthermore, the effects of proton irradiation on AlGaN/GaN interface states were investigated by utilizing the frequency dependent conductance technique. The time constants are extracted, which increase from 1.10–2.53 μs to 3.46–37 μs after irradiation. Meanwhile, it shows that the density of interface states increases from 9.45 × 1011–1.70 × 1013 cm−2·eV−1 to 1.8 × 1012–1.8 × 1013 cm−2·eV−1 with an increase in trap activation energy from 0.34 eV–0.32 eV to 0.41 eV–0.35 eV after irradiation. The Coulomb scattering effect of electron trapping at interface states with deeper energy levels is utilized to explain the mobility degradation in this paper.

Study of γ-ray irradiation influence on TiN/HfO2/Si MOS capacitor by C-V and DLTS

Gamma-ray (γ-ray) irradiation effects on HfO2-based MOS capacitors have been studied. The capacitance-voltage (C-V) characteristic was measured at room temperature (300 K) to study the change of electrical properties in capacitors before and after irradiation with different doses. The shifts of midgap and flatband voltage and the decrease of accumulation capacitance shown that defects in the oxide and interface traps were indeed created during the gamma irradiation. Deep level transient spectroscopy (DLTS) was used to characterize the interfacial states introduced by irradiation. The activation energies, capture cross-sections and interface state densities were EC-0.1697 eV, EC-0.1929 eV; 7.371 × 10−16 cm2, 1.158 × 10−14 cm2; 1.814 × 1013 eV−1 cm2, 5.042 × 1013 eV−1 cm2 for the 1 Mrad(Si) and 5 Mrad(Si) samples, respectively. The peak shifted toward lower temperature when increasing pulse voltages (VP) in measuring DLTS spectra with fixed reverse voltage (VR). It indicated that interface defects have been formed during irradiation. With the increasing of irradiation dose, both of the capture cross section (σn) and the interface state density (Dit) increased. These results provide the basis to the researches and applications for the HfO2-based devices in the field of high-κ materials, irradiation effect, devices in radiation working environment.

Charge trapping properties of Ge nanocrystals grown via solid-state dewetting

In the present work, we report on the charge trapping properties of Germanium Nanocrystals (Ge NCs) self assembled on SiO2 thin layer for promising applications in next-generation non volatile memory by the means of Deep Level Transient Spectroscopy (DLTS) and high frequency C-V method. The Ge NCs were grown via dewetting phenomenon at solid state by Ultra-High Vacuum (UHV) annealing and passivated with silicon before SiO2 capping. The role of the surface passivation is to reduce the electrical defect density at the Ge NCs-SiO2 interface. The presence of the Ge NCs in the oxide of the MOS capacitors strongly affects the C-V characteristics and increases the accumulation capacitance, causes a negative flat band voltage (VFB) shift. The DLTS has been used to study the individual Ge NCs as a single point deep level defect in the oxide. DLTS reveals two main features: the first electron traps around 255 K could correspond to dangling bonds at the Si/SiO2 interface and the second, at high-temperature (>300 K) response, could be originated from minority carrier generation in Ge NCs.

Improvement of Operation Characteristics for MONOS Charge Trapping Flash Memory with SiGe Buried Channel**Supported by the National Science and Technology Major Project of China under Grant No 2013ZX02303007, the National Key Research and Development Program of China under Grant No 2016YFA0301701, and the Youth Innovation Promotion Association of the Chinese Academy of Sciences under Grant No 2016112.

We propose and investigate a novel metal/SiO2/Si3N4/SiO2/SiGe charge trapping flash memory structure (named as MONOS), utilizing SiGe as the buried channel. The fabricated memory device demonstrates excellent program-erasable characteristics attributed to the fact that more carriers are generated by the smaller bandgap of SiGe during program/erase operations. A flat-band voltage shift 2.8 V can be obtained by programming at +11 V for 100 μs. Meanwhile, the memory device exhibits a large memory window of ∼7.17 V under ±12 V sweeping voltage, and a negligible charge loss of 18% after 104 s’ retention. In addition, the leakage current density is lower than 2.52 × 10−7 A·cm−2 below a gate breakdown voltage of 12.5 V. Investigation of leakage current-voltage indicates that the Schottky emission is the predominant conduction mechanisms for leakage current. These desirable characteristics are ascribed to the higher trap density of the Si3N4 charge trapping layer and the better quality of the interface between the SiO2 tunneling layer and the SiGe buried channel. Therefore, the application of the SiGe buried channel is very promising to construct 3D charge trapping NAND flash devices with improved operation characteristics.