Flash Technology Research Articles

Site-specific photocoupling of pBpa mutated scFv antibodies for use in affinity proteomics

Recombinant antibody libraries can provide a source of renewable and high-performing binders tailored for use in affinity proteomics. In this context, the process of generating site-specific 1:1 tagging/functionalization and/or orientated surface immobilization of antibodies has, however, proved to be challenging. Hence, novel ways of generating such engineered antibodies for use in affinity proteomics could have a major impact on array performance. In this study, we have further tailored the design of human recombinant scFv antibodies for site-specific photocoupling through the use of an unnatural amino acid (UAA) and the Dock'n'Flash technology. In more detail, we have generated the 2nd generation of scFvs carrying the photoreactive UAA p-benzoyl-l-phenylalanine (pBpa). Based on key properties, such as expression levels, activity, and affinity, a preferred choice of site for pBpa, located in the beginning of the C-terminal affinity-tag, was for the first time pin-pointed. Further, the results showed that pBpa mutated antibody could be site-specifically photocoupled to free and surface immobilized β-cyclodextrin (an affinity ligand to pBpa). This paves the way for use of scFv antibodies, engineered for site-specific photochemical-based tagging, functionalization, and orientated surface immobilization, in affinity proteomics.

Uniting Gradual and Abrupt set Processes in Resistive Switching Oxides

Oxide-based nonvolatile resistive-switching memories have the potential to close the performance gap between NAND flash and DRAM technologies. This study focuses on the dynamics of the ``SET'' process (switching from the high-resistance to the low-resistance state), unifying the description of gradual and abrupt SET events in the framework of thermal feedback that can result in thermal runaway. In an abrupt event, Joule heating causes positive feedback and a sudden increase in current.

Microscopic Analysis of Erase-Induced Degradation in 40 nm NOR Flash Technology

An in-depth investigation of NOR flash degradation occurring during Fowler–Nordheim (FN) erase operation is provided. After showing how to properly reproduce the flash equivalent stress on transistors, a complete set of delay-free experiments is performed on MOSFET devices. This paper explores FN-induced SiO2 damage from the two oxide interfaces, capturing both electrostatic aging, by reading the drifts of linear characteristics on single MOSFET, and erase efficiency degradation of the memory cell, by measuring the gate current evolution directly on array structures. After showing how to read the signatures of different defects, important insights are given on physical degradation mechanisms and significant guidelines are provided for the extraction of relevant physical-based parameters for modeling and optimization of flash cell endurance. In particular, the power law correlation between injected and trapped charges has been observed for both types of carriers, highlighting the difference in the power exponent which leads to a turnaround of Vth at erase state during flash endurance. It has been underlined how the holes are mainly trapped close to Si/SiO2 interface, essentially influencing the electrostatics, whereas the electrons are mainly located close to poly/SiO2 interface, mostly impacting the gate current. In addition, an accurate noise-free extraction of electrostatic parameters related to holes and amphoteric defects has been performed highlighting the negligible shift of the total threshold voltage. Finally, the interface trap aging kinetics has been experimentally addressed, emphasizing the weak electron-energy dependence.

Cycling-Induced Charge Trapping/Detrapping in Flash Memories—Part I: Experimental Evidence

By using our 16-nm NAND Flash technology as a test vehicle, in this paper, we summarize all the experimental evidence that we have gathered so far on the phenomenology of cycling-induced charge trapping/detrapping in Flash memories. In particular, results from experiments conceived to explore the dependence of charge detrapping on cell memory state reveal that the phenomenon involves more than the simple capture and emission of charge carriers in tunnel-oxide defects. Besides, the thermal activation of charge trapping is highlighted for the first time, along with the detailed dynamics leading to the increase of the trapped charge as cell cycling proceeds. These results allow to lay some cornerstones for the microscopic description of cyclinginduced charge trapping/detrapping in Flash memories. From these cornerstones, in the companion paper (Resnati et al. , 2016), a new physical picture for the trapping/detrapping processes will be proposed and implemented in a statistical model able to reproduce their corresponding threshold-voltage instabilities over array lifetime.

(Invited) Innovation and Challenges of 3-D NAND Flash Technology

NAND Flash has been improved by increasing the bit cost competitiveness and performance and enlarged its range of applications. Especially this cost reduction and performance improvement let the NAND Flash demand be increasing rapidly in the SSD applications. Needs of the market is demanding a high capacity and high speed of the NAND Flash for the information increase and exchange. Needs of these markets could be satisfied by implementation of a continuous scale down and multi bit. But 2D NAND Flash is not only faced with the difficulty of the scale down in a confined space, showing even marginal situations quality and performance secured in accordance with the scale down. 3D NAND Flash was able to break through the limit of the two-dimensional space by the vertical arrangement of cells in three-dimensional space. In this paper, we look at the critical technical elements for the vertical arrangement of 3D NAND Flash Cell and consider innovation and technology challenges of those elements. 3D NAND Flash meets the demand of the high density memory of the market by increasing the cell number per unit area with the increase of vertical stacks. This paper reviews the necessary stack number to meet the needs of the market and considers increasing the difficulty of the pattern formation increase with the high aspect ratio by increasing the stack height. . It also reviews some attempts to overcome the difficulty of the pattern formation for an effective bit cost reduction. 3D NAND Flash is there a big difference in electrical characteristics of 2D NAND Flash. First, we will compare the difference of the main characteristics of 3D NAND Flash and 2D NAND Flash. And we will look at the changes and challenges of the main electrical characteristics depending on the Stack increase for increased bit Cost reduction.

Development and Teaching Application of New Intelligent Courseware in "Sports Economics"

During the development of information technology, the application of multimedia courseware in teaching activities has become a trend of current education. Flash is widely applied in multimedia courseware making by virtue of its advanced technology, good interactivity and easy propagation etc. Based on the above background, this paper designs a new intelligent courseware based on Flash technology through summarizing the researches of domestic and overseas scholars about the application of Flash technology in teaching. Meanwhile, this paper analyzes design thought and major structure of courseware system. On this basis, contrastive teaching experiment and quantitative statistics are applied to demonstrate application effect of this intelligent courseware system in Sports Economics course teaching. The results verify that the new intelligent courseware can greatly improve students’ learning interest, learning initiative and academic performance, and plays a significant helping role in college sports specialty teaching. Besides, it also has strong reference value in teaching other courses.

Chemical state of Ag in Conducting Bridge Random Access Memory cells: a depth resolved X-ray Absorption Spectroscopy investigation.

Conducting Bridge Random Access Memories (CBRAM) are a promising substitute for FLASH technology but problems with limited retention of the low resistance ON state still hamper their massive deployment. Depth resolved X-ray Absorption Spectroscopy has been used to describe the chemical state of the atoms of the active electrode (in this case Ag) and to reveal the role of Sb as stabilizer of the metallic state.

(Invited) Non-Volatile Resistive Memory: Technology Capable of Revolutionary Compromises

Non-Volatile Resistive Memory (NVRM) such as Phase-Change Memory, Oxide-based Memory and Conductive Bridging Memory has rapidly increased in maturity in the last decade. In a memory market context dominated by DRAM and Flash technologies, the evolving memory hierarchy and the strong differentiation of the applications portfolio represent a real opportunity for NVRM to emerge. The real revolution of this technology resides in its versatility made possible by general trade-offs existing between the different NVRM performances, highlighted in the last years by the research and the development in several fields (e.g. materials science, engineering, etc.). We present here some of these trade-offs, and how they can be used to target specific applications.

Performance Enhancement of Metal Floating Gate Memory by Using a Bandgap Engineered High-k Tunneling Barrier

Metal floating gate (FG) memory has been a promising candidate to continue the scaling of NAND flash technology node beyond 1X nm. In this work, metal FG memory device with high-k engineered tunneling layer has been demonstrated. Compared to a single SiO2 tunneling layer, a metal FG memory device based on the OH/OHA tunneling layer exhibits a larger memory window, low operation voltage, faster program/erase speed, and improved data retention. Enhancements of memory performance and reliability are attributed to the high defect state density at the interface of OH/OHA and large physical thickness of tunneling layer by bandgap engineering. The findings provide a guide for future design of metal FG memory.

Analysis of the Retention Characteristic in Three dimensional Junction-less Charge Trapping Memory

To meet the storage requirement of big data, charge trap concept-based three dimensional charge trapping memory (3D-CTM) becomes the main trend of flash technology development. With the multi-layer gate stacking, the equivalent technology node can be scaled down to 10nm without the serious reliability problems from cell-to-cell coupling and SILC-inducing charge loss in conventional flash memory. Specially, the cylindrical junction-less structures such as BICS and TCAT have attracted extensive attention from academia and industry due to their merits of relatively simple procedure and full compatibility with the CMOS process. Moreover, the vertical channel and the ring shape gate stack of memory cell make the 3D memory show superior program/erase performance comparing with the conventional planar flash. However, the shape of charge trap layer is also an important factor affecting the device reliability. The uneven electrical field distribution in tunnel and block layer and the non-separated charge trapping layer of the cylindrical junction-less geometry bring some problems about charge lose in program or erase state. The retention is a critical issue for high density and reliability of 3D integration. In this work, the retention characteristic of 3D cylindrical junction-less charge trapping memory has been investigated. The trapped charge and electron concentration distribution after programming/erasing 10 years have been simulated by sentaurus 3D device simulator. The lateral and vertical charge migrations also have been discussed during the charge losing process. Furthermore, the dominant loss path at the vertical direction has been considered. Figure 1(a) shows schematic birds-eye view of typical 3D-CTM array structure. In order to study the retention properties of 3D vertical memory cell, a string with one cell and two select transistors is used in simulation, as shown in Figure 1(b). Sentaurus 3D device simulator was used for the simulation. The barrier tunneling model contains Fowler–Nordheim tunneling and direct tunneling components, which depends on the energy barrier and band bending calculated self-consistently. From the simulate result of trapped charge at the initial programmed state (initial state) and 10 years after programming state under 85°C condition (10 years state), it can be found that the lateral charge migration happened at 10 years state with respect to the initial state. And the lateral extention distance will be longer if the vertical charge loss is unconsidered. Also,the simulate result shows there is a competition between vertical and lateral charge loss and the vertical charge loss weaken the lateral charge migration during the retention time. Then, the dominant loss path at the vertical direction has been studied. We find that charge loss toward block layer is more serious than tunnel layer. The retention at erase state is also be investigated.Comparing with electron loss, the trapped hole nearly doesn’t loss even after 10 years. This simulation result coincides with the experiment data from Toshiba and Samsung. It’s can be attributed to the larger effective mass and deeper trap energy level of the hole, making it harder to occur tunneling and migration. In this article, retention of 3D cylindrical junction-less CTM has been studied. For the programmed device, lateral charge migration is obvious after 10 years. Vertical charge loss also occurs and lose more seriously toward block layer than tunnel layer. For the erased device, there is nearly no trapped hole loss even after 10 years. This work was supported by the National Natural Science Foundation of China (Grant No. 61474137, No. 61306107, No. 61404168, No. 61404160), China Postdoctoral Science Foundation funded project (No.2014M550866), and the Scientific Research Foundation of CUIT (KYTZ201318, J201404). Figure 1

Compact Modeling of Negative Shift Disturb in NAND Flash Memories

The negative $V_{t}$ shift disturb is one of the new scaling limiters for the NAND Flash technology, since it severely affects the reliability of ultrascaled products, lowering the read margin between the distributions in multilevel cell architectures. However, even if the phenomenon was thoroughly investigated, it lacks a proper model to be exploited for the development of tailored management solutions. In this paper, we have developed a compact model for the negative $V_{t}$ shift disturb simulation in NAND Flash arrays. The model accurately reproduces experimental data retrieved on a 26-nm technology. The application of the model for the fast and accurate statistical assessments of the reliability loss induced by the disturb is shown through the execution of Monte Carlo simulations.

Investigation of tunneling layer and inter-gate-dielectric engineered TaN floating gate memory

ABSTRACTMetal as floating gate (FG) in combination with high-k dielectrics has been seen as a possible solution to continue the scaling of NAND flash technology node beyond 2X nm. In this work, metal FG memory device with high-k engineered Inter-Gate-Dielectric (IGD) and/or tunneling layer (TL) was detailed investigated. It presents improved performance with lower operation voltage as well as faster speed, compared to control samples. Furthermore, improvement of long-term data retention is observed for the high-k engineered devices, proving that the introduction of engineered IGD and/or TL is a promising solution for further performance improvement of full metal FG memory device.

Accurate Estimation Technique of Low Frequency Noise in NAND Flash Cell Array

We propose a technique to accurately estimate low-frequency noise (LFN) of a NAND flash cell. When we measure the LFN of a particular cell in NAND cell array, parasitic resistance and noise due to other cells have high potential to degrade the accuracy of this measurement. We derive small signal equivalent circuit of a NAND flash cell array and then, de-embed the effects of the above parasitic components. We perform this estimation in sub-20-nm NAND flash technology. The results clearly show the necessity of our proposed estimation technique.

Exploiting Process Variation for Write Performance Improvement on NAND Flash Memory Storage Systems

The write performance of flash memory has been degraded significantly due to the recent density-oriented advancements of flash technology. Techniques have been proposed to improve the write performance by exploiting the varying strength of a flash block in its different worn-out stages. A block is written with a faster speed when it is new and strong, and gradually will be written with slower speeds as it is aging and becomes weak. Motivated by these works, this brief proposes a new technique by exploiting the significant process variation among flash blocks introduced by the advanced technology scaling. First, a write speed detection approach is proposed to identify the strength of each block. Then, a heuristic approach is proposed to exploit the speed variation among blocks for write performance improvement. A series of trace-driven simulations shows that the proposed approach generates substantial write performance improvement over state-of-the-art approaches by 30% on average.

Preparation of MoSe2 nano-islands array embedded in a TiO2 matrix for photo-regulated resistive switching memory

The electrically driven resistance change of a material, called memristive switching, is a fascinating phenomenon in the development of next generation nonvolatile memory alternatives to flash technology. Herein, the composite of MoSe2 nano-islands array inserted into TiO2 matrix grown on fluorine-doped tin oxide (FTO) substrate was prepared by anodic aluminum oxide (AAO) template assisted radio frequency magnetron sputtering. Further, a photo-controlled resistive switching memory device with Ag/[MoSe2/TiO2]/FTO structure is demonstrated. The device presents stable resistive switching memory behaviors in dark and under illumination respectively. Finally, the mechanism for the photo-controlled memory behaviors is discussed in detail. This implication provides a foundation for exploring the multifunctional composites and their applications in photo-controlled nonvolatile memory devices.

Multimedia Infographics as Journalistic Narratives and the Possibilities of Html5

The article is a comparative study of multimedia infographic elaborated by the Clarín.com (Argentina) and Folha.com, (Brazil) websites. The objective is to verify and analyze how the two important Latin American mediums of online communication have utilized HTML5 technology and its interactive possibilities in journalistic narrating. The analysis will examine multimedia infographics which have gone through substantial technological changes, altering the format and content of news. In order to understand the narrative possibilities of Flash and HTLM5 technologies for the production of interactive infographics this study will deal with the infographics section related to Folha.com and Especiales Multimedia from Clarin.com. The study, both quantitative and qualitative, verified which narrative and informative resources, tools and Internet programming language technologies were utilized by the two mediums of communication based on the analysis model proposed by Albert Cairo in the book Infografia 2.0.

Enhancing the Reliability of MLC NAND Flash Memory Systems by Read Channel Optimization

NAND flash memory is not only the ubiquitous storage medium in consumer applications but has also started to appear in enterprise storage systems as well. MLC and TLC flash technology made it possible to store multiple bits in the same silicon area as SLC, thus reducing the cost per amount of data stored. However, at current sub-20nm technology nodes, MLC flash devices fail to provide the levels of raw reliability, mainly cycling endurance, that are required by typical enterprise applications. Advanced signal processing and coding schemes are needed to improve the flash bit error rate and thus elevate the device reliability to the desired level. In this article, we report on the use of adaptive voltage thresholds and cell-to-cell interference cancellation in the read operation of NAND flash devices. We discuss how the optimal read voltage thresholds can be determined and assess the benefit of cancelling cell-to-cell interference in terms of cycling endurance, data retention, and resilience to read disturb.

ВИКОРИСТАННЯ FLASH-ТЕХНОЛОГІЙ І JAVA-АПЛЕТІВ В ЕЛЕКТРОННОМУ НАВЧАЛЬНОМУ КУРСІ З ЕЛЕМЕНТАРНОЇ МАТЕМАТИКИ

The article considers way to extend the functionality of LMS Moodle when creating e-learning courses for the mathematical sciences, in particular e-learning courses "Elementary Mathematics" by using flash technology and Java-applets. There are examples of the use of flash-applications and Java-applets in the course "Elementary Mathematics".

MLC NAND Flash memory: Aging effect and chip/channel emulation

This work presents an FPGA-based emulator that can be used for emulating NAND Flash memories, either at the chip or at the channel level, along with the effect of aging on their performance. The emulator is based on a reconfigurable hardware-software architecture, which enables accurate representation of various NAND Flash technologies, focusing especially on MLC cases. The presented architecture can be used for emulating memories at the chip and channel level, while the proposed hardware platform can be used as a valuable tool for developing and evaluating memory-related algorithms and techniques. In this paper, we analyze the architecture of the NAND Flash memory emulator and we present details about its internal functionality. Using experimental results, we demonstrate the high accuracy achieved when it is used to emulate specific MLC and TLC NAND Flash chips and we describe how this custom hardware can be used to emulate a complete NAND Flash channel, which consists of multiple NAND Flash chips that share a common data path and support the execution of pipelined commands.

Impact of the array background pattern on cycling-induced threshold-voltage instabilities in nanoscale NAND Flash memories

This paper highlights that cycling-induced threshold-voltage instabilities in nanoscale NAND Flash technologies display a non-negligible dependence on the background pattern of the memory array during idle/bake periods. Experimental results clearly reveal, in fact, that instabilities in a (victim) cell do not depend only on its memory state, but also on the memory state of its first neighboring (aggressor) cells. The magnitude of this new cell-to-cell interference effect, moreover, appears to depend on the memory state of the victim cell, decreasing with the increase of its threshold-voltage level. From all of the gathered experimental evidence a physical picture explaining the phenomenon is provided, which is, finally, confirmed with the help of numerical simulations.