Microscopic Analysis of Erase-Induced Degradation in 40 nm NOR Flash Technology

Abstract

An in-depth investigation of NOR flash degradation occurring during Fowler–Nordheim (FN) erase operation is provided. After showing how to properly reproduce the flash equivalent stress on transistors, a complete set of delay-free experiments is performed on MOSFET devices. This paper explores FN-induced SiO2 damage from the two oxide interfaces, capturing both electrostatic aging, by reading the drifts of linear characteristics on single MOSFET, and erase efficiency degradation of the memory cell, by measuring the gate current evolution directly on array structures. After showing how to read the signatures of different defects, important insights are given on physical degradation mechanisms and significant guidelines are provided for the extraction of relevant physical-based parameters for modeling and optimization of flash cell endurance. In particular, the power law correlation between injected and trapped charges has been observed for both types of carriers, highlighting the difference in the power exponent which leads to a turnaround of Vth at erase state during flash endurance. It has been underlined how the holes are mainly trapped close to Si/SiO2 interface, essentially influencing the electrostatics, whereas the electrons are mainly located close to poly/SiO2 interface, mostly impacting the gate current. In addition, an accurate noise-free extraction of electrostatic parameters related to holes and amphoteric defects has been performed highlighting the negligible shift of the total threshold voltage. Finally, the interface trap aging kinetics has been experimentally addressed, emphasizing the weak electron-energy dependence.