Design-Technology Co-Optimizations (DTCO) for General-Purpose Computing In-Memory Based on 55nm NOR Flash Technology

Abstract

In this work, based on 55nm NOR flash technology, a general-purpose computing in-memory (CIM) architecture is proposed for the first time. By using a device-aware DTCO approach, a flash-based high-precision partial differential equation (PDE) solver is constructed with the 32-bit floating point (FP) calculation ability. Memory cells (4bit/cell) work at the quasi-saturation region to balance the performances and reliabilities, and the hot hole injection (HHI) is utilized to tune each cell individually (negative Vth shift) in the matrix array, showing ultra-fast operation speed (~10ns) and ultra-low power dissipation. Comprehensive reliability characterizations are also done, including retention, read disturb, random signal noise (RTN) and endurance. It is witnessed that the proposed flash-based 32-bit CIM architecture can conduct high precision calculations with a good tolerance to the cells' fluctuations.