A Vertical 2T NOR (V2T) Architecture to Enable Scaling and Low-Power Solutions for NOR Flash Technology

Abstract

NOR Flash has stopped scaling for many years. However, recently there are increasingly new demands of NOR Flash in various 5G and IoT applications or wearable devices that strongly require new technology advancement of NOR. In this work, we developed a new vertical 2T (V2T) NOR Flash architecture that provides not only scaling capability but also low-power solutions. We leveraged the process of standard 3D NAND to develop a vertical 2T NOR that produces even smaller cell size than conventional planar 1T NOR. Advanced high-K metal-gate (HK/MG) integration is developed to provide high-performance BE-MANOS charge-trapping device with excellent 1M endurance and retention reliability. The 2T NOR architecture provides low-voltage read (~1V) that is compatible with advanced CMOS circuits without charge pumping to save power. We also suggest future technology extensions of the V2T NOR by adopting the ferroelectric memory devices (FeFET) and the 3DIC chiplets integration to broaden the applications fields of NOR technology in embedded Flash and computing in memory (CIM).