Flash Memory Technology Research Articles

An Overview of the Future of Memory Cells: Advances in SSD Technology

This paper explores the topic of Solid-State Drives (SSDs) and NAND flash memory. Information of this paper is mainly obtained from authoritative academic websites and papers related to SSDs and flash memory. Memory cells are fundamental components in various electronic devices. In the field of data storage, SSDs represent the latest generation of storage devices, offering significantly better performance and functionality than traditional hard disk drives (HDDs). NAND flash memory chips are crucial component of SSDs, particularly 3D NAND, which exhibits exceptional performance and holds significant potential for future advancements. This paper will commence by providing an overview of SSDs and HDDs, followed by a comparison between NAND flash and NOR flash, and ultimately analysing the future of NAND flash memory technology employed in SSDs, with a focus on elucidating the advantages of 2D NAND over 3D NAND. Additionally, this paper explains a few challenges that NAND technology faces currently, as well as some possible solutions.

The structure and formation of non-volatile memory cells of Superflash

Split-gate embedded Flash memory technology has been around for decades and has become the standard for a wide range of devices, such as microcontrollers and smart cards. Among the, due to a number of advantages, Silicon Storage Technology Super Flash non-volatile memory technology has become the most widespread. This article presents the results of a study of the memory cells structure, examines in detail the principle of their operation and the main technological stages of the production process of forming transistor structures.

Compliance-free, analog RRAM devices based on SnOx

Brain-inspired resistive random-access memory (RRAM) technology is anticipated to outperform conventional flash memory technology due to its performance, high aerial density, low power consumption, and cost. For RRAM devices, metal oxides are exceedingly investigated as resistive switching (RS) materials. Among different oxides, tin oxide (SnOx) received minimal attention, although it possesses excellent electronic properties. Herein, we demonstrate compliance-free, analog resistive switching behavior with several stable states in Ti/Pt/SnOx/Pt RRAM devices. The compliance-free nature might be due to the high internal resistance of SnOx films. The resistance of the films was modulated by varying Ar/O2 ratio during the sputtering process. The I–V characteristics revealed a well-expressed high resistance state (HRS) and low resistance states (LRS) with bipolar memristive switching mechanism. By varying the pulse amplitude and width, different resistance states have been achieved, indicating the analog switching characteristics of the device. Furthermore, the devices show excellent retention for eleven states over 1000 s with an endurance of > 100 cycles.

An Effective Selection of Memory Technologies for TCAM to Improve the Search Operations: Demonstration of Memory Efficiency in SDN Recovery

Ternary Content-Addressable Memory (TCAM) is used for storing the flow tables in software-defined networking (SDN)-based OpenFlow switches. However, the TCAM can store only a certain number of flow tables (8000). Moreover, when the switch flow tables need to be updated due to the link failure in the SDN, further updates may be lost due to the flow tables limit of the TCAM space. Hence, to resolve this issue, other memories need to be used in conjunction with TCAM to enhance the memory operations of TCAM. When considering which flash memory technology is to be used in conjunction with TCAM, we need to balance several factors to ensure optimal performance, speed, endurance, reliability, integration complexity, and cost-effectiveness. Hence, it leads to a multi-criteria decision-making problem regarding the selection of other memory technologies such as 3D XPoint, Magnetoresistive RAM, Resistive RAM, and Ferroelectric RAM. In this paper, we use the analytical network process (ANP) method to select the suitable technology in conjunction with TCAM, considering the features of the memory technologies for Software-Defined Internet-of-Things (SD-IoT). We provide a comprehensive numerical model leveraging the ANP to rank the memory technologies regarding their weights. The highest weights identify the most suitable technology for TCAM. We perform simulations to show the effectiveness of the mathematical model utilizing the ANP. The results show that the suggested methodology reduces the recovery delay, improves the packets received ratio (PRR), decreases the jitter, and increases the throughput.

Flash Memory Technology for Space Application - An Approach

Recently, flash memory technology has been considered for space application. This paper provides an approach for induction of the flash memory based mass data storage system to space program. It also, provides the studies and experiments that have been carried out in recent past to understand and characterize the behavior of flash memory in space environment. Further, it provides the design aspects which need to be addressed when dealing with flash memory for space environment, as identified by domain experts

Emerging Memory Devices Beyond Conventional Data Storage: Paving the Path for Energy-Efficient Brain-Inspired Computing

The current state of neuromorphic computing broadly encompasses domain-specific computing architectures designed to accelerate machine learning (ML) and artificial intelligence (AI) algorithms. As is well known, AI/ML algorithms are limited by memory bandwidth. Novel computing architectures are necessary to overcome this limitation. There are several options that are currently under investigation using both mature and emerging memory technologies. For example, mature memory technologies such as high-bandwidth memories (HBMs) are integrated with logic units on the same die to bring memory closer to the computing units. There are also research efforts where in-memory computing architectures have been implemented using DRAMs or flash memory technologies. However, DRAMs suffer from scaling limitations, while flash memory devices suffer from endurance issues. Additionally, in spite of this significant progress, the massive energy consumption needed in neuromorphic processors while meeting the required training and inferencing performance for AI/ML algorithms for future applications needs to be addressed. On the AI/ML algorithm side, there are several pending issues such as life-long learning, explainability, context-based decision making, multimodal association of data, adaptation to address personalized responses, and resiliency. These unresolved challenges in AI/ML have led researchers to explore brain-inspired computing architectures and paradigms.

Applications and mechanisms of anisotropic two-step Si3N4 etching with hydrogen plasma conditioning

The ability to precisely form Si3N4 spacers is critical to the success of dynamic random-access memory and NAND (NOT AND) flash memory technology development. In this study, we investigated the mechanisms and process windows of an innovative two-step nitride (Si3N4) etch consisting of H2 plasma processing in an inductively coupled plasma chamber followed by either buffered oxide etch (BOE, a mix of NH4F and HF solution) wet clean or in situ NF3 plasma etch. We obtained layer–by-layer removal with each layer’s removal capable of more than 10 nm. We revealed that H can penetrate more than 20 nm deep into the nitride film to transform pristine Si3N4 into SiON after air exposure, which can be subsequently removed by BOE wet clean. The H2 and BOE steps do not need to run back-to-back; the modified SiON layer is stable enough to sustain elevated temperature processing and can be removed by BOE later down-the-line integration. We also demonstrated that using NF3 plasma can have highly selective etch of nitride over oxide due to the incubation time difference between these two types of films. It takes much longer time to initiate the chemical reaction for oxide compared with nitride. Critically, the role of H2 is not the key for high selectivity; instead, it provides an etch directionality and shortens the incubation time for both nitride and oxide.

FLIXR: Embedding Index Into Flash Translation Layer in SSDs

Flash memory technologies rely on flash translation layer (FTL) to manage no in-place update and garbage collection. Current FTL management schemes do not exploit the semantics of the accessed data. In this paper, we explore how semantic knowledge can be exploited to build and maintain indexes for stored data automatically. Data indexing is a critical enabler to accelerate many database applications and big data analytics. Unlike traditional per-table or per-file indexes that are managed separately from the data, we propose to maintain indexes on a per-flash page basis. Our approach, called FLash IndeXeR (FLIXR), builds and maintains page-level indexes whenever a page is written into the flash. FLIXR updates the indexes alongside any data updates at page granularity. The cost of the index update is hidden in the page write delays. FLIXR stores index data for each page within the FTL entry associated with that page, thereby piggybacking index access on a page access request. FLIXR accesses the index data in each FTL entry to determine whether the associated page stores data with a given key. FLIXR achieves 52.6% performance improvement for TPC-C and TPC-H benchmarks, compared to the conventional host-side indexing mechanism.

A Novel Encrypted Computing-in-Memory (eCIM) by Implementing Random Telegraph Noise (RTN) as Keys Based on 55 nm NOR Flash Technology

A novel encrypted Computing-in-Memory (eCIM) architecture is proposed based on 55nm NOR Flash memory technology, wherein the current fluctuations caused by random telegraph noise (RTN) in flash cells are utilized as the intrinsic encryption source. Furthermore, aiming at the low-power consumption with high bit-density, the near-subthreshold region of the flash cell is used for 2-bit/cell operation. It is demonstrated that, in the designed 32-bit floating-point (FP) calculation architecture, ultra-low power dissipation (0.24 pJ/bit) can be achieved with high calculation accuracies after the decryption.

A novel SSD fault detection method using GRU-based Sparse Auto-Encoder for dimensionality reduction

In recent years, with the development of flash memory technology, storage systems in large data centers are typically built upon thousands or even millions of solid-state drives (SSDs). Therefore, the failure of SSDs is inevitable. An SSD failure may cause unrecoverable data loss or unavailable system service, resulting in catastrophic results. Active fault detection technologies are able to detect device problems in advance, so it is gaining popularity. Recent trends have turned toward applying AI algorithms based on SSD SMART data for fault detection. However, SMART data of new SSDs contains a large number of features, and the high dimension of data features results in poor accuracy of AI algorithms for fault detection. To tackle the above problems, we improve the structure of traditional Auto-Encoder (AE) based on GRU and propose an SSD fault detection method – GAL based on dimensionality reduction with Gated Recurrent Unit (GRU) sparse autoencoder (GRUAE) by combining the temporal characteristics of SSD SMART data. The proposed method trains the GRUAE model with SSD SMART data firstly, and then adopts the encoder of GRUAE model as the dimensionality reduction tool to reduce the original high-dimensional SSD SMART data, aiming at reducing the influence of noise features in original SSD SAMRT data and highlight the features more relevant to data characteristics to improve the accuracy of fault detection. Finally, LSTM is adopted for fault detection with low-dimensional SSD SMART data. Experimental results on real SSD dataset from Alibaba show that the fault detection accuracy of various AI algorithms can be improved by varying degrees after dimensionality reduction with the proposed method, and GAL performs best among all methods.

Analysis of Residual Stresses Induced in the Confined 3D NAND Flash Memory Structure for Process Optimization

In flash memory technology, mechanical stress is considered as one of the major factors that can influence the device performance. Furthermore, mechanical stress can have a greater impact on the electrical performance in 3D NAND than in 2D NAND because 3D NAND has a confined structure. Thus, the mechanical stress and its influence on the 3D NAND need to be investigated. In this study, we simulated the 3D NAND flash to quantify how deposition temperatures of components influenced residual stress and electrical characteristics. The stress distribution and electrical characteristics of the channel were shown to depend on the deposition temperatures of the poly-Si channel, charge trap nitride, tunneling oxide, and tungsten word line in technology computer-aided design simulations. Also, the relationship between residual stress and electrical characteristics was investigated and described using the energy band shift due to residual stress. These results have a potential to improve the cell performances and optimize process parameters in 3D NAND flash process technology.

The Fundamentals of NAND Flash Memory: Technology for tomorrow’s fourth industrial revolution

With the rise of the mobile-centric era, data-driven applications such as the Internet of Things, artificial intelligence, cloud computing, blockchain, and so on are ever increasing. As these applications create unprecedented amounts of data, the technologies used for collecting, processing, and storing them well are becoming more crucial. According to the research in <xref ref-type="bibr" rid="ref1">[1]</xref>, the amount of data we generate has a growth rate of 2.5 times per every four years, and the total amount of data will reach 175 ZB by 2025. Such a &#x201C;Big Bang&#x201D; of data means a tremendous demand on storage systems; it is evident that high-capacity and high-performance storage systems will play a key role. Therefore, along with this trend, NAND flash memory technology has continued to evolve to meet high demands. This article covers key technologies for high-density/high-performance NAND flash memory.

Address Pattern Recognition Flash Translation Layer for Quadruple-level cell NAND-based Smart Devices

The price of the solid-state drives has become a major factor in the development of flash memory technology. Major semiconductor companies are developing quadruple-level cell NAND-based SSDs for smart devices. Unfortunately, SSDs composed of quadruple-level cell (QLC) flash memory may suffer from low performance. In addition, few studies on internal page buffering mechanisms have been conducted. As a solution to these problems, an address pattern recognition flash translation layer (APR-FTL) is proposed in this study. APRA-FTL gathers the data in a page unit and separates random data from sequential data. Furthermore, APRA-FTL proposes address mapping algorithm which is compatible to the page buffering algorithm. Experimental results show that APRA-FTL generates a lower number of write and erase operations compared to previous FTL algorithms.

Technique for Profiling the Cycling-Induced Oxide Trapped Charge in NAND Flash Memories

NAND Flash memories have gained tremendous attention owing to the increasing demand for storage capacity. This implies that NAND cells need to scale continuously to maintain the pace of technological evolution. Even though NAND Flash memory technology has evolved from a traditional 2D concept toward a 3D structure, the traditional reliability problems related to the tunnel oxide continue to persist. In this paper, we review several recent techniques for separating the effects of the oxide charge and tunneling current flow on the endurance characteristics, particularly the transconductance reduction (ΔGm,max) statistics. A detailed analysis allows us to obtain a model based on physical measurements that captures the main features of various endurance testing procedures. The investigated phenomena and results could be useful for the development of both conventional and emerging NAND Flash memories.

Gate All around with Back Gate NAND Flash Structure for Excellent Reliability Characteristics in Program Operation

A gate all around with back-gate (GAAB) structure was proposed for 3D NAND Flash memory technology. We demonstrated the excellent characteristics of the GAAB NAND structure, especially in the self-boosting operation. Channel potential of GAAB shows a gradual slope compared with a conventional GAA NAND structure, which leads to excellent reliability characteristics in program disturbance, pass disturbance and oxide break down issue. As a result, the GAAB structure is expected to be appropriate for a high stacking structure of future memory structure.

Graphene Photo Memtransistor Based on CMOS Flash Memory Technology with Neuromorphic Applications

Graphene holds a great promise for a number of diverse future applications, in particular related to its easily tunable doping and Fermi level by electrostatic gating. However, as of today, most implementations rely on electrical doping via the application of continuous large voltages to maintain the desired doping. We show here how graphene can be implemented with conventional semiconductor flash memory technology in order to make programmable doping possible, simply by the application of short gate pulses. We also demonstrate how this approach can be used for a memory device, and also show potential neuromorphic capabilities of the device. Finally, we show that the overall performance can be significantly enhanced by illuminating the device with UV radiation. Our approach may pave the way for integrating graphene in CMOS technology memory applications, and our device design could also be suitable for large scale neuromorphic computing structures.

Self-Heating Effects in 3-D Vertical-NAND (V-NAND) Flash Memory

Self-heating effects (SHEs) were investigated through simulations for 3-D V- NAND flash memory. The SHEs are varied by adjusting the thickness of the poly-crystalline channel, the number of stacked cells along with a bitline, and the configuration of the multilevel cell. The simulation data show that the temperature change was smaller than 3 K under read operation; therefore, SHEs are no longer a concern for advances in 3-D V- NAND flash memory technology. In addition, we investigated whether SHEs are influenced by a thermally isolated channel, as in a novel architecture named peripheral-under-cell (PUC), which is a peripheral circuit under cell for 3-D V- NAND flash memory.

A Management Scheme of Multi-Level Retention-Time Queues for Improving the Endurance of Flash-Memory Storage Devices

As flash memory technology has been scaled down to 1x nm and more bits can be stored in a cell, the storage density of flash memory has been significantly improved. However, these technical trends also severely hurt the programming speed and endurance of flash memory. The internal data retention time is the duration for which a flash cell can correctly hold data. By relaxing internal data retention time, both the page programming speed and the block endurance could be improved. However, the retention time of flash memory typically requires to last for several years according to the industrial standard. Thus a refreshment scheme is required to deal with the decreasing of retention time. In this article, we propose multi-level retention-time queues with a management scheme to meet the retention-time requirement for a reliable storage system. Observing that many data are overwritten in hours or days in real workloads, multiple retention-time queues could effectively separate data with different update frequencies. There are three challenge issues for a proper design: (1) Since access pattern might change from time to time, a technical issue is how to promote/demote data so that data could be maintained in the proper retention-time queue to minimize the refreshment overhead. (2) Another technical issue is how to refresh each retention-time queue in time to guarantee data integrity. (3) Since blocks resided in different retention-time queue would suffer from different level of wearing, the third technical issue is how to estimate wearing status of flash-memory blocks in an effective and efficient manner to achieve wear leveling. In our scheme, data allocator, multi-level refresh module, garbage collector, and wear leveler are introduced to deal with these technical issues. Based on our experimental results, not only endurance and performance but also energy consumption of the flash-memory storage system could be significantly improved by our scheme.

WAL-SSD: Address Remapping-Based Write-Ahead-Logging Solid-State Disks

Recent advances in flash memory technology have reduced the cost-per-bit of flash storage devices such as solid-state drives (SSDs), thereby enabling the development of large-capacity SSDs for enterprise-scale storage. However, two major concerns arise in designing SSDs. First, the size of the address mapping table is increasing in proportion to the capacity of the SSD. The SSD-internal firmware, called flash translation layer (FTL), must maintain the address mapping table in the internal DRAM. Although the previously proposed demand map loading technique uses a small size of cached map table, the technique aggravates poor random performance. Second, there are many redundant writes in storage workloads, which have an adverse effect on the performance and lifetime of the SSD. For example, many transaction-supporting applications use the write-ahead-log (WAL) scheme, which writes the same data twice. To resolve these problems, we propose a novel transaction-supporting SSD, called WAL-SSD, which logs transaction data at the internally-managed WAL area and relocates the data atomically via the FTL-level remap operation at the transaction checkpointing. It can also be used to transform random write requests to sequential requests. We implemented a prototype of WAL-SSD with a real SSD device. Experiments demonstrate the performance improvement by WAL-SSD with three use cases: remap-journaling, atomic multi-block update, and random write logging.

Improving Utilization and Life-Span in Parallel Aware MLC-Based SSD Using Virtual Blocks

FTL (Flash Translation Layer) is a memory block controller that manages the challenges of a data storage system based on flash memory technology. The design of internal parallelism in MLC-based SSDs with virtual blocks resulted in various challenges and due to the physical structure of flash memory cells based on MLC technology, it is possible to write a new page in a data block at the address after the last page is written. In parallel-based SSD design based on virtual blocks, some writes create unusable pages at the memory space, and these created holes reduce memory efficiency; consequently, it reduces the life-time of memory blocks by creating more operations, and accelerates garbage collection and merging operations. The proposed FTL offers three steps to address this constraint. Firstly, an idea was proposed to prevent costly transitions and to distribute data more evenly at memory blocks (wear leveling). Secondly, the unused holes created in virtual blocks became much fewer resulting in increased utilization of memory space. At last, a policy was proposed to prevent update blocks (log blocks) from being blocked and to postpone the merging and garbage collection by which the memory lifetime increases significantly. Simulation results showed that the number of unused erased pages and the number of extra write operations decreased up to 23% and 17%, respectively. In addition, the number of invalid released pages increased up to 21% in the proposed FTL, and the speed of I/O executions to 3%.