Flash Memory Chips Research Articles

An Overview of the Future of Memory Cells: Advances in SSD Technology

This paper explores the topic of Solid-State Drives (SSDs) and NAND flash memory. Information of this paper is mainly obtained from authoritative academic websites and papers related to SSDs and flash memory. Memory cells are fundamental components in various electronic devices. In the field of data storage, SSDs represent the latest generation of storage devices, offering significantly better performance and functionality than traditional hard disk drives (HDDs). NAND flash memory chips are crucial component of SSDs, particularly 3D NAND, which exhibits exceptional performance and holds significant potential for future advancements. This paper will commence by providing an overview of SSDs and HDDs, followed by a comparison between NAND flash and NOR flash, and ultimately analysing the future of NAND flash memory technology employed in SSDs, with a focus on elucidating the advantages of 2D NAND over 3D NAND. Additionally, this paper explains a few challenges that NAND technology faces currently, as well as some possible solutions.

Neural Network-Based prediction for Cross-Temperature induced VT distribution shift in 3D NAND flash memory

In this study, a neural network (NN) was proposed for predicting the VT characteristics of NAND flash memories under cross-temperature conditions. The training data were obtained from commercial NAND flash memory chip measurements at various temperatures. The VT distribution shift caused by cross-temperature was accurately predicted by investigating the optimum data dimensions while minimizing the data generation process. Two types of NNs were used to achieve an accurate VT distribution prediction, and each network was optimized using specific parameters based on the data characteristics at various program verify levels. Finally, quantitative and visual evaluations were conducted to verify the performance of the trained NNs. When the program-measured temperature varied from low to high, the NNs achieved mean errors of 1.87%, 1.41% at low and 0.34%, 0.77% at high for the average and width of the VT distribution, respectively. Similarly, when the temperature varied from high to low, the corresponding mean errors were 2.01%, 0.74% at high and 0.23%, 1.59% at low. These findings demonstrate that NNs can minimize the procedures for detecting the VT distribution shift caused by cross-temperature, thereby offering a promising approach to enhance reliability in the presence of such effects.

Performance Analysis of Concatenated Coding to Increase the Endurance of Multilevel NAND Flash Memory

The increasing storage density of modern NAND flash memory chips, achieved both due to scaling down the cell size, and due to the increasing number of used cell states, leads to a decrease in data storage reliability, namely, error probability, endurance (number of P/E cycling) and retention time. Error correction codes are often used to improve the reliability of data storage in multilevel flash memory. The effectiveness of using error correction codes is largely determined by the model accuracy that exhibits the basic processes associated with writing and reading data. The paper describes the main sources of disturbances for a flash cell that affect the threshold voltage of the cell in NAND flash memory, and represents an explicit form of the threshold voltage distribution. As an approximation of the obtained threshold voltage distribution, a Normal-Laplace mixture model was shown to be a good fit in multilevel flash memories for a large number of rewriting cycles. For this model, a performance analysis of the concatenated coding scheme with an outer Reed-Solomon code and an inner multilevel code consisting of binary component codes is carried out. The performed analysis makes it possible to obtain tradeoffs between the error probability, storage density, and the number of P/E cycling. The resulting tradeoffs show that the considered concatenated coding schemes allow, due to a very slight decrease in the storage density, to increase the number of P/E cycling up to 2–2.5 times than their nominal endurance specification while maintaining the required value of the bit error probability.

Non-volatile resistive switching mechanism in single-layer MoS2 memristors: insights from ab initio modelling of Au and MoS2 interfaces.

Non-volatile memristive devices based on two-dimensional (2D) layered materials provide an attractive alternative to conventional flash memory chips. Single-layer semiconductors, such as monolayer molybdenum disulphide (ML-MoS2), enable the aggressive downscaling of devices towards greater system integration density. The "atomristor", the most compact device to date, has been shown to undergo a resistive switching between its high-resistance (HRS) and low-resistance (LRS) states of several orders of magnitude. The main hypothesis behind its working mechanism relies on the migration of sulphur vacancies in the proximity of the metal contact during device operation, thus inducing the variation of the Schottky barrier at the metal-semiconductor interface. However, the interface physics is not yet fully understood: other hypotheses were proposed, involving the migration of metal atoms from the electrode. In this work, we aim to elucidate the mechanism of the resistive switching in the atomristor. We carry out density functional theory (DFT) simulations on model Au and ML-MoS2 interfaces with and without the presence of point defects, either vacancies or substitutions. To construct realistic interfaces, we combine DFT with Green's function surface simulations. Our findings reveal that it is not the mere presence of S vacancies but rather the migration of Au atoms from the electrode to MoS2 that modulate the interface barrier. Indeed, Au atoms act as conductive "bridges", thus facilitating the flow of charge between the two materials.

Research on Improvement of Static Power Consumption of 90nm Embedded Flash Memory Chip

Research on Improvement of Static Power Consumption of 90nm Embedded Flash Memory Chip

A shared page-aware machine learning assisted method for predicting and improving multi-level cell NAND flash memory life expectancy

NAND flash memory is widely used in consumer electronics, personal computers, and enterprise data storage servers. The most prevalent source of flash memory errors is retention errors, which are mainly caused by leakage of charges. It has been observed that inside the chip, some flash memory blocks exhibit greater endurance to the retention errors than others. In an effort to prolong life expectancy, previous studies focus on improving the Raw Bit Error Rate (RBER) metric at page and block levels, without due consideration of the geometry of shared pages. In this paper, the first insight we provide is that groups of shared pages have different RBER values, and should be analyzed separately. We use this insight to construct a machine learning model to predict the blocks which have less endurance, using the characterization data of new unused flash memory chip(s). This is accomplished by extracting location-sensitive and value-sensitive features from the shared pages group, and engineering them into more sophisticated and explainable features. Furthermore, we describe how our proposed prediction model can be used in combination with the existing flash translation layer (FTL) wear-leveling algorithm to increase lifetime. We evaluated the proposed prediction and lifetime improvement method for four different machine learning techniques, among which Support Vector Machine (SVM) achieved superior accuracy up to 85% at a lower computational overhead.

Implementation and characterization of flash‐based hardware security primitives for cryptographic key generation

AbstractHardware security primitives, also known as physical unclonable functions (PUFs), perform innovative roles to extract the randomness unique to specific hardware. This paper proposes a novel hardware security primitive using a commercial off‐the‐shelf flash memory chip that is an intrinsic part of most commercial Internet of Things (IoT) devices. First, we define a hardware security source model to describe a hardware‐based fixed random bit generator for use in security applications, such as cryptographic key generation. Then, we propose a hardware security primitive with flash memory by exploiting the variability of tunneling electrons in the floating gate. In accordance with the requirements for robustness against the environment, timing variations, and random errors, we developed an adaptive extraction algorithm for the flash PUF. Experimental results show that the proposed flash PUF successfully generates a fixed random response, where the uniqueness is 49.1%, steadiness is 3.8%, uniformity is 50.2%, and min‐entropy per bit is 0.87. Thus, our approach can be applied to security applications with reliability and satisfy high‐entropy requirements, such as cryptographic key generation for IoT devices.

New Total-Ionizing-Dose Resistant Data Storing Technique for NAND Flash Memory

This paper describes a new non-charge-based data storing technique in NAND flash memory called watermark that encodes read-only data in the form of physical properties of flash memory cells. Unlike traditional charge-based data storing method in flash memory, the proposed technique is resistant to total ionizing dose (TID) effects. To evaluate its resistance to irradiation effects, we analyze data stored in several commercial single-level-cell (SLC) flash memory chips from different vendors and technology nodes. These chips are irradiated using a Co-60 gamma-ray source array for up to 100 krad(Si) at Sandia National Laboratories. Experimental evaluation performed on a flash chip from Samsung shows that the intrinsic bit error rate (BER) of watermark increases from <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mathbf {\sim }0.8$ </tex-math></inline-formula> % for TID = 0 krad(Si) to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mathbf {\mathrm {\sim }}1$ </tex-math></inline-formula> % for TID = 100 krad(Si). Conversely, the BER of charge-based data stored on the same chip increases from 0% at TID = 0 krad(Si) to 1.5% at TID = 100 krad(Si). The results imply that the proposed technique may potentially offer significant improvements in data integrity relative to traditional charge-based data storage for very high radiation (TID <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mathbf { &gt; } 100$ </tex-math></inline-formula> krad(Si)) environments. These gains in data integrity relative to the charge-based data storage are useful in radiation-prone environments, but they come at the cost of increased write times and higher BERs before irradiation.

Energy-Aware Adaptive Multi-Exit Neural Network Inference Implementation for a Millimeter-Scale Sensing System

Implementing a neural network (NN) inference in a millimeter-scale system is challenging due to limited energy and storage size. This article proposes an energy-aware adaptive NN inference implementation that utilizes one of two exits with different accuracies and computation options. The early-exit path provides a shorter processing time but less accuracy than the main-exit path. To compensate for the reduced accuracy, it additionally applies the main-exit path if the entropy of the early-exit inference is higher than a predetermined value. The NN is implemented with a custom low-power 180-nm CMOS processor chip and a 90-nm embedded flash memory chip and tested by the CIFAR-10 dataset. The measurement results show that the implemented convolutional NN (CNN) reduces processing time and thus energy consumption by 43.9% compared with a main-exit-only method while sacrificing its accuracy from 69.9% to 66.2%. Also, we explore the required minimum battery capacity at each optimal configuration for accuracy and/or energy consumption to achieve energy-autonomous operation under measured exemplary light profiles. It requires a minimum battery capacity of 855 mJ, acceptable for the target miniature system with two millimeter-scale batteries (684 mJ each). Compared with the state-of-the-art CNN technique (BranchyNet) allowing early stopping, the proposed design improves the accuracy by 0.7% and 3.3% to maintain energy-autonomous operation with two and one millimeter-scale batteries, respectively. Compared with the state-of-the-art lightweight CNN technique (MobileNet), this work provides flexibility with a tradeoff between accuracy and processing time for different application requirements.

ОПТИМИЗАЦИЯ ВРЕМЕНИ ТЕСТИРОВАНИЯ ТВЕРДОТЕЛЬНЫХ НАКОПИТЕЛЕЙ И МИКРОСХЕМ FLASH-ПАМЯТИ ПРИ ИССЛЕДОВАНИИ ВЛИЯНИЯ НАКОПЛЕННОЙ ДОЗЫ НА СОХРАННОСТЬ ИНФОРМАЦИИ

Testing the whole volume of memory while estimating the effect of space ionizing radiation on the parameters of flash memory might take long time, which is not acceptable for radiation tests The test time optimization is possible by reducing amount of the tested memory at a cost of predictable loss of accuracy in determining the level of radiation hardness. The nature of data loss under TID irradiation is described. The experimental dependences of number of errors in memory on the relative TID are analyzed based on the test results of nine chip types. A calculated estimate of the amount of memory to test is given, that is sufficient to detect errors in memory cells of the entire solid-state drive for the given detection probability. The experimental data analysis shows that testing 10% of the drive increases the error of the TID hardness level determination no more than 20%. An algorithm for identifying abnormal areas in address space of solid-state drives and flash memory chips is proposed. Knowledge about such areas makes it possible to reasonably choose or further reduce the tested amount of memory.

Analytical Bit-Error Model of NAND Flash Memories for Dosimetry Application

In this article, we provide an analytical model for the total ionizing dose (TID) effects on the bit error statistics of commercial flash memory chips. We have validated the model with experimental data collected by irradiating several commercial NAND flash memory chips from different technology nodes. We find that our analytical model can project bit errors at higher TID values [~20 krad (Si)] from measured data at lower TID values [<1 krad (Si)]. Based on our model and the measured data, we have formulated basic design rules for using a commercial flash memory chip as a dosimeter. We discuss the impact of NAND chip-to-chip variability, noise margin, and the intrinsic errors on the dosimeter design using detailed experimentation.

EXPRESS: Exploiting Energy–Accuracy Tradeoffs in 3D NAND Flash Memory for Energy-Efficient Storage

The density and cost-effectiveness of flash memory chips continue to increase, driven by: (a) The continuous physical scaling of memory cells in a single layer; (b) The vertical stacking of multiple layers; and (c) Logical scaling through storing multiple bits of information in a single memory cell. The physical properties of flash memories impose disproportionate latency and energy expenditures to ensure the high integrity of the data during flash memory writes. This paper experimentally explores this disproportionality on state-of-the-art commercial 3D NAND flash memories and introduces EXPRESS—a technique for increasing the energy efficiency of flash memory writes by exploiting the premature termination of the flash write operations. An experimental evaluation shows that EXPRESS reduces energy expenditures by 20–50%, relative to the traditional flash writes, at the cost of a minimal loss in the data integrity (&lt;1%). In addition, we evaluate the effects of the page-to-page variability, program–erase cycling, and data retention on the implementation of EXPRESS, and we propose enhancements to counter these effects.

URM: A Unified RAM Management Scheme for NAND Flash Storage Devices

In NAND flash storage devices, the random access memory (RAM) is composed of a data buffer and mapping cache that play critical roles in storage performance. Furthermore, as the capacity growth rate of RAM chips lags far behind that of flash memory chips, determining how to take advantage of precious RAM is still a crucial issue. However, most existing buffer management studies on storage devices report performance degradation since these devices cannot refine reference regularities such as sequential, hot, or looping data patterns. In addition, most of these studies focus only on separately managing the data buffer or mapping cache. Compared with the existing buffer/cache management schemes (BMSs), we propose a unified RAM management (URM) scheme for not only the mapping cache but also the data buffer in NAND flash storage devices. URM compresses the mapping table to save memory space, and the remaining dynamic RAM space is used for the data buffer. For the data buffer part, we utilize the program counter‐technique in the host layer that provides automatic pattern recognition for different applications, in contrast to existing BMSs. The program counter‐technique in our design is able to distinguish four patterns. According to these patterns, the data buffer is divided into four size‐adjustable zones. Therefore, our approach is linked to multimodal data and used in a data‐intensive system. In particular, in URM, we use a multivariate classification to predict prefetching length in mapping buffer management. Our multivariate classification is transformed into multiple binary classifications (logistic regressions). Finally, we extensively evaluate URM using various realistic workloads, and the experimental results show that, compared with three data buffer management schemes, CFLRU, BPLRU, and VBBMS, URM can improve the hit ratio of data buffer and save response time by an average to 32% and 18%, respectively.

A Novel Program Suspend Scheme for Improving the Reliability of 3D NAND Flash Memory

Experimental results indicate that the conventional program suspend scheme in 3D NAND flash memory chip can generate unexpected additional read fail bits and reduce the reliability of 3D NAND flash memory. These extra read fail bits are observed when the program suspend command is issued during the program stage, and particularly, they become more obvious as the delay time between program suspend operation and other following operations exceeds tens of milliseconds. By analyzing the waveform of conventional program suspend scheme, it is suggested that the unexpected extra read fail bits are caused by the different occupancy of grain boundary traps (GBTs) in the polycrystalline silicon (poly-Si) channel during the idle time after the program suspend operation. Accordingly, a novel program suspend scheme is proposed by adding a &#x201C;stabilizing&#x201D; pulse immediately after the program stage. Silicon experimental data show that the proposed scheme can effectively limit the read fail bit count (FBC) to a normal range, thus improving the reliability of 3D NAND flash memory significantly.

Development of a Datalogger for Submarine Glider: Integration of Fault-Tolerant Software Layers

Submarine gliders are specialized systems used in applications such as environmental monitoring of marine fauna, in the oil industry, among others. The glider launch and capture is a costly process that requires substantial technological and human resources, so the orderly and error-free storage of data is of fundamental importance due to the subsequent analysis. The amount of information being obtained from the seabed is increasing, this leads to the need to develop robust and low-cost ad-hocsystems for this type of application. The challenge is the integration of the different software layers in the storage system because the monitored variables must be ordered according to different glider operations such as calibration data update and navigation. Additionally, to avoid data corruption in the memory chip, error control coding must be used. The goal of this paper is to present a novel design of different layers of software integrated into a datalogger: reception, error control, and storage logic for the different glider operations. The design of the datalogger is based on a NAND flash memory chip and an MSP430 microcontroller. To correct bit-flipping errors, a BCH code that corrects 4 errors for every 255 bits is implemented into the microcontroller. The design and evaluation are performed for different glider operations, and for different lengths and correction capabilities of the BCH module. A test to calculate the storage time has been carried out. This test shows that in the case of 256 bytes per sample, at 30 samples per minute, and 1 GB of storage capacity, it is possible to collect data from the glider sensors for 84 days. The results obtained show that our device is a useful option for storing underwater sensor data due to its real-time storage, power consumption, small size, easy integration, and its reliability, where the bit error rate BER is of 2.4 ×10−11.

Forensic analysis for AI speaker with display Echo Show [formula omitted] generation as a case study

As the Internet of Things (IoT) era arrives, many Internet-connected devices are being released, and their use is increasing. One of these, the AI speaker, is designed to augment user convenience by using voice recognition. The best-known products are the Amazon Echo family, including Echo and Echo Dot and more recently, Echo Show with display. An AI speaker with display provides diverse functions such as surfing the Internet, taking pictures, making voice or video calls, and controlling smart home devices. To do this, Alexa cloud servers store a variety of configuration values and historical logs, and users can manage their own cloud-native data through interfaces (e.g., Web sites or mobile apps). For this reason, AI speakers with smart display are similar to PCs or smartphones, which can be very profitable from a digital forensic perspective. This paper focuses on detailed research on the second generation of Echo Show. The first step was to collect forensic artifacts stored inside the product by teardown, identifying eMMC flash memory chips and performing chip-off on Echo Show. Alexa app-related artifacts used on smartphones and how to automatically acquire data from the Alexa cloud were also investigated. From three sources including Echo Show, a companion client (smartphone), and the Alexa cloud, it was possible to acquire user credentials, traces of photos, records of watching videos, log files, and Internet histories with timestamp. The second step was to identify the possibility of inferring new information by correlating artifacts collected from different sources. Integrative analysis enables investigators to track suspect activity across digital devices. Third, this paper introduces an updated version of Cloud-based IoT Forensic Toolkit (CIFT) to support digital investigation of Echo Show. Based on the technical findings, this study proposes a digital forensic framework for a smart speaker with a display that can play an important role as a digital witness at a crime scene. Until now, there has been no multilevel approach to acquisition and analysis of Echo Show data in the field of digital forensics. Therefore, this study makes a contribution to the digital forensic community.

Temperature Impacts on Endurance and Read Disturbs in Charge-Trap 3D NAND Flash Memories.

Temperature effects should be well considered when designing flash-based memory systems, because they are a fundamental factor that affect both the performance and the reliability of NAND flash memories. In this work, aiming to comprehensively understanding the temperature effects on 3D NAND flash memory, triple-level-cell (TLC) mode charge-trap (CT) 3D NAND flash memory chips were characterized systematically in a wide temperature range (−30~70 °C), by focusing on the raw bit error rate (RBER) degradation during program/erase (P/E) cycling (endurance) and frequent reading (read disturb). It was observed that (1) the program time showed strong dependences on the temperature and P/E cycles, which could be well fitted by the proposed temperature-dependent cycling program time (TCPT) model; (2) RBER could be suppressed at higher temperatures, while its degradation weakly depended on the temperature, indicating that high-temperature operations would not accelerate the memory cells’ degradation; (3) read disturbs were much more serious at low temperatures, while it helped to recover a part of RBER at high temperatures.

Flash-DNA: Identifying NAND Flash Memory Origins Using Intrinsic Array Properties

Counterfeit electronics entering the globalized supply chain are a growing problem impacting manufacturers and consumers alike. This article introduces Flash-DNA, a new technique for identifying the original chip manufacturer of NAND flash memory, which will help preventing the proliferation of rebranded or cloned flash memory chips. Flash-DNA relies on extracting intrinsic variations in NAND arrays using a partial block erase operation. Our experimental evaluation, conducted on multiple memory chips from four major manufacturers, shows that Flash-DNA captures fundamental properties of the manufacturing process, providing a unique identifier for a family of NAND flash memory chips that can be used for tracing their origins.

Total Ionizing Dose Effects on Physical Unclonable Function From NAND Flash Memory

This article demonstrates the total ionizing dose (TID) impact on a NAND flash memory-based physical unclonable function (PUF). We used commercial-off-the-shelf flash memory chips to generate PUF. The flash chip is irradiated with Co-60 gamma rays up to 10 krad(Si). The irradiated chip shows significant accuracy degradation (bit error ~ 12%) of the flash-PUF. We show that TID-induced trapped charges in the oxide alter the intrinsic cell properties causing accuracy degradation of flash-PUF. We propose two independent techniques to improve the PUF accuracy under radiation environment. The first technique relies on electrical annealing which compensates the trapped charges by program stressing. The second technique uses radiation compensation method by adaptive PUF generation process. Our experimental results show that the accuracy degradation can be as low as 1.5% for TID up to 10 krad(Si) with these radiation mitigation techniques.

Decoupled SSD: Reducing Data Movement on NAND-Based Flash SSD

Modern NAND Flash memory-based Solid State Drive (SSD) is designed to support high bandwidth for I/O requests by exploiting various parallelism including multiple channels, multiple flash memory chips, and multiple planes. However, SSD system is utilized not only for general I/O requests but is also used during flash memory management processes (e.g., garbage collection). In particular, the sharing of system resources (e.g., system bus, DRAM) for I/O requests and garbage collection can cause performance degradation. In this letter, we address the system bus bottleneck and propose <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><b>Decoupled</b></i> SSD system that decouples the front-end (i.e. cores, system bus) with the back-end (i.e., flash memory) and provide an on-chip network to interconnect the controllers together. Our decoupled SSD enables advanced command (i.e. copy-back) to be exploited for efficient garbage collection; in particular, we propose to extend copy-back commands to enable <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">global</i> copy-back through the flash-controller interconnect to effectively decouple I/O path and garbage collection path. Our evaluations show that decoupled SSD results in up to 34.7% bandwidth improvement, for I/O traffic while achieving up to 69% speedup for garbage collection.