Flash Memory Chips Research Articles

G-Force Exposure in a Contact Sport: The Use of Accelerometers to Quantify Physical Stress

GPS-based analyses of movement patterns are inadequate for quantifying the physical stress imposed on athletes in contact sports. Accelerometers may be useful for monitoring such athletes. The purpose of this study was to use triaxial accelerometers to record G-force exposure in Gaelic football players to examine differences in G-force exposure between games and practices and between playing positions. A small triaxial accelerometer with a flash memory chip data logger was fitted to the waistband of players’ shorts. Game and practice data were acquired at 100 Hz (scale ±16G) from 19 club level players (age 25±7 yr). Resultant G-force was: calculated for each data point from the raw accelerometer data collected in all three planes of motion and analyzed by quantifying the time spent above different G-force thresholds. Player positions were categorized as central (half backs/half forwards/midfield) and peripheral (full back/full forward) with central players typically more involved in continuous running. ANOVA with Bonferroni corrections was used to compare G-force exposure between games vs. practices, and between central vs. peripheral players (practice not position dependent). Differences between games and practices were apparent for time >3G, >4G, and >5G with more time at these thresholds in practices versus games (P=0.003), indicating higher G-force exposure in practices versus games. In games central players had greater time at >2G and >3G (P<0.001). Accelerometry analysis was effective in distinguishing player position-dependent differences in G-force exposure, and differences between games and practices. These differences indicate that the method of analysis of G-force exposure used here may be of utility for quantifying the physical stresses imposed on athletes in contact sports.

Realizing Unequal Error Correction for nand Flash Memory at Minimal Read Latency Overhead

In nand Flash memory, all pages have the same storage capacity and hence accommodate the same amount of redundancy in support of error correction. In current practice, user data in all the pages are protected by the same error correction code. However, different types of pages in multibit per cell memory have largely different bit error rates, for which appropriate unequal error correction can achieve a better utilization of memory redundancy and hence improve program/erase (P/E) cycling endurance. Nevertheless, a straightforward realization of unequal error correction suffers from severe memory read latency penalty. This brief presents a design strategy to implement unequal error correction through concatenated coding, which can well match the unequal error rates among different types of pages at minimal memory read latency penalty. Based on measurement results from commercial sub-22-nm 2 bits/cell nand Flash memory chips, we carried out simulations from both the coding and storage system perspectives, and the results show that this design strategy can improve the P/E cycling endurance by 20% and only incur less than 7% increase of storage system read response time at the end of Flash memory lifetime with the P/E cycling of around 1800.

Coded Modulation Using Lattices and Reed-Solomon Codes, with Applications to Flash Memories

This paper describes a coded modulation scheme where low-dimension lattices are used as the constellation, and Reed-Solomon codes are used for error correction. Low-dimension lattices, such as the eight-dimensional E <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">8</sub> lattice, have better distance properties than one- and two-dimensional constellations, and they have efficient soft-input decoding algorithms as well. On the other hand, Reed-Solomon codes have optimal distance properties, and their decoding algorithms are well understood. This construction is targeted at high-rate flash memories, where BCH codes using Gray-coded pulse-amplitude modulation are often used. Performance gains of 1.0 dB to 1.8 dB over BCH codes is demonstrated through analysis and simulation, under the assumption of additive white Gaussian noise. For flash memory systems where the ECC chip is separate from the flash chip, this code construction allows using soft information entirely inside a flash memory chip which has a low-complexity lattice decoder implementation.

A New Multi-Tiered Solid State Disk Using Slc/Mlc Combined Flash Memory

Storing digital information, ensuring the accuracy, steady and uninterrupted access to the data are considered as fundamental challenges in enterprise -class organizations and companies. In recentyears, new types of storage systems such as solid state disks (SSD) have been introduced. Unlike hard disks that have mechanical structure, SSDs are based on flash memory and thus have electronic structure. Generally a SSD consists of a number of flash mem ory chips, some buffers of the volatile memory type, and an embedded microprocessor, which have been interconnected by a port. This microprocessor run a small file system which called flash translation layer (FTL). This software controls and schedules buff ers, data transfers and all flash memory tasks. SSDs have some advantages over hard disks such as high speed, low energy consumption, lower heat and noise, resistance against damage, and smaller size. Besides, some disadvantages such as limited endurance a nd high price are still challenging. In this study, the effort is to combine two common technologies- SLC and MLC chips- used in the manufacture of SSDs in a single SSD to decrease the side effects of current SSDs. The idea of using multi -layer SSD is regarded as an efficient solution in this field.

Design of a Small-Sized High-Speed Data Storage Module Based on FPGA

The large-capacity, high-speed and low power consumption become the new requirements for the data storage systems. In this paper, a high-performance storage module based on multiple NAND flash memory chips is presented to real-time massive data acquisition system. In order to achieve the miniaturization dimension and the high-speed data storage design requirements, the paper presents a small size and high-speed storage unit based on NAND flash, where the dimensions of the module can reach 33mm×33mm and the maximum rate is up to 60MB/s. Ensuring continuous and reliable operation requires a dedicated buffering for the data transmission. We analyze the elements and peculiarities of the flash memory chip and propose a multi-way architecture to speed up data access. The design of a multilevel high-speed buffer structure based on the field programmable gate array (FPGA) technology is introduced in the paper. The proposed system can be applicable to some portable digital equipment.

Ultra-fast annealing to reduce the residual stress in ultra-thin chips using flash light

The continuing trend of miniaturization in electronic equipment includes demands for thinner and smaller semiconductor devices with higher performance. To ensure the reliability of electronic devices and to enable high-throughput packaging processes, the mechanical properties of ultra-thin chips need to be accurately understood. One important consideration is the residual stress generated during wafer thinning due to the shear force between the grinding wheel and polish pad; this stress can degrade the fracture strength of ultra-thin devices. To reduce this residual stress, we developed a flash light irradiation annealing technique, including optimization of the irradiation conditions of flash light energy, pulse number and pulse duration. The distributions of residual stresses within ultra-thin flash memory chips before and after the annealing were measured using Raman spectroscopy, and their fracture strength was measured using a ball-on-ring test. Also, transmission electron microscopy (TEM) analysis and beam transfer function tests were performed to investigate the changes in mechanical properties and changes to the silicon lattice effected by the annealing. The ultra-fast flash light annealing was found to reduce the residual stress of ultra-thin chips by 50%, thereby improving their fracture strength by 20% compared to unannealed chips.

A PD-SOI based DTI-LOCOS combined cross isolation technique for minimizing TID radiation induced leakage in high density memory

In order to minimize leakage current increase under total ionizing dose (TID) radiation in high density memory circuits, a new isolation technique, combining deep trench isolation (DTI) between the wells, local oxidation of silicon (LOCOS) isolation between the devices within the well, and a P-diffused area in order to limit leakage at the isolation edge is implemented in partly-depleted silicon-on-insulator (PD-SOI) technology. This radiation hardening technique can minimize the layout area by more than 60%, and allows flexible placement of the body contact. Radiation hardened transistors and 256 Kb flash memory chips are designed and fabricated in a 0.6 μm PD-SOI process. Experiments show that no obvious increase in leakage current is observed for single transistors under 1 Mrad(Si) radiation, and that the 256 Kb memory chip still functions well after a TID of 100 krad(Si), with only 50% increase of the active power consumption in read mode.

On-Demand Block-Level Address Mapping in Large-Scale NAND Flash Storage Systems

The density of flash memory chips has doubled every two years in the past decade and the trend is expected to continue. The increasing capacity of NAND flash memory leads to large RAM footprint on address mapping management. This paper proposes a novel Demand-based block-level Address mapping scheme with a two-level Caching mechanism (DAC) for large-scale NAND flash storage systems. The objective is to reduce RAM footprint without excessively compromising system response time. In our technique, the block-level address mapping table is stored in fixed pages (called the translation pages) in the flash memory. Considering temporal locality that workloads exhibit, we maintain one cache in RAM to store the on-demand address mapping entries. Meanwhile, by exploring both spatial locality and access frequency of workloads with another two caches, the second-level cache is designed to cache selected translation pages. In such a way, both the most-frequently-accessed and sequentially accessed address mapping entries can be stored in the cache so the cache hit ratio can be increased and the system response time can be improved. To the best of our knowledge, this is the first work to reduce the RAM cost by employing the demand-based approach on block-level address mapping schemes. The experiments have been conducted on a real embedded platform. The experimental results show that our technique can effectively reduce the RAM footprint while maintaining similar average system response time compared with previous work.

Measurements of Dynamic Characteristics of Intermediate Layer in Thin Semiconductors

A vibration test method for investigating the dynamic characteristics of thin multi-layered semiconductor wafers was proposed. Flash memory chips whose thickness was varied by grinding the wafers were used as specimens. The specimens composed of silicon, device, and device-protecting layers were excited at the clamped end by using a shaker attached to the clamping device. The vibration of the beam was measured using a laser vibrometer. The wave approach was used to analyze the vibration, from which the complex bending stiffness was determined. A theoretical model to obtain the dynamic characteristics (Young's modulus and the loss factor) of the intermediate device layer by using the measured bending stiffness was investigated. The results were examined and compared with those of a nanoindentation test to verify the accuracy of the model. The proposed method enabled determination of the dynamic properties of the intermediate layer without separation which are essential for understanding the impact response of the wafers during manufacturing process.

Reliability Enhancement of Flash-Memory Storage Systems: An Efficient Version-Based Design

In recent years, reliability has become one critical issue in the designs of flash-memory file/storage systems, due to the growing unreliability of advanced flash-memory chips. In this paper, a version-based design is proposed to effectively and efficiently maintain the consistency among page versions of a file for potential recovery needs. In particular, a two-version one for a native file system is presented with the minimal overheads in version maintenance. A recovery scheme is then presented to restore a corrupted file back to the latest consistent version. The design is later extended to maintain multiple data versions with the considerations of the write constraints of multilevel-cell flash memory. It was shown that the proposed design could significantly improve the reliability of flash memory with limited management and space overheads.

PCI Express-Based NVMe Solid State Disk

This paper presents a new architecture SSD based on NVMe (Non-Volatile Memory express) protocol. The NVMe SSD promises to solve the conventional SATA and SAS interface bottleneck. Its aimed to present a PCIe NAND Flash memory card that uses NAND Flash memory chip as the storage media. The paper analyzes the PCIe protocol and the characteristics of SSD controller, and then gives the detailed design of the PCIe SSD. It mainly contains the PCIe port and Flash Translation Layer.

A reliability enhancement design under the flash translation layer for MLC-based flash-memory storage systems

Although flash memory has gained very strong momentum in the storage market, the reliability of flash-memory chips has been dropped significantly in the past years. This article presents a reliability enhancement design under the flash management layer (i.e., flash translation layer) to address this concern so as to reduce the design complexity of flash-memory management software/firmware and to improve the maintainability and portability of existing and future products. In particular, a log-based write strategy with a hash-based caching policy is proposed to provide extra ECC redundancy and performance improvement. Strategies for bad block management are also presented. The failure rate of flash-memory storage systems is analyzed with the considerations of bit errors. The proposed design is later evaluated by a series of experiments based on realistic traces. It was shown that the proposed approach could significantly improve the reliability of flash memory with very limited system overheads.

Modeling Power Consumption of NAND Flash Memories Using FlashPower

Flash is the most popular solid-state memory technology used today. A range of consumer electronics products, such as cell-phones and music players, use flash memory for storage and flash memory is increasingly displacing hard disk drives as the primary storage device in laptops, desktops, and servers. There is a rich microarchitectural design space for flash memory, and there are several architectural options for incorporating flash into the memory hierarchy. Exploring this design space requires detailed insights into the power characteristics of flash memory. In this paper, we present FlashPower, a detailed power model for the two most popular variants of NAND flash, namely, the single-level cell (SLC) and 2-bit Multi-Level Cell (MLC) based flash memory chips. FlashPower is built on top of CACTI, a widely used tool in the architecture community for studying various memory organizations. FlashPower takes several parameters like the device technology, microarchitectural layout, bias voltages and workload parameters as input to estimate the power consumption of a flash chip during its various operating modes. We validate FlashPower against chip power measurements from several different manufacturers and show that our results are comparable to the actual chip measurements. We illustrate the versatility of the tool in a design space exploration of power optimal flash memory array configurations.

Hot hole-induced device degradation by drain junction reverse current

In this paper, device degradation mechanisms by drain junction reverse current in the off-state were studied, using n-type metal–oxide–semiconductor field-effect transistor (N-MOSFET), which is used as the high-voltage core circuit of flash memory chip. Components of drain leakage currents in the off-state are gate-induced drain-leakage (GIDL) and drain junction reverse currents. Device degradation phenomenon and mechanism by GIDL in the MOSFETs have been well known, but those by drain junction reverse current have not. A variety of measurement conditions for separating drain junction reverse current from total drain current in the off-state were suggested, and hole injection phenomenon into the gate was investigated through the modified capacitive-voltage method. In addition, we investigated the location of electron–hole generation between GIDL and drain junction reverse current through the lateral profile of trapped hole extracted from charge pumping method.

Using Quasi-EZ-NAND Flash Memory to Build Large-Capacity Solid-State Drives in Computing Systems

Future flash-based solid-state drives (SSDs) must employ increasingly powerful error correction code (ECC) and digital signal processing (DSP) techniques to compensate the negative impact of technology scaling on NAND flash memory device reliability. Currently, all the ECC and DSP functions are implemented in a central SSD controller. However, the use of more powerful ECC and DSP makes such design practice subject to significant speed performance degradation and complicated controller implementation. An EZ-NAND (Error Zero NAND) flash memory design strategy is emerging in the industry, which moves all the ECC and DSP functions to each memory chip. Although EZ-NAND flash can simplify controller design and achieve high system speed performance, its high silicon cost may not be affordable for large-capacity SSDs in computing systems. We propose a quasi-EZ-NAND design strategy that hierarchically distributes ECC and DSP functions on both NAND flash memory chips and the central SSD controller. Compared with EZ-NAND design concept, it can maintain almost the same speed performance while reducing silicon cost overhead. Assuming the use of low-density parity-check (LDPC) code and postcompensation DSP technique, trace-based simulations show that SSDs using quasi-EZ-NAND flash can realize almost the same speed as SSDs using EZ-NAND flash, and both can reduce the average SSD response time by over 90 percent compared with conventional design practice. Silicon design at 65 nm node shows that quasi-EZ-NAND can reduce the silicon cost overhead by up to 44 percent compared with EZ-NAND.

Implementation strategy for downgraded flash-memory storage devices

In recent years, low-cost flash-memory devices have contributed greatly to the rapid growth of the flash memory market. Given that the most of the cost of such devices is the cost of the flash-memory chips, many vendors are managing the cost of such devices by using flash-memory chips of low quality, and they will continue to do so in the near future. Recognizing strong market demand, this work presents a set-based mapping strategy with an effective implementation and low hardware resource requirements for making downgraded flash-memory chips useable in products. A configurable management design for managing chips of various qualities with improved lifetime is presented. The effectiveness of the proposed strategy is evaluated by performing a series of experiments and analyzed with reference to popular implementations in industry.

A multi-controller architecture for high-performance solid-state drives

A solid-state drive consists of controllers and NAND flash memory chips, and each chip is controlled by one controller. Since each controller is responsible for a fixed number of chips, it can't control other chips that don't belong to it. Therefore, some idle controllers can't access other chips that don't belong to them, and it will reduce system performance. In this paper, we will propose a multi-controller architecture for high-performance solid-state drives. With the design, any chip will not be restricted to any specific controller, and any idle controller can access any chip. The experimental results show that the proposed method can improve system throughput of 25% when compared with traditional solid-state drives, and the incurred overhead is also reasonable.

1-W 3.3–16.3-V Boosting Wireless Power Transfer Circuits With Vector Summing Power Controller

This paper presents SD-card-size wireless power transfer system for large-volume contactless memory cards. Voltage is boosted simultaneously with power transfer, which eliminates the dc-dc converter or charge-pump circuit for data write operation into the flash memory chip. The proposed approach reduces the number of components and BOM cost and improves the total power efficiency. A vector summing technique is proposed to control the transmitting power and secondary side voltage. The transmitter and rectifier have been designed and fabricated using 0.18-μ m-CMOS with high voltage option. Voltage boost from 3.3 to 16.3 V and 1-W power transfer with 50% total efficiency have been successfully demonstrated, and the response time for the power control loop is shorter than 35 μs .

Bi-axial fracture strength characteristic of an ultra-thin flash memory chip

Recently, ultra-thin chips with thicknesses of under 35 µm have emerged as an option for thinner, high performance electronic devices. For reliable electronic devices and high throughput packaging processes, the mechanical properties of ultra-thin chips need to be accurately understood. In this study, the fracture strength of an ultra-thin flash memory chip was measured using a ball-on-ring (BOR) test. To evaluate and validate the bi-axial strength in the BOR test, a finite element analysis was performed. It was compared with the analytical solution based on Hertzian contact theory. Flash memory chip specimens with different thicknesses were prepared and their bi-axial strengths were tested with respect to various wafer thinning process parameters such as grinding speed and polishing time. Raman spectroscopy was used to characterize the residual stress generated during the wafer thinning process. The surface roughness of the silicon wafer was measured using an atomic force microscope under various wafer thinning conditions. From the study, the fracture strength characteristics of the ultra-thin chip could be established as a function of the wafer thinning parameters.

개인용 SSD를 위한 선반입 및 메모리 관리 정책

기존의 운영체제에서 하드디스크의 성능을 향상시키기 위해서 사용해왔던 기술들이 SSD(Solid State Drive)에는 부정적 효과를 나타내는 경우가 많다. HDD의 기계적인 요소 때문에 접근 시간과 블록 주소의 순서가 성능에 매우 중요한 요인으로 작용하였지만, SSD는 불록 주소의 순서에 영향을 받지 않는 우수한 랜덤 읽기 성능을 제공한다. 실제 개인용 PC에서 SSD를 사용할 때에 선반입을 끄도록 권고되고 있다. 하지만 이 논문은 SSD의 내부 구조와 낸드 플래시 메모리의 특징을 고려한 선반입 및 메모리관리 정책를 결합한 방법을 제시한다. SSD에는 다수개의 낸드 플래시 메모리로 구성되어 있어 칩을 동시에 구동시키는 것이 중요하며, 낸드 플래시 메모리의 기본 입출력 단위가 계속 증가하는 방향으로 발전하고 있어서 SSD 내부의 동작 단위가 운영체제의 블록 크기보다 훨씬 커지게 되었다. 이 논문은 이러한 SSD의 특징과 경향을 수용하여, 제안하는 선반입 기법은 SSD의 동작 단위로 수행되며, 제안하는 메모리 관리 기법은 그 선반입 기법의 단점을 보완하여, 캐시 히트율과 선반입 히트율의 합이 최대가 되도록, 선반입되었지만 사용되지 않는 데이터를 적응적으로 퇴출한다. 본 기술은 리눅스 커널 모듈로 개발하였으며 실제 SSD를 사용하여 성능 평가를 실시하였다. 주어진 실험에서 제안하는 선반입 기법이 약 26%까지 성능을 향상시켰다. Traditional technologies that are used to improve the performance of hard disk drives show many negative cases if they are applied to solid state drives (SSD). Access time and block sequence in hard disk drives that consist of mechanical components are very important performance factors. Meanwhile, SSD provides superior random read performance that is not affected by block address sequence due to the characteristics of flash memory. Practically, it is recommended to disable prefetching if a SSD is installed in a personal computer. However, this paper presents a combinational method of a prefetching scheme and a memory management that consider the internal structure of SSD and the characteristics of NAND flash memory. It is important that SSD must concurrently operate multiple flash memory chips. The I/O unit size of NAND flash memory tends to increase and it exceeded the block size of operating systems. Hence, the proposed prefetching scheme performs in an operating unit of SSD. To complement a weak point of the prefetching scheme, the proposed memory management scheme adaptively evicts uselessly prefetched data to maximize the sum of cache hit rate and prefetch hit rate. We implemented the proposed schemes as a Linux kernel module and evaluated them using a commercial SSD. The schemes improved the I/O performance up to 26% in a given experiment.