Fixed-point Digital Filters Research Articles

Discrete-time state delayed systems with saturation arithmetic: overflow oscillation-free realization

ABSTRACT In many smart systems, such as cloud computing, networked control, manufacturing, and telecommunication, the effects of time delays are unavoidable. Saturation nonlinearity is common in many smart systems (e.g. electric systems with limited actuator power supplies, mechanical systems with position and speed constraints, fixed-point digital filters, etc.). Therefore, the study of stability of discrete-time systems (DTSs) with time delay and saturation is of high importance in practice. The global asymptotic stability (GAS) problem of such systems is investigated in this paper. The saturation nonlinearity is constrained by a convex hull with a free matrix whose infinity norm is smaller than or equal to unity. A new Lyapunov-based GAS criterion for DTSs with time-varying delay and state saturation is established. The GAS problem for DTSs with constant delay and saturation is also discussed. The obtained results can be used to ensure the absence of overflow oscillations in the considered system. In comparison to several existing criteria, the approach yields improved stability results. An example is provided to demonstrate the importance of the presented results.

Criterion for the Global Asymptotic Stability of Fixed-Point Lipschitz Nonlinear Digital Filter with 2’s Complement Overflow Arithmetic

This paper is concerned with the global asymptotic stability (GAS) problem of fixed-point Lipschitz nonlinear digital filters employing 2’s complement overflow arithmetic. Nonlinear digital filtering finds immense applications in various fields such as adaptive systems and controllers, digital controllers and observers for nonlinear systems, realization of neural networks using digital hardware, controllers for feedback linearization, etc. Lipschitz nonlinear digital filter is considered in this paper as it is frequently employed in nonlinear digital filtering, state filtering, neural networks, feedback control, digital controllers, decision-taking systems and so on. Based on Lyapunov theory, the property of 2’s complement overflow arithmetic and Lipschitz condition associated with system nonlinearities, a new criterion for the suppression of overflow oscillations in 2’s complement state variable realizations of digital filters is established. Several examples along with simulation results are provided to highlight the utility of the criterion.

Novel Criterion for Preventing Overflow Oscillations in Fixed-Point Digital Filters With State Saturation

This letter presents a novel global asymptotic stability (GAS) criterion for fixed-point digital filters (DFs) employing saturation overflow arithmetic. The criterion is developed using an improved characterization of saturation nonlinearities (as prevailing in the DF under study) and Lyapunov theory. The criterion outperforms a series of existing criteria.

Realisation of overflow oscillation-free fixed-point digital filters with 2’s complement arithmetic

ABSTRACT In this paper, we focus on the problem of overflow oscillation elimination in 2’s complement state variable realisation of fixed-point digital filters. A new global asymptotic stability (GAS) criterion for the zero-input fixed-point state-space digital filters employing 2’s complement overflow arithmetic is proposed. The proposed criterion captures the structural properties of 2’s complement overflow nonlinearities in a greater detail as compared to several existing criteria. A comparative evaluation of the proposed criterion with various previously reported criteria is made. The obtained criterion turns out to be less stringent than several existing results. An example along with simulation results to substantiate the utility of the criterion is also provided.

Criterion for the H∞ Suppression of Overflow Oscillations in Fixed Point Digital Filters Employing Saturation Nonlinearities and External Interference

This paper proposes a novel criterion for suppressing the [Formula: see text] overflow oscillations in fixed point state-space digital filters employing saturation nonlinearities and external interference. The proposed criterion can be used to ensure the exponential stability (ES) and diminish the external interference effects to an [Formula: see text] norm constraint. An example is given to exemplify the utility of the obtained results.

IIR Filter Architectures with Truncation Error Feedback for ECG Signal Processing

This work proposes fixed-point hardware architectures for two IIR filters, focusing on design specifications for ECG signal processing, using the truncation error feedback (TEF) to attenuate errors caused by truncation operations inside these recursive structures. The TEF is represented by modulo operation followed by a unit-delay operator and multiplication by a coefficient. In this work, the proposed TEF core consists of a hardware structure based on delay, right-shift and modulo operations. The TEF approach is applied to sequential and parallel IIR filter architectures with fixed and adaptive coefficients. The first structure comprises a first-order high-pass filter applied to attenuate low frequencies of the electrocardiogram (ECG) signal. The second one is a second-order infinite impulse response (IIR) adaptive notch filter used to attenuate power line interference signals. All dedicated architectures were described and simulated using VHDL and synthesized in Cadence environment using the 45 nm Nangate Open Cell Library to verify the results of the area, delay and power metrics. A simulated ECG signal was used as input to check the functionality of the filters. Our results indicate that the TEF approach was useful for both high-pass filter (HPF) and adaptive notch filter (ANF), and it can be a significant strategy to meet design specifications and dynamic performance of fixed-point digital filters. For the synthesis analysis, both HPF and ANF sequential filters had lower power and cell area figures but presented higher normalized power per sample and delay. In summation, the TEF approach enabled the use of fixed-point filters for ECG filtering without degrading their dynamic performance or increasing noise caused by truncation.

The laboratory tester of solar cells with dynamic reconfigutration of measuring system

An express meter of photovoltaic solar cells based on the programmable system on a chip PSoC5 and a personal computer is proposed. This tester is best suited for research on experimental samples of solar cells with non-standard dimensions and parameters, but can also be used as a standard tester for standard samples to control their characteristics with high precision. For the implementation a minimum of discrete elements — a PSoC5 chip, a transistor and a couple of resistors and diodes are required. And such devices as voltage supplies and a computer are available in each laboratory. The standard test conditions (irradiance 1 kW per sq.meter; spectral distribution AM 1.5; sample temperature 25oC) are conditions that obtainable in a laboratory by using a xenon single flash tube or by an incandescent lamp with filter to reduce the red part of spectra. Despite of the simplicity of the implementation the tester performs measurements of the basic parameters of solar cells (open-circuit voltage, short-circuit current, internal serial resistance and shunt resistance, maximum power, voltage and current at maximum power, efficiency, fill factor, short circuit current density) with high precision and charting current-voltage characteristic of solar cell during less than a second. All the parameters and the current-voltage characteristic are automatically saved to a file and can be examined later. Advantages of the tester are a low cost and highly flexible implementation of the measuring system that allows you to explore experimental samples of solar cells with different characteristics. This was implemented through the use of dynamic reconfiguration of system on a chip that adapts to the conditions of measurement. Depending on the photoelectric current, the algorithm, written in the memory of the programmable system on a chip, selects the appropriate configuration of the measuring system and adjusts the bit resolution (up to 20 bit) and type of the analog-to-digital converter, and gain of the built-in amplifier to provide a minimum time of measurement and maximum of accuracy at given conditions. This allows researchers to reduce the time for investigation of objects with unknown characteristics at a given measurement accuracy. In addition, a sufficient number of additional hardware resources of the programmable system on a chip (digital blocks for logic, timers, counters, analog blocks for operational amplifiers, a programmable gain amplifier, comparators, mixer sample and hold circuit, etc.) with the possibility of their easy configuration into the electronic circuit in the graphic mode of the PSoC Creator allows to researchers easily and quickly to fill up / adjust the electrical scheme to their needs without the need to change the circuit board of the device. The presence on the PSoC of the ARM Cortex-M3 32-bit CPU and the 24-bit fixed-point digital filter processor allows the researcher to supplement the measurement circuitry with digital signal processing, which is especially relevant for small-scale research samples with weak signals in the presence of noises.Ref. 10, fig. 7.

Novel Results for Induced l∞ Stability for Digital Filters with External Noise

This paper establishes novel criteria for the induced [Formula: see text] stability to avoid overflow oscillations in fixed-point digital filters with generalized overflow non-linearities and external noise. The proposed linear matrix inequality (LMI)-based criteria ensure exponential stability as well as confirm reduction in the influence of external noise. The generalized overflow non-linearities which are considered for analysis commonly occur in practice, viz. saturation, zeroing, two's complement, and triangular. The presented approach unifies a string of existing results which are derived by considering saturation non-linearities and external interference. Simulation examples are shown to validate the usefulness of the proposed approach.

An Improved Criterion for Induced Stability of Fixed-Point Digital Filters with Saturation Arithmetic

<p>This paper establishes a criterion for the induced stability of fixed-point state-space digital filters with saturation nonlinearities and external interference. The criterion is established in a linear matrix inequality (LMI) setting, and therefore, computationally tractable. The criterion turns out to be an improvement over a previously reported criterion. A comparison of the presented criterion with existing criterion is made. Numerical examples are given to demonstrate the usefulness of the proposed approach.</p>

A Note on the Induced $${\varvec{l}}_\infty $$ l ∞ Stability of Fixed-Point Digital Filters Without Overflow Oscillations and Instability Due to Finite Wordlength Effects

A recently reported criterion due to Ahn and Lee (Adv Differ Equ 51:1---7, 2012) for the induced $${\varvec{l}}_\infty $$lź stability of fixed-point digital filters without overflow oscillations and instability due to finite wordlength effects is reviewed. This article points out that there is a technical error in the main result and at the same time presents an approach to correcting the main result. Moreover, a relaxed version of the criterion is made available. Illustrative examples are given to demonstrate the effectiveness of the proposed result.

Bounded model checking for fixed-point digital filters

Currently, digital filters are employed in a wide range of signal processing applications, using fixed- and floating-point processors. Regarding the former, some filter implementations may be highly prone to errors, due to problems related to finite word-length. In particular, signal processing modules may produce overflows and unwanted noise, which are caused by quantization and round-off effects, during accumulative-addition and multiplication operations. As a consequence, the system output may overflow or even keep oscillating, which compromises the expected system performance. The present paper addresses this problem and proposes a new methodology for verifying digital filters, called digital systems verifier, which is based on state-of-the-art bounded model checkers that support full C and employ solvers for boolean satisfiability and satisfiability modulo theories. In addition to verifying overflow and limit-cycle occurrences, the present approach can also check output errors and time constraints, based on discrete-time models implemented in C. Experiments conducted during this work show that the proposed methodology is effective, when finding realistic design errors with respect to fixed-point implementations of digital filters. Going further than previous attempts, the present results suggest that the proposed method, in addition to helping designers in determining the number of bits for fixed-point representations, can also aid in defining details about filter realization and structure.

A bit too precise? Verification of quantized digital filters

Fixed-point digital filters are simple yet ubiquitous components of a wide variety of digital processing and control systems. Common errors in fixed-point filters include arithmetic round-off (truncation) errors, overflows and the presence of limit cycles. These errors can potentially compromise the correctness of the system as a whole. Traditionally, digital filters have been verified using a combination of design techniques from control theory and extensive testing. In this paper, we examine the use of formal verification techniques as part of the design flow for fixed-point digital filters. We study two classes of verification techniques involving bit-precise analysis and real-valued error approximations, respectively. We empirically evaluate several variants of these two fundamental approaches for verifying fixed-point implementations of digital filters. We design our comparison to reveal the best possible approach towards verifying real-world designs of infinite impulse response (IIR) digital filters. Our study compares the strengths and weaknesses of different verification techniques for digital filters and suggests efficient approaches using modern satisfiability-modulo-theories solvers (SMT) and hardware model checkers. This manuscript extends our previous work evaluating bounded verification, where a limited number of iterations of the system are explored, with unbounded verification, where an unlimited number of iterations of the system are considered. Doing so allows us to evaluate techniques that can prove the correctness of fixed-point digital filter implementations.

Stability criterion for a class of fixed-point digital filters using two’s complement arithmetic

A new stability criterion for a class of digital filters using two’s complement arithmetic is presented. The effectiveness of the obtained results is shown by using a numerical example.

Fixed-point digital IIR filter design using two-stage ensemble evolutionary algorithm

The research on optimal design of infinite-impulse response (IIR) filter design based on various optimization techniques, including evolutionary algorithms (EAs), has gained much attention in recent years. Previously, the parameters of digital IIR filters are encoded with floating-point representations. It is known that a fixed-point representation can effectively save computational resources and is more convenient for direct realization on hardware. Inherently, compared with the floating-point representation, the fixed-point representation would make the search space miss much useful gradient information and therefore, surely rises new challenges for continuous EAs. In this paper, we first analyze the fitness landscape properties of optimal digital IIR filter design. Based on the fitness landscape investigation, a two-stage ensemble evolutionary algorithm (TEEA) is applied to digital IIR filter design with fixed-point representation. In order to fully evaluate the performance of TEEA, we experimentally compare it with five state-of-the-art EAs on four types of digital IIR filters with different settings. Based on the experimental results, we can conclude that TEEA has higher convergence speed, better exploration, and higher success rate. In order to benchmark TEEA further, we apply it to some more difficult problems with shorter word length or higher order. We can find that TEEA can provide satisfying performance on these hard tasks as well.

Induced l∞ stability of fixed-point digital filters without overflow oscillations and instability due to finite word length effects

This article studies a new criterion for the induced l∞ stability of fixed-point state-space digital filters without overflow oscillations and instability due to finite word length effects. The criterion not only guarantees exponential stability but also reduces the effect of external interference to an induced l∞ norm constraint. We present a numerical example, which demonstrates the effectiveness of the proposed criterion.

A note on the criterion for the elimination of overflow oscillations in fixed-point digital filters with saturation arithmetic and external disturbance

A recently reported criterion for the exponential stability and H∞ performance of fixed-point digital filters with saturation arithmetic and external disturbance is reviewed. It is shown that there is a technical error in this criterion. A corrected version of the criterion is presented. Finally, a relaxed version of the criterion is made available.

Criterion for the elimination of overflow oscillations in fixed-point digital filters with saturation arithmetic and external disturbance

Abstract In this paper, a new criterion for the H ∞ elimination of overflow oscillations in fixed-point digital filters with saturation arithmetic and external disturbance is presented. The criterion not only guarantees exponential stability but also reduces the effect of external disturbance to an H ∞ norm constraint. The criterion takes the form of linear matrix inequality (LMI) and, hence, is computationally tractable. An illustrative example is given to demonstrate the effectiveness of the proposed criterion.

Noise gain expressions for low noise second-order digital filter structures

The quantization noise of a fixed-point digital filter is commonly expressed in terms of its noise gain, i.e., the factor by which the noise power q/sup 2//12 of a single quantizer is amplified to the output of the filter. In this brief, first a closed-form expression for the optimal second-order noise gain in terms of the coefficients of the numerator and denominator polynomials of the transfer function is derived. It is then shown, by deriving a similar expression for its noise gain, that the second-order direct form structure has an arbitrarily larger noise gain the closer the filter poles are to the unit circle. The main result, however, is that the wave digital form and the normal form structures have noise gains which are only marginally larger than the minimum gain. For these forms, the expressions for their noise gain in terms of the transfer function are given as well. The importance of these forms lies in the fact that they use less multipliers than the optimal structure and that they are much easier to design: properly scaled forms are given requiring no design tools.

A fast exhaustive search algorithm for checking limit cycles in fixed-point digital filters

The presence of limit cycles in fixed arithmetic implementations of digital filters can significantly impair their performances. This paper presents a fast algorithm to determine the presence or absence of such limit cycles and their exact maximum amplitude. This algorithm may be used for different arithmetic representations and for second-order section with one or two quantizers. Computer results are given to establish the feasibility of the algorithm, which may be helpful to designers by providing them a knowledge of when and where he must really resort to more complex filters structures and rounding strategies.

Comparison of fixed-point FIR digital filter design techniques

The multiplier block digital filter design algorithms recently introduced by the authors, are found to design superior filters, in terms of complexity minimization, to two well-established techniques, namely the sigma-delta coding of coefficients, and the cascading of simple sections using genetic algorithms.