IIR Filter Architectures with Truncation Error Feedback for ECG Signal Processing

Abstract

This work proposes fixed-point hardware architectures for two IIR filters, focusing on design specifications for ECG signal processing, using the truncation error feedback (TEF) to attenuate errors caused by truncation operations inside these recursive structures. The TEF is represented by modulo operation followed by a unit-delay operator and multiplication by a coefficient. In this work, the proposed TEF core consists of a hardware structure based on delay, right-shift and modulo operations. The TEF approach is applied to sequential and parallel IIR filter architectures with fixed and adaptive coefficients. The first structure comprises a first-order high-pass filter applied to attenuate low frequencies of the electrocardiogram (ECG) signal. The second one is a second-order infinite impulse response (IIR) adaptive notch filter used to attenuate power line interference signals. All dedicated architectures were described and simulated using VHDL and synthesized in Cadence environment using the 45 nm Nangate Open Cell Library to verify the results of the area, delay and power metrics. A simulated ECG signal was used as input to check the functionality of the filters. Our results indicate that the TEF approach was useful for both high-pass filter (HPF) and adaptive notch filter (ANF), and it can be a significant strategy to meet design specifications and dynamic performance of fixed-point digital filters. For the synthesis analysis, both HPF and ANF sequential filters had lower power and cell area figures but presented higher normalized power per sample and delay. In summation, the TEF approach enabled the use of fixed-point filters for ECG filtering without degrading their dynamic performance or increasing noise caused by truncation.