First-in First-out Buffer Research Articles

Modeling and Analysis of FPGA Accelerators for Real-Time Streaming Video Processing in the Healthcare Domain

Complex real-time video processing applications with strict throughput constraints are commonly found in a typical healthcare application. The video processing chain is implemented as Field-Programmable Gate Array (FPGA) accelerators (processing blocks) communicating through a number of First-In First-Out (FIFO) buffers. The FIFO buffers are made out of Block RAM (BRAM) and limited in availability. Therefore, a key design question is the optimal sizes of the FIFO buffers with respect to the throughput constraint. In this paper, we use model-driven analysis and detailed hardware level simulation to address the question of buffer dimensioning in an efficient way. Using a Cyclo-Static Dataflow (CSDF) model and an optimization method, we identify and optimize the FIFO buffers. The results are confirmed using a detailed hardware level simulation and validated by comparison with VHDL simulations. The technique is illustrated on a use case from Philips Healthcare Image Guided Therapy (IGT) on the imaging pipeline of an Interventional X-Ray (i XR) system.

Reduction of the supply current of single-flux-quantum time-to-digital converters by current recycling techniques

We have been developing superconducting time-of-flight mass spectrometry systems that utilize superconducting strip particle detectors and single-flux-quantum (SFQ) time-to-digital converters (TDCs). We previously demonstrated a 24-bit SFQ TDC with a 3 × 24-bit first-in first-out (FIFO) buffer using the AIST Nb standard process (STP2) with a time resolution of 100 ps. In this study, we improved the SFQ TDC by using a current recycling technique. The technique enables us to increase the FIFO buffer capacity without increasing the total supply current, and the result is an improvement of ion count rates. We designed and demonstrated the SFQ TDC with a 12 × 24-bit FIFO buffer, whose total supply current was reduced by 71% with the current recycling technique.

LaminarIR: compile-time queues for structured streams

Stream programming languages employ FIFO (first-in, first-out) semantics to model data channels between producers and consumers. A FIFO data channel stores tokens in a buffer that is accessed indirectly via read- and write-pointers. This indirect token-access decouples a producer’s write-operations from the read-operations of the consumer, thereby making dataflow implicit. For a compiler, indirect token-access obscures data-dependencies, which renders standard optimizations ineffective and impacts stream program performance negatively. In this paper we propose a transformation for structured stream programming languages such as StreamIt that shifts FIFO buffer management from run-time to compile-time and eliminates splitters and joiners, whose task is to distribute and merge streams. To show the effectiveness of our lowering transformation, we have implemented a StreamIt to C compilation framework. We have developed our own intermediate representation (IR) called LaminarIR, which facilitates the transformation. We report on the enabling effect of the LaminarIR on LLVM’s optimizations, which required the conversion of several standard StreamIt benchmarks from static to randomized input, to prevent computation of partial results at compile-time. We conducted our experimental evaluation on the Intel i7-2600K, AMD Opteron 6378, Intel Xeon Phi 3120A and ARM Cortex-A15 platforms. Our LaminarIR reduces data-communication on average by 35.9% and achieves platform-specific speedups between 3.73x and 4.98x over StreamIt. We reduce memory accesses by more than 60% and achieve energy savings of up to 93.6% on the Intel i7-2600K.

Two-Level FIFO Buffer Design for Routers in On-Chip Interconnection Networks

SUMMARY The on-chip interconnection network (OCIN) is an integrated solution for system-on-chip (SoC) designs. The buffer architecture and size, however, dominate the performance of OCINs and affect the design of routers. This work analyzes different buffer architectures and uses a data-link two-level FIFO (first-in first-out) buffer architecture to implement high-performance routers. The concepts of shared buffers and multiple accesses for buffers are developed using the two-level FIFO buffer architecture. The proposed two-level FIFO buffer architecture increases the utilities of the storage elements via the centralized buffer organization and reduces the area and power consumption of routers to achieve the same performance achieved by other buffer architectures. Depending on a cycleaccurate simulator, the proposed data-link two-level FIFO buffer can realize performance similar to that of the conventional virtual channels, while using 25% of the buffers. Consequently, the two-level FIFO buffer can achieve about 22% power reduction compared with the similar performance of the conventional virtual channels using UMC 65 nm CMOS technology.

Synthesis and Optimization of Pipelined Packet Processors

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> We consider pipelined architectures of packet processors consisting of a sequence of simple packet-processing modules interconnected by first-in first-out buffers. We propose a new model for describing their function, an automated synthesis technique that generates efficient hardware for them, and an algorithm for computing minimum buffer sizes that allow such pipelines to achieve their maximum throughput. Our functional model provides a level of abstraction familiar to a network protocol designer; in particular, it does not require knowledge of register-transfer-level hardware design. Our synthesis tool implements the specified function in a sequential circuit that processes packet data a word at a time. Finally, our analysis technique computes the maximum throughput possible from the modules and then determines the smallest buffers that can achieve it. Experimental results conducted on industrial-strength examples suggest that our techniques are practical. Our synthesis algorithm can generate circuits that achieve 40 Gb/s on field-programmable gate arrays, equal to state-of-the-art manual implementations, and our buffer-sizing algorithm has a practically short runtime. Together, our techniques make it easier to quickly develop and deploy high-speed network switches. </para>

All-optical autonomous first-in–first-out buffer managed with carrier sensing of output packets

A simple method for optical buffering management without electronic processing is proposed. The buffer system consists of feedback-looped parallel fibers as first-in–first-out buffers and an optical buffer manager. The buffering system has multiple input ports and one output port. The buffer stores incident packets in order of arrival. The manager controls stored packets and output switches of the buffers by sensing packet flow at the output port. The buffer system can be operated autonomously without an external controller. The buffer performance is evaluated with numerical simulation.

Consequences of parameter differences in a model of short-term persistent spiking buffers provided by pyramidal cells in entorhinal cortex

In previous simulations of hippocampus-dependent and prefrontal cortex-dependent tasks, we demonstrated the use of one-shot short-term buffering with time compression that may be achieved through persistent spiking activity during theta rhythm. A biophysically plausible implementation of such a first-in first-out buffer of short sequences of spike patterns includes noise and differences between the parameter values of individual model pyramidal cells. We show that a specific set of parameters determines model buffer capacity and buffer function, and individual differences can have consequences similar to those of noise. The set of parameters includes the frequency of network theta rhythm and the strength of recurrent inhibition (affecting capacity), as well as the time constants of the characteristic after-depolarizing response and the phase of afferent input during theta rhythm (affecting buffer function). Given a sufficient number of pyramidal cells in layer II of entorhinal cortex, and in each self-selected category of pyramidal cells with similar model parameters, buffer function within a category is reliable with category-specific properties. Properties include buffering of spikes in the order of inputs or in the reversed order. Multiple property sets may enable parallel buffers with different capacities, which may underlie differences of place field sizes and may interact with grid cell firing in a separate population of layer II stellate cells in the entorhinal cortex.

Implementation and application of first-in first-out buffers

First-in, first-out (FIFO) buffers load and unload data using separate clocks that may be incoherent. We explore the application of FIFOs to circular shift registers, serial memory, and data re-clocking. We describe two different FIFO implementations in RSFQ. One employs classic handshaking using the Muller C-element. The other employs physical back-pressure based on repulsion of stored single flux quanta in a JTL. Both implementations use seven Josephson junctions, and a single bias resistor, per cell. The bias resistor can be reduced to an arbitrarily low value, thereby eliminating static power dissipation.

An approximate analysis of the LRU and FIFO buffer replacement schemes

In this paper, we develop approximate analytical models for predicting the buffer hit probability under the Least Recently Used (LRU) and First In First Out (FIFO) buffer replacement policies under the independent reference model. In the case of the analysis of the LRU policy, the computational complexity for estimating the buffer hit probability is O ( KB ) where B is the size of the buffer and K denotes the number of items having distinct access probabilities. In the case of the FIFO policy, the solution algorithm is iterative and the computational complexity of each iteration is O ( K ). Results from these models are compared to exact results for models originally developed by King [KING71] for small values of the buffer size, B , and the total number of items sharing the buffer, D . Results are also compared with results from a simulation for large values of B and D . In most cases, the error is extremely small (less than 0.1%) for both LRU and FIFO, and a maximum error of 3% is observed for very small buffer size (less than 5) when the access probabilities are extremely skewed. To demonstrate the usefulness of the model, we consider two applications. In our first application, we compare the LRU and FIFO policies to an optimal static buffer allocation policy for a database consisting of two classes of data items. We observe that the performance of LRU is close to that of the optimal allocation. As the optimal allocation requires knowledge of the access probabilities, the LRU policy is preferred when this information is unavailable. We also observe that the LRU policy always performs better than the FIFO policy in our experiments. In our second application, we show that if multiple independent reference streams on mutually disjoint sets of data compete for the same buffer, it is better to partition the buffer using an optimal allocation policy than to share a common buffer.

Queueing in high-performance packet switching

The authors study the performance of four different approaches for providing the queuing necessary to smooth fluctuations in packet arrivals to a high-performance packet switch. They are (1) input queuing, where a separate buffer is provided at each input to the switch; (2) input smoothing, where a frame of b packets is stored at each of the input line to the switch and simultaneously launched into a switch fabric of size Nb*Nb; (3) output queuing, where packets are queued in a separate first-in first-out (FIFO) buffer located at each output of the switch; and (4) completely shared buffering, where all queuing is done at the outputs and all buffers are completely shared among all the output lines. Input queues saturate at an offered load that depends on the service policy and the number of inputs N, but is approximately 0.586 with FIFO buffers when N is large. Output queuing and completely shared buffering both achieve the optimal throughput-delay performance for any packet switch. However, compared to output queuing, completely shared buffering requires less buffer memory at the expense of an increase in switch fabric size.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A device for spike train sampling with built-in memory

The described interface to a digital computer measures interspike interval durations with a resolution of 10 μs. A built-in first-in first-out (FIFO) memory relieves the host computer from frequent I/O intensive tasks. The internal FIFO buffer can store up to 512 data words (wordlength is 16 bit) and works on the dual-port principle. This way the acquisition of a neuronal spike train is completely independent of the computer's simultaneously ongoing data access. A simple handshake protocol between the interface and the computer prevents any overhead communication. The buffer architecture of the instrument releases the host computer from high speed I/O handling schemes like real-time, clock-controlled, polling or interrupt procedures, that would request assembly language support. The body of two software, driver routines in the BASIC and the PASCAL language is presented. A complete and detailed schematic diagram of the circuitry is included.

A Tool for Structured Functional Simulation

BLOSIM is a general purpose time-driven (as opposed to event-driven) simulation language. It is written in C language, and is intended to provide a highly structured environment for simulations, thereby making practical the accumulation of libraries of simulation routines which can be reused and making multiprogrammer simulation efforts more practical. It is written with the philosophy of not including any simulation primitives within the language itself, but rather complete generality is maintained by having the user provide these as C routines (either coded from scratch or from a user-provided library). It includes as features a hierarchical specification of blocks, interconnection of blocks by first-in first-out buffers, the passing of parameters to blocks, multiple instances of blocks, and automatic scheduling of the order of block execution. It has been used for the multiprogrammer simulation of data transmission and speech processing systems, in both academic and industrial environments, with good results.