Finite Word Length Research Articles

An algorithm for the design of optimal finite wordlength FIR filters

In practical FIR digital filter applications it is often necessary to represent the filter coefficients with a finite number of bits. The finite wordlength coefficient restriction reduces the filter quality and increases the filter deviation. This increase can be reduced substantially if the optimal finite wordlength coefficients are used. Computing these coefficients is more difficult and can be slow. It was shown before that the computation time can be significantly reduced with the help of a lower bound on the deviation increase. Derivation of a new algorithm that uses a much better lower bound is the purpose of this paper. We consider the general case of a length N filter with a discrete set of allowable real coefficients and demonstrate the effectiveness of the new algorithm on a set of filter design cases. The results show that this algorithm reduces the computation times up to 3 times when compared with the previously best results.

BFT—Low-Latency Bit-Slice Design of Discrete Fourier Transform

Structures for the evaluation of fast Fourier transforms are important components in several signal-processing applications and communication systems. Their capabilities play a key role in the performance enhancement of the whole system in which they are embedded. In this paper, a novel implementation of the discrete Fourier transform is proposed, based on a bit-slice approach and on the exploitation of the input sequence finite word length. Input samples of the sequence to be transformed are split into binary sequences and each one is Fourier transformed using only complex sums. An FPGA-based solution characterized by low latency and low power consumption is designed. Simulations have been carried out, first in the Matlab environment, then emulated in Quartus IDE with Intel. The hardware implementation of the conceived system and the test for the functional accuracy verification have been performed, adopting the DE2-115 development board from Terasic, which is equipped with the Cyclone IV EP4CE115F29C7 FPGA by Intel.

Modeling and Simulation of a Micro strip Antenna in Annular Geometry

In the last decade, the study of multidimensional systems for signal filtering purpose has attracted the attention of many research teams, which are motivated by various interesting real world applications such Image processing, video signal filtering processing, video signal filtering Computational tomography, distributed parameters systems. The representation of the state space realization for two-dimensional (2D) filters by a transfer function, with minimal delays is a crucial problem; the minimal realization can avoidmathematical complexities as well as technical benefit to hardware requirement. Unfortunately, it is not possible to find the minimal state space realization for every 2D system other than the 1D system, but we can find it for a specific cases of all-pole or the all-zero. Lattice filter is classified as an important structure in digital signal processing. In fact, it minimizes the computation complexity, reduces the finite word length and requires less hardware compared to the direct form digital filter with similar design specifications. The authors in two delay units z1-1 , z2-1 are used. In this paper we propose a new lattice-ladder structure of 2-D digital filter, composed of a delay units z1-1 and a basic lattice section z1 and z2-1 - Using matrix representation of the basic lattice sections and we derived transfer functions of the proposed 2-D digital ladder-lattice filters. The proposed structure is composed by a minimal number of delays and a minimal number of basic lattice sections. Furthermore, we have considered the description of the proposed lattice structure by using a state-space n-D Roesser form description presented in below and the implementations suggested by the authors in literatures. Besides, the state space equations for 2-D digital filter are presented, where the dimension of the matrices of the proposed lattice structure verify the minimal state space realization. The remainder of the paper is organized as follows; first is devoted to the proposed -D lattice-ladder structure and realization and in the second is dedicated to the state space realization. As conclusion this work has allowed us to approach a field that has experienced a great growth in recent years which is constantly evolving in order to improve, understanding and control the complex systems and processes that surround us.

Performance evaluation of infinite impulse response filter synthesis using parallel-Direct-Ladder form under finiteword-Length effects

Synthesizing a parallel-form IIR filter from a given non-strictly-proper transfer function requires a polynomial long division method, which results in dynamical range problem under finite word-length (FWL) fixed-point implementations. Based on the state-space similarity transformation, in this paper, a synthesis scheme for parallel-form IIR filters is proposed without requiring long division of polynomials operations to reduce dynamical range problems for obtaining parallelized first or second-order sections either in direct-form or coupled-form. The main advantage of the proposed scheme is that the parallelized IIR filter can be synthesized based on state-space normal-form similarity transformation from any digital filter transfer functions. In addition, the proposed two modified coupled-form filters based on the parallelized IIR filter have benefits of less computational consumption and zero-input limit-cycle free, especially for modified second-order coupled forms in contrast with the conventional coupled-form biquad. Finally, two numerical examples are performed to illustrate the effectiveness of the proposed scheme.

A unified approach for digital realization of fractional order operator in delta domain

The fractional order operator (s?a,0 < a <1) plays the pivotal role for the realization of fractional orders systems (FOS). For the realization of the FOS, fractional order operator (FOO) needs to be realized either in discrete or continuous time domain. Discrete time rational approximation of FOO in the z -domain fails to provide meaningful information at fast sampling interval. Moreover, z domain rational transfer function becomes highly sensitive with respect to its coefficients variation resulting to the poor finite word length effects for digital realization. In the other hand delta operator parameterized system allows to develop unification of continuous and discrete time formulations leading to the development of a unified framework for digital realization at fast sampling interval. The discrete time approximation of the FOO in delta domain is found to be robust to its coefficient variation in comparison to the shift operator based discretization of FOO. In this paper, discrete d -operator parameterization is proposed for the digital realization using direct discretization of FOO. As a result, superior finite word length effect is observed for the realization of the FOO in discrete delta domain. Fractional order operator with different orders (a ) are considered for the realization purpose using the proposed method and the results obtained using MATLare presented for validation.

Design of FRM-Based Nonuniform Filter Bank With Reduced Effective Wordlength for Hearing Aids.

This paper presents a design method for frequency response masking (FRM)-based nonuniform filter bank with reduced effective wordlength. Instead of designing prototype filters separately, we propose to model the filter bank design problem as a nonlinear programming problem and jointly design the prototype filters in the FRM structure. Moreover, in this work, all the filters are designed directly in the finite wordlength space, such that they can be directly implemented using efficient fixed-point arithmetic without any quantization. By simultaneously considering all the subband constraints during optimization, the proposed method is able to guarantee the desirable stopband attenuation for all subbands and achieve optimal effective wordlength (EWL) for the coefficients, reducing the hardware complexity for very large-scale integration (VLSI) implementation. Experimental results show that the hardware complexity of filter banks can be reduced without sacrificing the audiogram compensation performance for hearing aid applications.

The topography of zeros and poles of a third order IIR digital filter with finite word length in the z-plane

Earlier it was found that the zeros and poles of IIR digital filters with finite word length are elements of the set of algebraic numbers. Therefore, not every point of the unit circle of the z-plane can be a zero and / or a pole of such digital filters. The position of admissible positions for zeros and poles depends on the degree of algebraic numbers and the length of the fractional part of the coefficients of the equivalent canonical structure of the corresponding order. The formation of the corresponding configurations is considered as a z-plane discretization due to the quantization of the filter coefficients. The z-plane discretization for second-order filters has been well studied. The geometric locus of the corresponding algebraic numbers is a system of concentric circles, that is, plane algebraic curves of the second degree. This paper presents the results of studying the geometrical place of the third order IIR filter zeros and poles.

Limit Cycle-Free Realization of Discrete-Time Delayed Systems with External Interference and Finite Wordlength Nonlinearities

Limit Cycle-Free Realization of Discrete-Time Delayed Systems with External Interference and Finite Wordlength Nonlinearities

Exact Analysis of the Finite Precision Error Generated in Important Chaotic Maps and Complete Numerical Remedy of These Schemes

A first aim of the present work is the determination of the actual sources of the “finite precision error” generation and accumulation in two important algorithms: Bernoulli’s map and the folded Baker’s map. These two computational schemes attract the attention of a growing number of researchers, in connection with a wide range of applications. However, both Bernoulli’s and Baker’s maps, when implemented in a contemporary computing machine, suffer from a very serious numerical error due to the finite word length. This error, causally, causes a failure of these two algorithms after a relatively very small number of iterations. In the present manuscript, novel methods for eliminating this numerical error are presented. In fact, the introduced approach succeeds in executing the Bernoulli’s map and the folded Baker’s map in a computing machine for many hundreds of thousands of iterations, offering results practically free of finite precision error. These successful techniques are based on the determination and understanding of the substantial sources of finite precision (round-off) error, which is generated and accumulated in these two important chaotic maps.

Exponential Stability Analysis of Fixed Point Interfered Nonlinear Digital Systems in the Presence of Quantization and Overflow Constraints

Finite word length is a practical limitation when discrete-time systems are implemented by using digital hardware. This restriction degrades the performance of a discrete-time system and may even lead it toward instability. This paper, addresses the stability and disturbance attenuation performance analysis of nonlinear discrete-time systems under the influence of energy-bounded external interferences when such systems are subjected to quantization and overflow effects of fixed point hardware. The proposed methodology, in comparison with previous paper, describes exponential stability for the nonlinear discrete-time systems by considering composite nonlinearities of digital hardware. The proposed criteria that ensure exponential stability and [Formula: see text] performance index for the digital systems under consideration are presented in the form of a set of linear matrix inequalities (LMIs) by exploiting Lyapunov stability theory, Lipschitz condition and sector conditions for different types of commonly used quantization and overflow arithmetic properties, and the results are validated for recurrent neural networks. Furthermore, novel stability analysis results for a nonlinear discrete-time system under hardware constraints can also be observed as a special case of the proposed criteria.

Overview of Factorisation Methods in Kalman Filtering

Abstract The paper summarises and describes the most commonly used matrix factorisation methods applied in design of the Kalman filter in order to improve computational efficiency and avoid divergence issues caused by numerical round-off and truncation errors. Some forms of the Kalman filter are more prone to the growth of numerical error sand possible divergence than other implementations. In order to prevent the algorithm’s divergence additional processing is needed and this paper discusses pros and cons of different implementations and their numerical characteristics. Numerical issues still arise in finite word length implementations of algorithms, which frequently occur in embedded systems. This paper describes algorithms based on different factorisations such as Cholesky, U-D, SVD and their basic numerical properties.

Delay partitioning approach to the robust stability of discrete-time systems with finite wordlength nonlinearities and time-varying delays

This paper is associated with the problem of robust stability of discrete-time systems with time-varying delays and finite wordlength nonlinearities. The main contribution of the paper is two-fold. First, this paper presents a new Lyapunov function based on the idea of partitioning the delay interval into subintervals. The approach may be considered as an advancement over the several existing approaches where only the lower delay bound is partitioned. The second is that reciprocally convex inequality (RCI) and Wirtinger-based inequality (WBI) are used to estimate the sum terms involved in the forward difference of Lyapunov function. The intermediate delay is also included in the Lyapunov function to deal with the delay information more effectively. Finally, several examples are provided to illustrate the less conservatism of the proposed approach as compared to several existing results.

Design of Infinite Impulse Response Filter Using Fractional Derivative Constraints and Hybrid Particle Swarm Optimization

In this paper, a new method for designing digital infinite impulse response filter with nearly linear-phase response is presented using fractional derivative constraints (FDC). The design problem is constructed as a phase optimization problem between the desired and designed phase response of a filter. In order to achieve the highly accurate passband (pb) response, phase response is fitted to desired response more precisely using FDC, due to which design problem becomes a multimodal error surface that is constructed from sum of passband error (ep) and stopband error (es). Optimal value of FDC is accomplished by minimizing the total error (er0) using improved swarm-based optimization technique, which is formulated by associating the scout bee mechanism of artificial bee colony algorithm with particle swarm optimization and termed as hybrid particle swarm optimization. The simulated results reflect that the improved response in passband along with better transition width is achieved using the proposed method. It is observed that about 90–99% of improvement in passband error can be achieved with 100% reduction in maximum passband ripple. However, slight reduction in stopband attenuation (As), in some cases, results within the permissible limit. The designed filters using this method are also stable toward finite word length effect.

Formal Non-fragile Verification of Step Response Requirements for Digital State-Feedback Control Systems

We describe and evaluate a novel approach to formally verify whether a digital control system meets specifications related to step response parameters. In particular, we obtain a state feedback controller designed for a system represented by a state-space model. Then, we analyze whether its required specifications regarding settling time and maximum overshoot are met, using both open- and closed-loop forms and considering finite-word-length (FWL) effects for the latter. We developed our verification approaches inside DSVerifier, which is a verification tool that employs bounded (and unbounded) model checking based on satisfiability modulo theories. Thus, DSVerifier checks performance requirements of digital control systems considering fragility, such as round-off and numerical quantization errors. Our approaches were also evaluated over a set of standard control-system benchmarks extracted from the control literature. Experimental results show that DSVerifier can check settling time and overshoot in control systems suffering from FWL effects, while other existing approaches routinely ignore those issues.

Robust and Computationally Efficient Digital IIR Filter Synthesis and Stability Analysis Under Finite Precision Implementations

In this paper, an analytical synthesis method for obtaining an optimal infinite impulse response (IIR) state-space realization, say minimal pole-zero and pole-L2 sensitivity realizations, based on minimizing zero/L2 sensitivity measures subject to sparse normal-form state transition matrix is proposed. The proposed nth order realization possesses strong robustness and at most only 4n + 1 multiplications per output sample to prevent instability and output distortion, as well as to keep computational efficiency under finite word-length (FWL) effects. This is important for the IIR filter implemented in fixed-point and portable digital devices. In this paper, the proposed pole-L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> sensitivity minimization method, an alternative approach of pole-zero sensitivity minimization, may solve the issue of zero multiplicity. A normal-form realization has been proven that it can achieve a global minimum of un-weighted pole sensitivity measure as well as zero-input limit-cycle free property. The sparse normal-form realization can be synthesized from an arbitrary initial realization with distinct poles by using an analytical similarity transformation. Based on the derived fixed-point arithmetic model in state-space realizations, the Bellman-Gronwall Lemma, and normal-form transformation, a new word-length estimation to guarantee stability is derived. Finally, numerical simulations are performed to verify the correctness and the effectiveness of the theoretical results.

Design and Realizations of Networked Estimators: A Descriptor Model Approach

This paper addresses the design and realization of a networked estimator, which requires further digital implementation using several subsystems. Implementation on a digital process entails finite word length effects on the coefficients’ representation, and a multiple-subsystem architecture also introduces internal time delays in the information interaction. Dealing with these intrinsic defects requires finding a resilient realization. A corresponding descriptor model-based approach is thus constructed to describe the internal time delays and equivalent realizations with finite word length effects in a unifying framework, which enables simultaneous consideration of design and realization. Based on the obtained descriptor model, a stability analysis condition is deduced and a design method for the estimator is further obtained. An algorithm is also proposed for finding the optimal realization requiring the minimum word length for stabilization. Finally, a simulation with two cooperative robots is considered to illustrate the effectiveness of the results.

Loop Shaping by Single-Resonant Controllers for Prescribed Tracking of Sinusoidal References

It is well-known that in ac-grid-connected or motor-driving converters, current behavior directly sets the exchange of power between the two. Moreover, in corresponding current plants, most of the disturbance (formed by grid voltage or back EMF and the dc-link voltage) may be measured/estimated and appropriately canceled, reducing the current regulation problem to tracking challenge only. The latter is still of extreme importance since the amount of active/reactive power exchanged is proportional to current magnitude and phase. Recently, a method for deriving proportional-resonant controller structure and coefficients according to desired tracking behavior of ac signal amplitude, applied to typical power converter current loop, was proposed based on the fact that if ac signal envelope is perceived as dc signal, its transient behavior may be easily shaped utilizing well-known approaches employed in dc systems loop shaping while keeping zero phase tracking error at all time. This paper extends the proposed methodology by introducing in-depth analysis of the resulting loop gain shaping, applying practical issues, such as actuator delay, damping, and finite word length to the system, yielding a closed set of hands-on design guidelines. Experimental results are also given, providing a two-fold value: successfully validating the presented material and demonstrating that some of the previously reported outcomes (based on simulations) cannot be achieved in practice due to the above mentioned real world constraints.

Verifying fragility in digital systems with uncertainties using DSVerifier v2.0

Control-system robustness verification with respect to implementation aspects lacks automated verification approaches for checking stability and performance of uncertain control systems, when considering finite word-length (FWL) effects. Here we describe and evaluate novel verification procedures for digital systems with uncertainties, based on software model checking and satisfiability modulo theories, named as DSVerifier v2.0, which is able to check robust stability of closed-loop control systems with respect to FWL effects. In particular, we describe our verification algorithms to check for limit-cycle oscillations (LCOs), output quantization error, and robust non-fragile stability on common closed-loop associations of digital control systems (i.e., series and feedback). DSVerifier v2.0 model checks new properties of closed-loop systems (e.g., LCO), including stability and output quantization error for uncertain plant models, and considers unknown parameters and FWL effects. Experimental results over a large set of benchmarks show that 35%, 34%, and 41% of success can be reached for stability, LCO, and output quantization error verification procedures, respectively, for a set of 396 closed-loop control system implementations and realizations.

Design of Bandpass and Bandstop Infinite Impulse Response Filters Using Fractional Derivative

In this paper, a new design method for digital bandpass and bandstop infinite impulse response filters with nearly linear-phase response is proposed. In this method, the phase response of an all-pass filter is optimized in the frequency domain to yield less passband error ${\text{Er}}_{p}$ and stopband error ${\text{Er}}_{s}$ with optimal stopband attenuation $A_{s}$ . To achieve high accuracy in passband and stopband regions, fractional derivative (FD) constraints are evaluated in the respective regions, and the filter coefficients are computed using the Lagrange multiplier method. The behavior of fidelity parameters measured in terms of ${\text{Er}}_{p}{,\text{Er}}_{s}$ , and phase error ${\text{Er}}_{{\text{ph}}}$ is multimodel w.r.t. FD values. Therefore, modern heuristic technique, known as cuckoo search optimization is used for determining the optimal value of FDs and reference frequency simultaneously to minimize the fitness function, which is constructed as a sum of the squared error in passband and stopband. The designed filter yields up to 60% reduction in ${\text{Er}}_{p}$ and ${\text{Er}}_{{\text{ph}}}$ in the case of bandpass filter. Meanwhile, the response of filter is not degraded due to the finite word length effect.

Simultaneous Estimation of Moving-Vibration Parameters by Sliding Goertzel Algorithm in PLL Technique

Sliding Goertzel DFT algorithm in phase-locked loop technique is proposed for simultaneous estimation of moving-vibration parameters: amplitude, frequency, and velocity. The proposed algorithm is derived from the standard sliding discrete Fourier transform where its computation complexity is reduced by inserting a pole–zero pair in the system function. A damping factor is introduced in the system function to stabilize when discrete Fourier transform (DFT) is computed with limited finite word length precession. It allows the system poles to lie within unit circle of the $z$ plane and confirms a stable system. Furthermore, an adaptive sampling control is achieved as the sampling pulse duration varies according to carrier frequency deviation. An appropriate figure of merit is selected for the system function to reduce the noise effects in the input signal and to accept large range of measurement. Simulation investigation confirms the capability of the proposed technique to extract information even in the presence of large noise.