Finite Impulse Response Structure Research Articles

Confidence set-membership FIR filter for discrete time-variant systems

In this paper, a confidence set-membership filter based on the finite impulse response (FIR) structure is proposed for time-variant systems that are simultaneously subject to both the unknown but bounded noises and the Gaussian noises. At each step, the filter provides a confidence state set that includes the true state with an adjustable confidence level. The FIR structure improves the robustness and brings more degrees of freedom to the filter design. Multiple recent measurements within a moving horizon are fully utilized to construct and optimize each confidence state set. Under two different size criteria, an analytical solution and an LMI-based numerical solution for the filter gain are derived by minimizing the size of the confidence state set, respectively. Finally, an example is given to illustrate the effectiveness and superiority of the algorithms.

Gerchberg-Saxton Based FIR Filter for Electronic Dispersion Compensation in IM/DD Transmission Part I: Theory and Simulation

Intensity-modulation and direct-detection (IM/DD) transmission over short-reach optical fiber links, require electronic dispersion compensation (EDC) at the transmitter and/or electronic equalization at the receiver. Recently, the iterative Gerchberg-Saxton (GS) algorithm was demonstrated for EDC in IM/DD systems, through treating the amplitude at the transmitter and the phase prior-to the direct detection receiver as a degree of freedom. In Part I of this work, three GS approaches using finite impulse response (FIR) filters for EDC in IM/DD systems are demonstrated. The first two are closely related and rely on a cascaded FIR structure, while the third offers a novel non-iterative EDC solution using a single GS optimized static FIR filter. This is achieved through decoupling pattern dependent aspects of transmission from the GS iterations by targeting a single impulse at the DD receiver. With every successive iteration an impulse response for the GS filter emerges and sets the FIR tap weights. It is also demonstrated that closed-form analytical expressions for the GS filter impulse response can be obtained through small-signal frequency-domain analysis. The FIR filter is simulated using 8-bit finite-precision arithmetic. An adaptive <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$T$</tex-math></inline-formula> -spaced post feed-forward equalizer (FFE) is utilized for mitigating residual chromatic dispersion. It is shown, that a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$T/2$</tex-math></inline-formula> -spaced pre-EDC FIR filter with 417 taps can support 56 Gb/s non-return-to-zero (NRZ) on-off keying (OOK) transmission over 80 km of single mode fiber (SMF) with a chirp-free Mach-Zehnder modulator (MZM). Part II, presents experimental demonstration of the non-iterative GS FIR filter proposed and simulated in this article.

Digital filters windowing for data transmission enhancement in communication channel

In this search, an important methodology has been presented for communicated information rectification utilizing advanced channel windowing approach. The modern data communication technologies are ensured with numerous challenges because of their unpredictability and arrangement. Various digital transmission topologies in 4G can't fulfill the requirements in future arrangements, therefore, alternative multicarrier modulation (MCM) becoming the nominated approaches among all other data transmission techniques. Wherein prototype filter configuration is a fundamental system based on which the synthesis and analysis filters are derived. This paper presents a complete review on the ongoing advances of finite impulse response (FIR) filter plan procedures in MCM based correspondence frameworks. Initially, the essential issues are tried, taking into consideration the presentation of available data signal applicants and the FIR filter design concept. At that point the techniques for FIR filter configuration are summed up in subtleties and are center around the accompanying three group’s recurrence testing strategies, windowing based strategies and advancement-based techniques. At last, the exhibitions of different FIR structure strategies are assessed and measured by power spectral density (PSD) and bit error rate (BER), and variable MCM plots as well as their potential prototype filters are examined.

Forward–Backward Smoothers With Finite Impulse Response Structure

State estimation is an important component for advance control and fault detection. This paper addresses the problem of smoother design for state estimation based on a finite number of measurements collected in a finite estimation horizon. Three different finite impulse response (FIR) smoothing algorithms are proposed using the maximum likelihood FIR estimation, which is robust against uncertain noise statistics and model parameters, and also independent of the initial states of each finite horizon. Moreover, we provide equivalent but iterative Kalman-like structures of these algorithms for practical implementation. The applications of the proposed smoothing algorithms to an object tracking and image processing examples are demonstrated, and it shows that they have better robustness against model uncertainties than traditional smoothing approaches.

Systolic architecture for adaptive block FIR filter for throughput using distributed arithmetic

In this paper, the design of distributed arithmetic (DA) finite impulse response (FIR) filter using block least mean square algorithm (BLMS) based on systolic array architecture with parallel data processing units is presented. A high level of parallelism is observed in the proposed work, improving the efficiency of variable coefficient FIR structure. The parallel look-up tables (LUT) in combination with the shift accumulator emulate multiply and accumulate operations. In order to reduce the number of clock cycles, B parallel LUTs are used, where B is the coefficient size. The block processing in BLMS Adaptive FIR Filter of block length L gives L times high throughput. This structure accepts block of input samples and generates block of output in each clock cycle. It requires less number of registers for computing filter output response and weight increment vector as memory reuse concept is used for implementing registers. This structure doesn’t require multiplexer. The designed DA based FIR filter is implemented on FPGA. The implementation results shows that the manuscript presents a high speed and low power architecture. The proposed structure provides 17.3 times less power and 9.5 times increase in throughput when compared to existing designs.

An Improved VLSI Design of the ALU Based FIR Filter for Biomedical Image Filtering Application.

FIR filter is the most widely used device in DSP applications, which is also applicable to integrate with image processing approaches. The ALU based FIR structure is applicable for various devices to increase the performance. The ALU design operation includes accumulation, subtraction, shifting, multiplication and filtering. Existing methods are designed with various multipliers like Wallace tree multiplier, DADDA multiplier, Vedic multiplier and adders like carry select adder, and carry look-ahead adder. The main objective is to reduce the area, delay and power factors since optimum VLSI circuit is employed in this paper. By these adders and multipliers, operations are independently enabling main operations in DSP. The FIR filter is designed using a MAC unit with clock regenerative comparators. In the field of the VLSI industry, the low power, reduced time, and area-efficient designs are mostly preferred for various applications. Adders and multipliers play a vital role in VLSI circuit designs. The recent electronics industry uses a digital filter for various real-time applications. This utilizes Finite Impulse Response (FIR) and Infinite Impulse Response (IIR) filters, here the FIR filter is most stable than IIR filter. This FIR filter indicates the impulse signal into finite form and it is used mainly in DSP processors for getting high-speed. In these two ALU and FIR circuits, the adders and multiplier block's usage is increased, it consumes much power. The proposed research work uses the clock-gating technique for reducing power consumption. Here the latch-based clock gating technique provides an efficient result. XOR-based logic circuit reduces the design complexity and utilizes the less area. Carry save accumulator is a digital adder used for addition. It provides the two set of output, which is partial sum and carry output. The ripple carry adder uses a full adder circuit for its operation. It propagates the carry value in the last bit. In addition, the combination of CSA and RCA utilizes less area, high speed and provides the better throughput. In multiplier block, the booth multiplier algorithm is used with XOR-based logic. Here this proposed FIR filter is designed for performing image filtration of retina image. This process improves the better visualization approach inthe medical field. Thus, the proposed ALU based FIR filter with a latch-based clock gating technique is designed and analyzed with various parameters. Here the modified adders and multipliers are proposed for the efficiency of the system. The modified carry save adder is proposed with combining ripple carry adder logic for improving the adders' performance. The enhanced booth multiplier is designed using add and shift method for reducing the numberof stages to calculate the result. This process is applied to perform image processing of the retina image. After designing the ALU based FIR filter structure in the VLSI environment, the image is loaded on the MATLAB as the .png format, then it is converted into a hex file, which is read from the Xilinx to perform filtering the process. Then the 'dataout' is converted into a binary file to obtain the result of the filtering process. The enhanced booth multiplier reduces the delay by reducing the number of stages to calculate the result. Here the clock gating technique is proposed with the latch-based design for reducing the dynamic and clock power consumption. The number of adder's circuit in both ALU and FIR circuits is less since it improves the overall efficiency of the system. Thus, the proposed methodology concluded that the design and analysis of ALU based FIR filter for medical image processing give the efficient result on the way of achieving the factors such as power (Static & Dynamic), Delay (Path delay) area utilization, MSE and PSNR. Here the image processing of FIR results to MSE and PSNR values, which obtained a better result than the existing VLSI based image processing works. The latch-based clock gating circuit is connected with the proposed circuit, based on the gated clock signal, it optimizes the gated circuit of the whole design since it also reduces the error and provides the efficient power report. This proposed VLSI model is simulated using Xilinx ISE 14.5 and Modelsim synthesizes it; here with the help of MATLAB, with the adaptation of the 2018a tool, the image filtering was done.

Comprehensive Survey of FIR-Based Sample Rate Conversion

Sample rate conversion (SRC) is ubiquitous and critical function of software defined radio and other signal processing systems (speech coding and synthesis, computer simulation of continuous-time systems, etc..). In this paper, we present a survey on linear phase finite impulse response (FIR) based sampling rate conversion. Many different FIR-based SRC solutions exist, such as classical FIR, polyphase, Farrow, cascaded-integrator-comb, and Newton structures. Each one of these solutions is presented differently in the literature, and SRC reference books introducing the subject are often missing hardware implementation aspects. The main objective of this paper is to provide a simple and comprehensive overview of main FIR-based SRC techniques from theoretical to hardware implementation aspects. The state of the art of FIR-based SRC filters is summed-up through a concise derivation of the different solutions from a common root: linear phase FIR filters. Each SRC solution is presented from both theoretical and practical implementation points of view. The paper provides a succinct tutorial that introduces SRC, and helps identifying and implementing the appropriate FIR-based SRC architecture for any given applications.

Type II, III, and IV Linear-Phase FIR Structures Based on Cardinal Filters

Novel structures of type II, III, and IV linear-phase finite impulse response (FIR) systems are proposed. It is constituted of a linear combination of basic sub-filters, called cardinal filters , with weighting coefficients equal to the derivatives of the system amplitude response at a prescribed frequency. Since the cardinal filters can be synthesized via recursive closed-form expressions, regardless of the desired system amplitude response, the proposed structure provides a universal design for arbitrary derivative-constrained linear-phase FIR filters. Design examples of maximally flat filters show that further improvement by combining derivative constraints with the least squared error optimization technique can be obtained.

An Improved Iterative FIR State Estimator and Its Applications

In this paper, an iterative finite impulse response (FIR) filter is proposed for discrete time-varying state-space models, with the purpose of a new initialization strategy for the iterative FIR structure as well as consideration of possible unexpected state dynamics in a finite horizon. A compensation variable that satisfies the Gaussian property is introduced into the state equation, and its probability density function (pdf) is estimated analytically together with the pdf of state variable using the variational Bayesian inference technique. Different from the existing methods, the proposed filter exploits the FIR structure from the perspective of pdf propagation, which provides a new efficient way to use the iterative FIR filtering structure without any particular initialization scheme. Moreover, the effects of uncertainties (caused by initialization and/or possible unmodeled state dynamics) on the filtering output are loosened adaptively. Two examples of applications demonstrate that the proposed algorithm can not only provide optimal estimates when the model used perfectly matches the measurements, but can also exhibit better robustness than the Kalman filter, optimal FIR filter, maximum likelihood FIR filter, and some commonly used robust and/or adaptive Kalman filters when the underlying process suffers from unpredicted uncertainties.

A variable‐step size NLMS algorithm based on the cross‐correlation between the squared output error and the near‐end input signal

In this work, we introduce an adaptive variable‐step size normalized least mean squares algorithm to be used in finite impulse response structures. In our proposal, the step size is adjusted according to the cross‐correlation between the squared output error of the adaptive filter and the near‐end input signal. We show that the step increases or decreases as the error increases or decreases. This behavior is used to update the filter coefficients in the proposed adaptive filter. The proposed algorithm is named VSS‐CR, after variable step size based on cross‐correlation. This proposal was evaluated using computer simulations, and the obtained results show that it achieves higher levels of echo return loss enhancement and less misalignment than other algorithms. We identified a trade‐off between steady‐state performance and convergence time; the VSS‐CR achieves higher levels of echo reduction, but it takes some more time to reach its mean square error steady‐state value. This algorithm can be used in acoustic echo canceling in public switched telephone networks. © 2019 Institute of Electrical Engineers of Japan. Published by John Wiley &amp; Sons, Inc.

Robust FIR State Estimation of Dynamic Processes Corrupted by Outliers

The outlier is a common issue in the design of state estimators for an industrial process. In this paper, a robust finite impulse response (FIR) filter is proposed for time-invariant state-space models with its noise following the Student's $t$ distributions. A batch solution is first derived by maximizing the likelihood, and then, an equivalent iterative realization is given to provide a clearer insight into the FIR structure. It shows that the essence of the proposed approach is the convergence of the maximum likelihood estimates in horizon scale through iterations, and the state estimate at each sampling instant is independent of the degree-of-freedom (DOF) parameter of the Student's $t$ distribution. Based on this, a modified algorithm that updates the DOF parameter in each iteration is further proposed. Applications to a moving target tracking example and a 3-DOF helicopter system demonstrate that the proposed methods can exhibit good immunity against outliers during the filtering.

Robust Estimation and Tracking of Power System Harmonics Using an Optimal Finite Impulse Response Filter

In this paper, a robust estimation method for estimating the power system harmonics is proposed by using the optimal finite impulse response (FIR) filter. The optimal FIR filter is applied to the state space representation of the noisy current or voltage signal and estimates the magnitude and phase-angle of the harmonic components. Due to the FIR structure, the FIR filter is more robust against model uncertainty than the Kalman filter. Hence, the FIR filter-based method will give a more robust solution for the power system harmonic estimation than the previous Kalman filter-based approaches. The performance and robustness of the proposed method are verified through simulation. Moreover, the proposed method is employed in the power conditioning system to estimate the harmonic components and total harmonic distortions.

Realization of a Finite Impulse Response Pulse Shaping Filter for Ultra-Wide Band Electronic Communication System

This paper has addressed the problem to design the Finite Impulse Response (FIR) filter for a pulse shaper used in electronics communication systems for a frequency band of 3.1 to 10.6 GHz, which is unlicensed indoor UWB. Therefore unlikely from the previous approaches, an LSE combined pulse which is a procedural grouping of the initial fifteen higher time offshoots of a Gaussian pulse has been used to obtain desired pulse shape. The impulse outcome of the system doing pulse shaping has been cross validated against FCC indoor channel emission mask and the results are well satisfactory for UWB propagation standards proposed by FCC. The impulse response being highly non-linear poses problems for the implementation. We have solved this problem by using Recursive Least Square (RLS) technique to develop an FIR structure for the pulse shaper of this LSE combined pulse. The attraction of the solution is that the resultant filter structure is simple and cost effective.

FPGA Schematic Implementations and Comparison of FIR Digital Filter Structures

In this study, we investigate the FPGA schematic implementations of finite impulse response (FIR) digital filters for three fundamental structures on Altera DE2-115 board without requiring any other software packages such as DSP Builder and Matlab Simulink. First of all, a low pass FIR digital filter is designed by using Matlab filter design and analysis tool (fdatool) program. Then, the designed filter is implemented and simulated on Matlab for a given input signal. After that, for three fundamental structures (namely direct-form, transposed direct-form, and symmetric direct-form) in literature, the designed filter is implemented schematically on Quartus-II software and then each project containing different structure implementation is compiled. Then, the digital filters implemented by each structure are simulated by University Program Vector Wave File (VWF) simulation program on Quartus-II software. Simulation results show that the obtained results are the same as the ones obtained on Matlab, which confirms that the schematic designs are successfully implemented. Moreover, the implemented digital filters are realized and successfully tested on Altera DE2-115 FPGA board. Finally, three fundamental FIR structures for various filter lengths from 11 to 51 are implemented to compare them in terms of total logic elements, total registers, and total memory.

Iterative Residual Generator for Fault Detection With Linear Time-Invariant State–Space Models

In this paper, an iterative residual generator (IRG) is proposed for discrete time-invariant state-space model with the aim of detecting faulty signals. By minimizing the mean square errors subject to unbiasedness constraint, a new filter with finite impulse response structure is derived. The resulting IRG is then obtained by extracting residual signal from the batch filter through several predictor/corrector iterations. It shows that IRG can provide a zero-mean Gaussian process regardless of previous estimation errors. More importantly, it includes the residual generation process in the Kalman filter as its special case. With the chi-square test, a numerical example is simulated to demonstrate that IRG can reduce the false alarm significantly compared with the traditional recursive strategy in the presence of actuator or sensor faults, and the estimation horizon length in IRG serves as a tuning parameter providing a tradeoff between the missed alarm and false alarm.

Bayesian state estimation on finite horizons: The case of linear state–space model

The finite impulse response (FIR) filter and infinite impulse response filter including the Kalman filter (KF) are generally considered as two different types of state estimation methods. In this paper, the sequential Bayesian philosophy is extended to a filter design using a fixed amount of most recent measurements, with the aim of exploiting the FIR structure and unifying some basic FIR filters with the KF. Specifically, the conditional mean and covariance of the posterior probability density functions are first derived to show the FIR counterpart of the KF. To remove the dependence on initial states, the corresponding likelihood is further maximized and realized iteratively. It shows that the maximum likelihood modification unifies the existing unbiased FIR filters by tuning a weighting matrix. Moreover, it converges to the Kalman estimate with the increase of horizon length, and can thus be considered as a link between the FIR filtering and the KF. Several important properties including stability and robustness against errors of noise statistics are illustrated. Finally, a moving target tracking example and an experiment with a three degrees-of-freedom helicopter system are introduced to demonstrate effectiveness.

FPGA Implementation of Higher Order FIR Filter

The digital Finite-Impulse-Response (FIR) filters are mainly employed in digital signal processing applications. The main components of digital FIR filters designed on FPGAs are the register bank to save the samples of signals, adder to implement sum operations and multiplier for multiplication of filter coefficients to signal samples. Although, design and implementation of digital FIR filters seem simple but the design bottleneck is multiplier block for speed, power consumption and FPGA chip area occupation. The multipliers are an integral part in FIR structures and these use a large part of the chip area. This limits the number of processing elements (PE) available on the chip to realize a higher order of filter. A model is developed in the Matlab/Simulink environment to investigate the performance of the desired higher order FIR filter. An equivalent FIR filter representation is designed by the Xilinx FIR Compiler by using the exported FIR filter coefficients. The Xilinx implementation flow is completed with the help of Xilinx ISE 14.5. It is observed how the use of higher order FIR filter impacts the resource utilization of the FPGA and it’s the maximum operating frequency.

A new design of prefilter for reducing timing synchronization jitter

SummaryFor high‐precision timing synchronization in feedback Gardner algorithm and different feedforward nonlinear algorithms, timing jitter reduction is the key problem, especially with a small roll‐off factor in high‐order modulation. Through the elaborate analysis about the timing jitter, this paper proposes a new prefilter design method based on finite impulse response structure. Using a suitable Kaiser window for suppressing the sidelobe energy of the proposed prefilter, this method can further decrease the complexity of filter design and eliminate most part of the pattern noise. Compared with the previous prefilter design algorithms, the approach has a better improvement in steady‐state phase jitter reduction without increasing the capture time in Gardner timing error detector. Meanwhile, with such kind of prefilter, the performance of logarithmic nonlinearity is better than that of square law nonlinearity, this is not reported in literature. Simulation results show that the residual timing jitter in both kinds of algorithms is closed to the modified Cramer‐Rao bound when the roll‐off factor is equal to 0.1 in 1024QAM.

A Review - Design of Area and Power Efficient Digital FIR Filter Based On Faithfully Rounded Truncated 12-Bit Constant

Finite impulse response (FIR) designs are given exploitation the conception of rounded truncated multipliers 12bit. we have a tendency to think about the optimization of bit width without sacrificing the frequency response and output preciseness. A smallest amount comes to of dissimilar pairs or groups of symbols and residues are often used to code a set of coefficients support on their likelihood and conditional probability of occurrence. This ingenious idea permits the notion of entropy to be applied as a quantitative measure to evaluate the coding density of various compositions of symbols towards a set of coefficients. No uniform constant quantization with correct filter order is projected to attenuate total region expenditure. Multiple invariable multiplication/increase during an exceedingly in a very} direct FIR structure is implemented exploitation an improved version of truncated multipliers. Multiple constant multiplication/ accumulation during an exceedingly in a very} synchronized direct FIR structure are implemented using an improved version of truncated multipliers.

A New Approach on Design of a Digital Phase-Locked Loop

In this letter, we propose a new approach to the design of a digital phase-locked loop (DPLL) with a finite impulse response (FIR) structure, deadbeat property, and $H_\infty$ performance. This DPLL is called the deadbeat $H_\infty$ FIR DPLL (DHFDPLL). The proposed DHFDPLL ensures the $H_\infty$ performance against incorrect information on noise and has intrinsic robustness against quantization effects because of the FIR structure. Demonstrative simulations are provided to show that the DHFDPLL exhibits excellent robustness against effects of incorrect noise and quantization compared with the existing DPLLs.