Finite Impulse Response Filter Research Articles

Wideband, Low Profile Coupling Suppression Circuit for Simultaneous Transmit and Receive System Based on Hybrid Finite Impulse Response and Resonator Topology

In-band full-duplex (IBFD) systems can double the spectral efficiency by enabling simultaneous transmission and reception within the same band. Key to realizing full-duplex radios is the cancellation of the self-interference (SI) that couples from the transmitting antenna into the receiving path. This is done by introducing a self-interference cancellations (SIC) circuit to significantly reduce the coupled transmit signal and avoid receiver’s desensitization. Additionally, SI suppression becomes more challenging across broader bandwidths. This paper presents a novel, wideband, and low profile SIC circuit based on a hybrid Finite Impulse Response (FIR) and resonator filter topology. The latter is optimized to provide an average of 22dB cancellation across 800MHz in the L-band. Conventional, SIC circuits require a filter bank with at least two FIR filters to achieve such a wide bandwidth. Conversely, our FIR resonator design is low profile with a circuit size nearly half of that of a filter bank. Simulations show a minimum cancellation of 15dB and a maximum cancellation of 45dB. A prototype was fabricated and tested, showing an average of ~ 20dB cancellation which is in good agreement with our simulation. Further, measured results show a minimum cancellation of 15dB and maximum cancellation of 27dB.

Measuring Mental Workload Using ERPs Based on FIR, ICA, and MARA

Mental workload is considered to be strongly linked to human performance, and the ability to measure it accurately is key for balancing human health and work. In this study, brain signals were elicited by mental arithmetic tasks of varying difficulty to stimulate different levels of mental workload. In addition, a finite impulse response (FIR) filter, independent component analysis (ICA), and multiple artifact rejection algorithms (MARAs) were used to filter event-related potentials (ERPs). Then, the data consisting of ERPs, subjective ratings of mental workload, and task performance, were analyzed through the use of variance and Spearman’s correlation during a simulated computer task. We found that participants responded faster and performed better in the easy task condition, followed by the medium and high-difficulty conditions, which verifies the validity of the ERP filtering. Moreover, larger P2 and P3 waveforms were evoked as the task difficulty increased, and a higher task difficulty elicited a more enhanced N300. Correlation analysis revealed a negative relationship between the amplitude of P3 and the subjective ratings, and a positive relationship between the P3 amplitude and accuracy. The results presented in this paper demonstrate that a combination of FIR, ICA, and MARA methods can filter ERPs in the non-invasive real-time measurement of workload. Additionally, frontocentral P2, N3, and parietal P3 components showed differences between genders. The proposed measurement of mental workload can be useful for real-time identification of mental states and can be applied to human–computer interaction in the future.

Flexible Sub-bands F-OFDM Configured for Spectrum Efficiency Enhancement in 5G System

The new product of wireless communication systems, the Fifth generation (5G), promises higher data rates and Spectrum Efficiency (SE) enhancements to support the communication of heterogeneous services. The Filtered-OFDM (F-OFDM) technique was proposed as the strongest candidate waveform for the physical layer in 5G to fulfill these requirements. In F-OFDM, the whole band is split into narrow sub-bands, each filtered by a digital Finite Impulse Response (FIR) filter with different specifications to increase the spectrum utilization and allow for asynchronous transmission. This paper proposes a novel F-OFDM design waveform for the first time with four sub-bands in equal and unequal sub-band sizes of seven kinds of window sinc filters and a variety of numerology designs to observe SE enhancement using Matlab-Simulink Software. Simulation results show that F-OFDM can reduce Out-Of-Band Emission (OOBE) and achieve SE of about (5%-6%) higher than conventional OFDM for equal and unequal sized sub-bands, respectively, by optimizing the guard band between the designed sub-bands, which achieves 5G guard band requirements.

Removing Powerline Interference from EEG Signal using Optimized FIR Filters

The Electroencephalography (EEG) is a signal representing the electrical activity of the brain and is used in the diagnosis of brain diseases. The EEG signal is weak and highly prone to noise from the powerline which generates a sinusoidal signal with the main frequency of 5060 Hz. Therefore, three harmonics of powerline noise must be removed using notch filters for a perfect diagnosis which requires three series notch filters. This paper presents a new method to design a digital notch finite impulse response (FIR) filter using a modified particle swarm optimization technique. The proposed method provides a short length, maximum stopband attenuation, and small transition width compared to different algorithms which results in removing the noise in EEG signal efficiently.

A Self-Contained STFT CNN for ECG Classification and Arrhythmia Detection at the Edge

Automated classification of Electrocardiogram (ECG) for arrhythmia monitoring is the core of cardiovascular disease diagnosis. Machine Learning (ML) is widely used for arrhythmia detection using various feature engineering and classification models. Cloud-based inference is the prevailing deployment model of modern ML algorithms which does not always meet the availability and privacy requirements of ECG monitoring. Edge inference is an emerging alternative which addresses the concerns of latency, privacy, connectivity, and availability. However, edge deployment of AI models is challenging due to the demanding requirements of modern ML algorithms and the computation constraints of edge devices. In this work, we propose a lightweight self-contained short-time Fourier Transform (STFT) Convolutional Neural Network (CNN) model for ECG classification and arrhythmia detection in real-time at the edge. We provide a clear interpretation of the convolutional layer as a Finite Impulse Response (FIR) filter and exploit this interpretation to develop an STFT-based 1D convolutional (Conv1D) layer to extract the spectrogram of the input ECG signal. The Conv1D output feature maps are reshaped into a 2D heatmap and fed to a 2D convolutional (Conv2D) neural network (CNN) for classification. The real-time performance of the proposed model is planned in advance to fit the resource constraints of edge inference. Four model variants are trained, optimized, and tested on a raspberry-pi edge device. Weight quantization and pruning techniques are applied to the developed models to optimize them for edge computing. The MIT-BIH arrhythmia database is used for model training and testing. The proposed classifiers can achieve up to 99.1% classification accuracy and 95% F1-score at the edge with a maximum model size of 90 KB, an average inference time of 9 ms, and a maximum memory usage of 12 MB. The achieved results of the proposed classifier enable its deployment on a wide range of edge devices for arrhythmia detection.

A New Reduced-Order Implementation of Discrete-Time Fractional-Order PID Controller

This paper presents a new method for computationally effective implementation of a discrete-time fractional-order proportional–integral–derivative (FOPID) controller. The proposed method is based on a unique representation of the FOPID controller, where fractional properties are modeled by a specific finite impulse response (FIR) filter. The balanced truncation model order reduction method is applied in the proposed approach to obtain an effective, low-order model of the FOPID controller. The time-invariant FOPID controller implementation is presented first, and then the methodology is extended to the controller with time-varying gains. A comparative analysis shows that the proposed methodology leads to the effective modeling of discrete-time FOPID controllers. In addition to simulation runs, the effectiveness of the introduced methodology is confirmed in a real-life experiment involving the control of the DC motor servo system. The paper concludes with the implementation tools developed in the Matlab/Simulink environment.

A Generalized Flat-Topped Beam Synthesis Approach for Uniform Linear Array With Arbitrary Beam Directions

A systematic approach to synthesize the flat-topped beam (FTB) with arbitrary beam directions for uniform linear arrays (ULAs) is proposed, illustrated, and demonstrated. Based on the correspondence between the far-field pattern of ULAs and the response function of finite impulse response (FIR) filters, both the broadside and end-fire FTBs can be synthesized using window method, whereas the oblique FTB synthesis is failed due to the appearance of grating lobes. A mathematical analyzation indicates that two grating lobes are conjugate to each other. Thus, a linear phase method (LPM) is proposed to apply progressive excitation phases to each individual array element, which can eliminate the grating lobes by manipulating the two conjugate beams to overlap with each other. The proposed LPM is generalized to the synthesis of broadside, oblique and unidirectional end-fire FTBs, and the corresponding inter-element spacing constraints are addressed. The proposed approach is experimentally verified using a 16-element substrate-integrated waveguide slot antenna array. Comparing with the conventional Fourier series method and Woodward-Lawson method, the proposed approach has advantages of both smaller ripples in the main beam and controllable side-lobe levels. The proposed approach is promising for offering efficient beamforming functionalities for wireless communications, imaging, and radar applications.

FPGA Acceleration of 3GPP Channel Model Emulator for 5G New Radio

The channel model is by far the most computing intensive part of the link level simulations of multiple-input and multiple-output (MIMO) fifth-generation new radio (5G NR) communication systems. Simulation effort further increases when using more realistic geometry-based channel models, such as the three-dimensional spatial channel model (3D-SCM). Channel emulation is used for functional and performance verification of such models in the network planning phase. These models use multiple finite impulse response (FIR) filters and have a very high degree of parallelism which can be exploited for accelerated execution on Field Programmable Gate Array (FPGA) and Graphics Processing Unit (GPU) platforms. This paper proposes an efficient re-configurable implementation of the 3rd generation partnership project (3GPP) 3D-SCM on FPGAs using a design flow based on high-level synthesis (HLS). It studies the effect of various HLS optimization techniques on the total latency and hardware resource utilization on Xilinx Alveo U280 and Intel Arria 10GX 1150 high-performance FPGAs, using in both cases the commercial HLS tools of the producer. The channel model accuracy is preserved using double precision floating point arithmetic. This work analyzes in detail the effort to target the FPGA platforms using HLS tools, both in terms of common parallelization effort (shared by both FPGAs), and in terms of platform-specific effort, different for Xilinx and Intel FPGAs. Compared to the baseline general-purpose central processing unit (CPU) implementation, the achieved speedups are 65X and 95X using the Xilinx UltraScale+ and Intel Arria FPGA platform respectively, when using a Double Data Rate (DDR) memory interface. The FPGA-based designs also achieved ~3X better performance compared to a similar technology node NVIDIA GeForce GTX 1070 GPU, while consuming ~4X less energy. The FPGA implementation speedup improves up to 173X over the CPU baseline when using the Xilinx UltraRAM (URAM) and High-Bandwidth Memory (HBM) resources, also achieving 6X lower latency and 12X lower energy consumption than the GPU implementation.

An Adaptive Filter for Subdivision of Circular Grating Signal of Angle Measurement

Angle is an important physical quantity in International Systems of Units (SI). The precise measurement of an angle is of great significance for scientific research and production. The circular grating is a widely used angle measurement sensor because of its large range and high resolution. Subdivision is the key part of grating measurement to ensure high resolution. In order to guarantee the subdivision function, we propose an adaptive filter to suppress the noises in the moiré signals of the circular grating. The principle of subdivision is introduced and the arc-tangent subdivision method mapping the phase of the moiré signals into the displacement is adopted. The influence of noises on subdivision results is analyzed by building the error model of the moiré signals. A detailed description of the adapted filter, which is composed of a linear prediction filter and the least mean square (LMS) adaptive algorithm, is provided herein. The structure of the adapted filter is optimized with a symmetrical structure and the hardware resources are reduced by about 1/3. Finally, evaluation tests are performed with a calibration platform for positioning the accuracy of a turntable and a laboratory-made field-programmable gate array (FPGA) circuit. The results confirmed that the adaptive filter proposed in this article can filter out random noises more effectively than the conventional finite impulse response (FIR) filter with the same order, revealing a phase error fluctuates within [−0.012, +0.003 rad]. The positioning accuracy of the turntable with a laboratory-made circuit using an adaptive filter is better than 0.8.

A Natively Fixed-Point Run-Time Reconfigurable FIR Filter Design Method for FPGA Hardware

We present a natively fixed-point filter design method that targets FPGA-based Reconfigurable Finite Impulse Response (RFIR) filters for Software Defined Radio applications. The Filter Designer is capable of reconfiguring cut-off frequencies on-the-fly at run-time; with other parameters, such as filter length and window type, configurable at compile-time. The ability to compute filter coefficients directly on FPGAs is compelling, as much lower latencies can be achieved when compared to RFIRs programmed with embedded processors. In this work we discuss several filter design techniques from the literature and investigate their suitability for implementation on FPGAs. A hybrid method combining window and frequency sampling methods is developed and implemented on a Xilinx Zynq-7000 SoC. We explore the limitations of designing filters in fixed-point arithmetic and consider the effects filter length and wordlength have on filter quality. Results show that the proposed algorithm generates good-quality filters that display stopband attenuation up to 88dB, transition bandwidths less than 1% of the sample rate, and low resource utilisation. Most notably, we found that our method is up to three orders of magnitude faster than an equivalent software implementation, with execution times as low as 2.52 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{s}$ </tex-math></inline-formula> , enabling radio applications in which latency is a principal constraint.

Quantization Analysis and Robust Design for Distributed Graph Filters

Distributed graph filters have recently found applications in wireless sensor networks (WSNs) to solve distributed tasks such as reaching consensus, signal denoising, and reconstruction. However, when implemented over WSNs, the graph filters should deal with network limited energy constraints as well as processing and communication capabilities. Quantization plays a fundamental role to improve the latter but its effects on distributed graph filtering are little understood. WSNs are also prone to random link losses due to noise and interference. In this instance, the filter output is affected by both the quantization error and the topological randomness error, which, if it is not properly accounted in the filter design phase, may lead to an accumulated error through the filtering iterations and significantly degrade the performance. In this paper, we analyze how quantization affects distributed graph filtering over both time-invariant and time-varying graphs. We bring insights on the quantization effects for the two most common graph filters: the finite impulse response (FIR) and autoregressive moving average (ARMA) graph filter. Besides providing a comprehensive analysis, we devise theoretical performance guarantees on the filter performance when the quantization stepsize is fixed or changes dynamically over the filtering iterations. For FIR filters, we show that a dynamic quantization stepsize leads to more reduction of the quantization noise than in the fixed-stepsize quantization. For ARMA graph filters, we show that decreasing the quantization stepsize over the iterations reduces the quantization noise to zero at the steady-state. In addition, we propose robust filter design strategies that minimize the quantization noise for both time-invariant and time-varying networks. Numerical experiments on synthetic and two real data sets corroborate our findings and show the different trade-offs between quantization bits, filter order, and robustness to topological randomness.

Reduction of Harmonics in Power Lines Using Finite Impulse Response Filter

This work focused on reduction of harmonics in Power lines using finite impulse response filter. Since the rising usage of power electronic devices sensitive to harmonics, which has resulted in a growth in the number of adverse harmonic-related occurrences, network harmonic investigations have become a major concern in electric power systems. The problem of power quality and how to control it is becoming more of a concern. Power quality difficulties have arisen as a result of the connection of nonlinear loads in the network, resulting in widespread waveform distortion. The harmonic analysis was based on bus bar voltage solutions acquired from a power flow study on the Electricity Distribution Company's power distribution network at the Onitsha TCN work centre. The focus of this work was on the use of active power filter in reducing the harmonics by generating compensation signal by the active filter (APF) for the reduction of harmonic distortion as well as enhancing the system’s power factor. A system model to reduce harmonics in power line by using FIR filter to generate compensation signals and switching pulses for the active filter was modeled and the performance of the FIR filter using Matlab/Simulink environment was compared with the performance without filter. The sending and receiving end bus bar voltages were derived from the power flow analysis and used in the simulation. Harmonic results without filter and with filter were shown and it shows that the use of FIR active filter which has improved advantages over the conventional passive filters in mitigating harmonics was able to reduce the harmonics from 17.77% to 0.87% which is 16.9% ( 95% reduction) thereby improving the current, voltage and power factor (pf) of the system. Reduction of harmonics reduced disturbances that usually cause equipment overheating and deterioration of the performance of electronic equipment; hence the performances of the electronic equipment greatly improved leading to economic benefits.

Detection of Transients in Vibration Signals Using Reverse Dispersion Entropy

Abstract In this work, the reverse dispersion entropy (RDE) is used to process the squared envelope (SE) signal in order to detect nonstationarites. Based on the idea of spectral kurtosis (SK) and kurtogram, the squared envelope signal is first extracted by applying the short time Fourier transform to vibration signal. Then, as an alternative to negative Shannon entropy, the RDE is used to process the squared envelope to detect the range of frequencies at which the transients occur. The RDEgram color-coded map is used to represent the RDE values as a function of frequency and frequency resolution from which the ideal filter parameters can be inferred. Once the best frequency and frequency bandwidth pair are found, an optimum finite impulse response filter can be designed to filter the original vibration signal. The proposed method is tested against simulated and actual vibration signals and proved to be superior to existing methods.

FPGA Design of a High- Resolution FIR Band-Pass Filter by Using LabVIEW Environment

Designers regularly use Finite Impulse Response (FIR) filters to fulfil the need for current electronic design applications such as signal or image processing and digital communications because of the remarkable selectivity computational efficiency. Fast and efficient information processing requires a dedicated microprocessor or a digital signal processor that may not always be available or provide enough performance. In such scenarios, designers can configure FPGAs for processing digitized signals. One of the most popular signal processing applications is filtering. Unlike the Infinite Impulse Response (IIR) filters, FIR filters do not have analog equivalent circuits. For this purpose, continuous time-discrete time conversion is not possible with the help of transforms. Because analog filters cannot have a finite impulse response, the design methods of FIR filters can be made as windowing method, pulse response truncation, and optimal filter design method. Considering this information, it aims to digitally separate two signals with different frequencies (2.4 kHz and 4.2 kHz), which are given to the input as analog, to obtain the desired information signal and suppress other signals. We preferred to use LabVIEW graphical programming language to get the digital FIR filter coefficients. We selected rectangular windowing, set the digital filter's sampling frequency as 18720 Hz, and determined the filter's coefficient with high-frequency resolution as 24. Using filter coefficients in the real-time FPGA-VHDL environment, we showed the performance and resource consumption. LabVIEW is used for simulation as well as obtaining filter coefficients. In addition, we compared both simulation and real-time FPGA-VHDL application output waveforms and examined both platforms' advantages and disadvantages.

Analysis of a novel FPGA-based system for filtering audio signals using a finite impulse response filters

Analysis of a novel FPGA-based system for filtering audio signals using a finite impulse response filters

Digital filters windowing for data transmission enhancement in communication channel

In this search, an important methodology has been presented for communicated information rectification utilizing advanced channel windowing approach. The modern data communication technologies are ensured with numerous challenges because of their unpredictability and arrangement. Various digital transmission topologies in 4G can't fulfill the requirements in future arrangements, therefore, alternative multicarrier modulation (MCM) becoming the nominated approaches among all other data transmission techniques. Wherein prototype filter configuration is a fundamental system based on which the synthesis and analysis filters are derived. This paper presents a complete review on the ongoing advances of finite impulse response (FIR) filter plan procedures in MCM based correspondence frameworks. Initially, the essential issues are tried, taking into consideration the presentation of available data signal applicants and the FIR filter design concept. At that point the techniques for FIR filter configuration are summed up in subtleties and are center around the accompanying three group’s recurrence testing strategies, windowing based strategies and advancement-based techniques. At last, the exhibitions of different FIR structure strategies are assessed and measured by power spectral density (PSD) and bit error rate (BER), and variable MCM plots as well as their potential prototype filters are examined.

Epileptic seizure identification in EEG signals using DWT, ANN and sequential window algorithm

A patient-specific novel systematic methodology is described in this study for automatic seizure detection from raw electroencephalogram (EEG) signals. Filtering process by means of band-pass finite impulse response (FIR) filter with the frequency range of 0.5–40 Hz is implemented at the outset to eliminate different artifacts and noises mixed with raw EEG signals. As EEGs are highly non-linear and non-stationary signals in nature, discrete wavelet transform (DWT) is then used to analyze the signals in time-frequency domain. DWT with four level decomposition is performed using db6 mother wavelet for feature extraction. A new feature set, composed of eleven non-linear statistical features extracted from each sub-bands resulting from due to wavelet decomposition, is then fed to the input of artificial neural network (ANN) to classify the signal accurately. Finally, a novel algorithm named sequential window algorithm is carried out to improve the classification performance. 99.44% mean classification accuracy, 80.66% average sensitivity, 4.12 s mean latency and 0.2% average false positive rate (FPR) are achieved in this study. This study successfully reduces the latency time with more accuracy and significantly low FPR.

An IR-UWB IEEE 802.15.4z Compatible Coherent Asynchronous Polar Transmitter in 28-nm CMOS

A low-power IEEE 802.15.4z high-rate PHY (HRP) compatible coherent transmitter is described. The proposed transmitter uses a digital polar architecture with fixed amplitude steps in the power amplifier and asynchronous time-discrete pulse shaping. The pulse-shaping unit consists of a finite-impulse response (FIR) filter using current-starved inverter-based delay taps that can be calibrated on-chip. An injection-locked ring oscillator (ILRO)-based frequency synthesis enables wideband operation from 3- to 10-GHz frequency bands. The ILRO also allows for duty-cycled coherent mode operation with 2–4-ns phase locking time and binary phase modulation is applied directly on the oscillator. The on-chip digital front end enables duty cycling (DC) of analog front-end modules with a granularity of 2 ns. Implemented in 28-nm CMOS process, this chip is measured to consume 4.9-mW power in nominal mode with IEEE 802.15.4z high pulse repetition frequency (HPRF) compatible data rate of 6.81 Mb/s compliant with major spectrum mask regulations for channels 5 and 9. With DC of the oscillator enabled in the energy-efficient mode, a power consumption of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$430~\mu \text{W}$ </tex-math></inline-formula> is achieved for packets compatible with legacy pulse-position-modulated IEEE 802.15.4a standard with a data rate of 27.2 Mb/s.

RDO-WT: optimised Wallace Tree multiplier based FIR filter for signal processing applications

ABSTRACT Digital Signal Processing (DSP) and communication applications utilise a Finite Impulse Response (FIR) filter which is key component for digital communication. Moreover, quality of signal is enhanced by FIR filter which is mostly employed by filtering applications. The execution speed of the FIR is determined by multiplier’s performance. Hardware resource utilisation and speed-up operations are some of the issues found in existing methods which are occurred due to a critical path in incomplete products. So, this can be improved by the proposed optimisation algorithm based multiplier. This research establishes the execution of FIR Filter design using Red Deer Optimisation (RDO) based Wallace Tree (WT) multiplier. By using the optimised WT multiplier, FIR filter is simulated to examine the area, delay, power and frequency for different tap FIR filter. Moreover, FIR filter with optimised WT is introduced to perform signal denoising application. Proposed multiplier design is simulated using Xilinx tool. Filtering simulation is done by using the publicly available database named as MIT-BIH database and the noise removal process is simulated using Matlab tool. The FIR filter designed with proposed multiplier provides delay around 1.373 ns and consumes 0.143 W as total power which is lesser than the existing methods.

Factors Affecting Self-Localization in UHF RFID Tag Networks

Accuracy of mobile objects self-localization in radio frequency identification (RFID) tag networks depends on many environmental and design factors. This paper analyzes effect of such factors on estimates of the mobile object location. As an estimator, we use the extended finite impulse response (EFIR) filter. It is shown that accuracy of self-localization in the ultra high frequency (UHF) RFID tag networks can be increased by the factor of several times if to optimize design of the tag and network environment and obtain the optimal angle of arrival and viewing angle. Many other factors are also considered.