Finite Impulse Response Feedback Research Articles

A 24-kHz BW 90.5-dB SNDR 96-dB DR continuous-time delta-sigma modulator using FIR DAC feedback

This paper presents a single bit continuous time delta-sigma modulator (CTDSM) with finite impulse response (FIR) feedback DAC designed for audio applications. By using FIR feedback in the input stage, the linearity requirements of the first integrator are relaxed, and the clock jitter sensitivity is reduced, as seen in a multi-bit quantizers. The choppers, working in conjunction with the FIR DAC, effectively suppresses in-band aliasing noise generated by the chopper in the first integrator. A fast comparator serves as a single-bit quantizer, and the 9.2% TS loop delay eliminates the need for excess loop delay compensation in the modulator. Energy efficient integrators are implemented using the current-starved OTA. The CTDSM prototype was fabricated using a 180-nm CMOS process, achieving a 90.5 dB SNDR and 96 dB DR with a 24 kHz signal bandwidth. The power consumption is 210 μ W, corresponding to a Schreier figure-of-merit value of 171.1 dB.

Analysis and Design of an Audio Continuous-Time 1-X FIR-MASH Delta–Sigma Modulator

We combine a first-order single-bit CTΔΣM employing finite impulse-response (FIR) feedback with a 1-bit second-order ΔΣ back end to achieve a modulator with maximum stable amplitude (MSA) that is close to full scale, and a third-order overall noise transfer function (NTF). FIR feedback is used in the input stage to reduce clock-jitter sensitivity, improve linearity, and reduce chopping artifacts. We show that in a MASH ADC, FIR feedback has the additional benefit of filtering the error waveform of the first stage that is fed into the second stage. We apply the principle to an audio continuous-time delta-sigma modulator. A prototype chip, fabricated in 180-nm CMOS to demonstrate the principle, achieves 100.9-dB SNDR in a 24-kHz bandwidth and dissipates 265μW. The resulting Schreier figure of merit is 180.5 dB.

Sparse Representation of Feedback Filters in Delta-Sigma Modulators

In this paper, we propose sparse representation of FIR (Finite Impulse Response) feedback filters in delta-sigma modulators. The filter has a sparse structure, that is, only a few coefficients are non-zero, that stabilizes the feedback modulator, and minimizes the maximum magnitude of the noise transfer function at low frequencies. The optimization is described as an ℓ1 minimization with linear matrix inequalities (LMIs), based on the generalized KYP (Kalman-Yakubovich-Popov) lemma. A design example is shown to illustrate the effectiveness of the proposed method.

Continuous-Time Delta-Sigma Modulators With Time-Interleaved FIR Feedback

The use of a single-bit quantizer in a wideband CTΔΣM is attractive, as the quantizer can be implemented in a power and area-efficient manner. Unfortunately, 1-bit CTΔΣMs are plagued by a host of difficulties. Clock jitter and quantizer metastability are particularly problematic, and the higher loop filter linearity needed to process the full-scale feedback waveform results in increased power dissipation. The use of a finite impulse response (FIR) feedback DAC is a power efficient way of addressing the challenges above. However, even this technique runs into difficulties at multi-GHz clock rates. This paper introduces the idea of time-interleaved (TI) FIR feedback to enhance the performance of a conventional FIR DAC. A single-bit CTΔΣM that uses a 2× TI-FIR DAC achieves 67.6/68.8/76 dB SNDR/SNR/DR in a 60 MHz bandwidth. Designed in a low leakage 65 nm CMOS process, the modulator operates at 6 GHz and occupies only 0.07 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Its Walden Figure of Merit is 56.5 fJ/lvl.

Analysis and Design of Continuous-Time Delta–Sigma Converters Incorporating Chopping

Chopping the operational transconductance amplifier (OTA) of the input integrator in a CT $\Delta \Sigma \text{M}$ is a traditional and effective way of addressing flicker noise in such modulators. Unfortunately, chopping leads to aliasing of shaped quantization noise into the signal band and degrades performance. We analyze the mechanisms of shaped-noise aliasing in OTA- $RC$ integrators that use two-stage feedforward-compensated OTAs, and show that aliasing can be largely mitigated by using an finite impulse response feedback digital-to-analog converter with its zeros placed at multiples of twice the chopping frequency. The theory is borne out by measurement results from a single-bit CT $\Delta \Sigma \text{M}$ , which achieves a peak SNDR of 98.5 dB in a 24-kHz bandwidth while consuming only 280 $\mu \text{W}$ from a 1.8-V supply. Realized in a 180-nm CMOS technology, it achieves a $1/f$ noise corner of about 3 Hz when chopped at $f_{s}/24$ .

Double‐sampled ΔΣ modulator with 1.5‐bit FIR feedback DAC for reduced noise folding and increased power efficiency

A double-sampled delta-sigma modulator (DSM) with a 1.5-bit finite impulse response (FIR) feedback digital-to-analogue converter (DAC) is proposed to avoid noise folding due to the mismatch between feedback paths. The proposed DSM allows the use of the sharing input-sampling capacitor configuration in a switched-capacitor integrator, resulting in lower kT/C noise, smaller area and lower power consumption. It also shapes only the frequency response of the feedback DAC output without modifying the noise transfer function to avoid the signal-to-quantisation noise ratio (SQNR) degradation of conventional techniques. Evaluation results indicate that the proposed double-sampled DSM achieves a 101.5 dB SQNR with 30% lower power and 20% reduced area as compared with conventional double-sampled DSMs.

Interpolated decision feedback equalization for long intersymbol interference channels

The decision feedback equalizer (DFE) is widely used in communication systems combating intersymbol interference effect. In wireline communications, the channel response is usually long and the computational complexity of the DFE is often high. This is particularly true when the precoding is applied in which the feedback signal value becomes continuous rather than discrete. In this paper, an interpolated DFE (IDFE) structure is proposed to solve the problem. The proposed IDFE consists of a finite-impulse-response (FIR) feedforward filter and an interpolated FIR feedback filter. Thanks to the interpolation operation, the computational complexity of the DFE can be greatly reduced. The least-mean-squared (LMS) algorithm is applied to train the tap weights yielding an adaptive IDFE. Closed-form expressions for optimal filter coefficients, mean squared errors, and signal-to-noise ratios are derived. The convergence behavior of the adaptive IDFE is also analyzed. Simulation results show that while the computational complexity is significantly reduced, the performance of the proposed IDFE is similar to the conventional DFE. The computational saving can be as high as 76% for a high-speed digital subscriber line application.

Linear analysis of the influence of FIR feedback filters on the response of the pulsed digital oscillator

The objective of this work is to extend the linear analysis of Pulsed Digital Oscillators to those topologies having a Finite Impulse Response (FIR) in the feedback loop of the circuit. It will be shown with two specific examples how the overall response of the oscillator can be adjusted to some point by changing the feedback filter, when the resonator presents heavy damping losses. Extensive discrete-time simulations and experimental results obtained with a MEMS cantilever with thermoelectric actuation and piezoresistive position sensing are presented. It will be experimentally shown that the performance of the oscillator is good even below the Nyquist limit.