Finite Field Operations Research Articles

Finite algebras in the design of multivariate cryptography algorithms

A new approach to the design of multivariate public-key cryptalgorithms is introduced. It envisages using non-linear mappings defined as squaring and cubic operations in finite fields represented as finite algebras. The developed approach allows significant reduction of the size of public key and thereby make post-quantum algorithms of multivariate cryptography much more practical. In the developed algorithms, the secret key includes a set of values of structural constants that determine the modifications of the finite fields used and the coefficients in the set of sixth degree polynomials that make up the public key

Side-Channel Attacks Against the FESH Algorithm

The FESH algorithm is a block cipher algorithm based on finite field operations. Currently, no research has been conducted on its side-channel attack security. Therefore, this study proposes two methods to address this issue: a correlation power analysis attack method targeting the FESH algorithm, and a template attack method based on an improved TransNet model. The first method theoretically analyzed the vulnerabilities of the FESH algorithm and successfully obtained valid leaked information through a correlation power attack; The second method introduced BlurPool blurring and downsampling techniques, as well as normalization operations, which reduced the training parameters of the improved model by approximately 50%. Additionally, the validation was performed on both the FESH dataset and the desynchronized ASCAD public dataset, which provided evidence that the entropy estimates were significantly better than those of the original TransNet model. The experimental results highlight the importance of considering side-channel security when implementing the FESH algorithm.

Direct numerical simulations on oscillating flow past surface-mounted finite-height circular cylinder

In this work, a surface-mounted circular cylinder with a fixed aspect ratio (ratio of height of the cylinder to its diameter) of 5 is subjected to a non-zero mean oscillating flow with a range of frequencies and amplitudes. Three-dimensional direct numerical simulations are then conducted on this finite-height cylinder. The mass and momentum equations are resolved using the finite volume-based Open Source Field Operation and Manipulation (OpenFOAM). A fixed Reynolds number Re=UoD/ν of 250 is used in this study, which is defined based on mean velocity at the inlet ( Uo ) and cylinder diameter (D). Here ν is the kinematic viscosity of the working fluid. Non-dimensional velocity oscillation amplitude ( A∗=a/Uo ) is varied from 0.1 to 0.3, while the non-dimensional oscillation frequency ( f∗=f/fo ) takes the values of 0.33, 0.5, 1, 2, and 3. Here a and f are the dimensional oscillation amplitude and frequency, respectively and fo is the vortex shedding frequency corresponding to a uniform flow at Re = 250. The three-dimensional vortex structures, presented with the help of iso-Q surfaces, show that the oscillating flow changes the size and shape of the hairpin-shaped vortices. Wake is found to be synchronized with the oscillation frequency at f* = 2 for each value of the A* and results in the maximum lift force on the cylinder. Hilbert Huang transformation analysis of the transverse velocity signals at a specific point in the wake reveals that the wake is more complex and aperiodic in nature for f* values of 0.33, 0.5, and 1, whereas it is periodic for f* = 2 and 3. In order to further disclose the nonlinearity associated with the oscillating flow, the degree of stationarity is discussed corresponding to each value of A* and f*. Dynamic mode decomposition is exploited to obtain information about the coherent vortical structures and their spatial and temporal behavior in the wake with a change in the value of f*. Effects of A* and f* on the dynamic characteristics are also investigated.

Bounds on Performance for Recovery of Corrupted Labels in Supervised Learning: A Finite Query-Testing Approach

Label corruption leads to a significant challenge in supervised learning, particularly in deep neural networks. This paper considers recovering a small corrupted subset of data samples which are typically caused by non-expert sources, such as automatic classifiers. Our aim is to recover the corrupted data samples by exploiting a finite query-testing system as an additional expert. The task involves identifying the corrupted data samples with minimal expert queries and finding them to their true label values. The proposed query-testing system uses a random selection of a subset of data samples and utilizes finite field operations to construct combined responses. In this paper, we demonstrate an information-theoretic lower bound on the minimum number of queries required for recovering corrupted labels. The lower bound can be represented as a function of joint entropy with an imbalanced rate of data samples and mislabeled probability. In addition, we find an upper bound on the error probability using maximum a posteriori decoding.

Parallel Finite Field Algorithms for Communications and Sensor Networks

Sensor network integrates sensor technology, embedded computing technology, modern network and wireless communication technology, distributed information processing technology, etc. It can monitor, perceive and collect the information of various environments or monitoring objects in real time through various integrated micro sensors, and process the information through the embedded system. The perceived information is transmitted to the user terminal by multi-hop relay through the random ad-hoc wireless communication network. The coding of communications and sensor networks affects the efficiency of communication. The main coding technology is based on finite field. Among operations in finite fields, divisions are time-consuming operations since they are generally computed via inversions and multiplications. We present techniques to exploit extend binary trees for fast divisions in finite fields. We implement the finite field algorithm on Field Programmable Logic Arrays (FPGAs) in a parallel way. The implementation result from FPGAs shows that the parallel finite field algorithm can speed up the process of coding of communications and sensor networks.

Hardware Optimization and System Design of Elliptic Curve Encryption Algorithm Based on FPGA

Since entering the era of big data, the degree of information sharing is getting higher and higher; the information exchange is becoming more and more convenient, but at the same time, personal information is also easy to be exposed to the network environment, if it is used by criminals to lead to information leakage, and then bring certain risks. Therefore, it is in the information age and do a good job of network information security and confidentiality. At present, the security and secrecy of network information are mainly realized by cryptography. Public key cryptography can encrypt information and ensure the security of information transmission, so it is widely used in the contemporary society. At present, elliptic curve encryption is highly respected in the research field of public key cryptosystem. Elliptic curve encryption is divided into two main points, multiplication and inversion, respectively. Through the comparison of these two algorithms, it can be found that there are several choices if the main research objective is to save time, and the Euclidean extension method is mainly discussed in this paper. In other words, more efficient algorithms are used in the hardware implementation process, and a variety of algorithms can be used instead of a single curve algorithm. In this process, we can find the special features of upper level operation and bottom level finite operation. The upper level operation is KP operation, while the bottom level operation is fast calculation of four kinds of K in finite field operation, and finally realize FPGA algorithm. With the help of Quartus ii developed by predecessors, the upper and lower operations of elliptic curve are carried out using VHDL language. Combined ANXIX9.62 in the elliptic curve of each module to test, so as to ensure the accuracy of the data, reduces the error. According to the test results, the designed chip can efficiently complete the elliptic curve encryption system in the whole process. And the average KP operation time can reach 15.15 ms at 20 MHz frequency. At the same time, the chip can complete the operation on ECC public key with any variable curve in F domain less than 256. Therefore, this chip is a high-speed elliptic curve cryptographic chip with optional system parameters. Based on this, this article on the elliptic curve encryption algorithm based on FPGA hardware implementation of system design, from the view of mathematical study analysis, was carried out on the elliptic curve cryptosystem, according to the above two big difficulty, namely, the polynomial of GF(2), the finite field multiplication, and inversion; there will be a detailed studies of discussion, through software comparison to find the differences between different software, especially the software implementation performance level. In addition, it will also focus on the design of elliptic curve algorithm PGA, so as to explore the solution of the algorithm hardware.

Lightweight Architecture for Elliptic Curve Scalar Multiplication over Prime Field

In this paper, we present a novel lightweight elliptic curve scalar multiplication architecture for random Weierstrass curves over prime field Fp. The elliptic curve scalar multiplication is executed in Jacobian coordinates based on the Montgomery ladder algorithm with (X,Y)-only common Z coordinate arithmetic. At the finite field operation level, the adder-based modular multiplier and modular divider are optimized by the pre-calculation method to reduce the critical path while maintaining low resource consumption. At the group operation level, the point addition and point doubling methods in (X,Y)-only common Z coordinate arithmetic are modified to improve computation parallelism. A compact scheduling method is presented to improve the architecture’s performance, which includes appropriate scheduling of finite field operations and specific register connections. Compared with existing works, our design is implemented on the FPGA platform without using DSPs or BRAMs for higher portability. It utilizes 6.4~6.5k slices in Kintex-7, Virtex-7, and ZYNQ FPGA and executes an elliptic curve scalar multiplication for a field size of 256-bit in 1.73 ms, 1.70 ms, and 1.80 ms, respectively. Additionally, our design is resistant to timing attacks, simple power analysis attacks, and safe-error attacks. This architecture outperforms most state-of-the-art lightweight designs in terms of area-time products.

Hardware Implementation of Efficient Elliptic Curve Scalar Multiplication using Vedic Multiplier

This paper presents an area efficient and high-speed FPGA implementation of scalar multiplication using a Vedic multiplier. Scalar multiplication is the most important operation in Elliptic Curve Cryptography(ECC), which used for public key generation and the performance of ECC greatly depends on it. The scalar multiplication is multiplying integer k with scalar P to compute Q=kP, where k is private key and P is a base point on the Elliptic curve. The Scalar multiplication underlying finite field arithmetic operation i.e. addition multiplication, squaring and inversion to compute Q. From these finite field operations, multiplication is the most time-consuming operation, occupy more device space and it dominates the speed of Scalar multiplication. This paper presents an efficient implementation of finite field multiplication using a Vedic multiplier. The scalar multiplier is designed over Galois Binary field GF(2233) for field size=233-bit which is secured curve according to NIST. The performances of the proposed design are evaluated by comparing it with Karatsuba based scalar multiplier for area and delay. The results show that the proposed scalar multiplication using Vedic multiplier has consumed 22% less area on FPGA and also has 12% less delay, than Karatsuba, based scalar multiplier. The scalar multiplier is coded in Verilog HDL, synthesize and simulated in Xilinx 13.2 ISE on Virtex6 FPGA.

FFT enabled ECC for WSN nodes without hardware multiplier support

ECC is a popular cryptographic algorithm for key distribution in wireless sensor networks where power efficiency is desirable. A power efficient implementation of ECC without using hardware multiplier support was proposed earlier for wireless sensor nodes. The proposed implementation utilized the number theoretic transform to carry operands to the frequency domain, and conducted Montgomery multiplication, in addition to other finite field operations, in that domain. With this work, we perform in the frequency domain only polynomial multiplication and use the fast Fourier transform to carry operands between the time and frequency domains. Our ECC implementation over $GF((2^{13}-1)^{13})$ on the MSP430 microcontroller implements multiplications without using a hardware multiplier. It achieves scalar multiplication with fixed and random points in only 0.89 s and 1.74 s, respectively. Our implementation achieves ECC point multiplication of fixed and random points $10\%$ and $13\%$ faster, and consuming $12\%$ and $15\%$ less energy, in comparison to the existing work.

The soft graphic integer sub-decomposition method for elliptic scalar multiplication

A new version of the ISD method for computing a scalar multiplication on elliptic curve defined over prime field has been proposed. This version is called the soft graphic ISD (SG-ISD) method. The SG-ISD method employed the connected sub-graphs of undirected simple graph, which formed a soft graph (F, A) generated by a set valued function F, to represent the sub-scalars of ISD method. Thus, undirected simple graph can be proved as the SG-ISD version. On the SG-ISD method, the binary representations, which are all edges of the ISD sub-scalars that forms a nonempty set A, has been done directly from the connected sub-graphs. So, every ISD version of a scalar k is proven mathematically as the SG-ISD version of k in an elliptic scalar multiplication kP. New experimental results on the proposed SG-ISD method are presented. The computational complexities of the original ISD and proposed SG-ISD methods are determined mathematically on the basis of the counting operations. These operations are elliptic curve and finite field operations. The comparison results on these computational complexities of the ISD and SG-ISD methods have been discussed. The experiments on the computational complexities reveal that the SG-ISD method is faster than the ISD method. Thus, the SG-ISD method is considered as an efficient algorithm in comparison with the original ISD for cryptographic applications.

Machine Learning Attacks and Countermeasures on Hardware Binary Edwards Curve Scalar Multipliers

Machine Learning techniques have proven effective in Side Channel Analysis (SCA), enabling multiple improvements over the already-established profiling process of Template Attacks. Focusing on the need to mitigate their impact on embedded devices, a design model and strategy is proposed that can effectively be used as a backbone for introducing SCA countermeasures on Elliptic Curve Cryptography (ECC) scalar multipliers. The proposed design strategy is based on the decomposition of the round calculations of the Montgomery Power Ladder (MPL) algorithm and the Scalar Multiplication (SM) algorithm into the underlined finite field operations, and their restructuring into parallel-processed operation sets. Having as a basis the proposed design strategy, we showcase how advanced SCA countermeasures can be easily introduced, focusing on randomizing the projective coordinates of the MPL round’s ECC point results. To evaluate the design approach and its SCA countermeasures, several simple ML-based SCAs are performed, and an attack roadmap is provided. The proposed roadmap assumes attackers that do not have access to a huge number of leakage traces, and that have limited resources with which to mount Deep Learning attacks. The trained models’ performance reveals a high level of resistance against ML-based SCAs when including SCA countermeasures in the proposed design strategy.

Flow transition in periodically fully developed wavy channels

In the present study, numerical investigations have been performed to study the flow transition mechanism in wavy channels using finite volume-based open source field operation and manipulation. Two different wavy channel configurations are chosen, which represent two different flow destabilization mechanisms, viz., Kelvin–Helmholtz and centrifugal instabilities. Sinusoidal walls with out-of-phase and in-phase channel configurations have been considered in the present study. Steady to chaotic flow transition in two different channel configurations are investigated by varying Reynolds number. A detailed flow regime map is presented for the two different wavy channel configurations. Unsteady flow features have been illustrated with the help of instantaneous streamlines, velocity contours, vorticity contours, and iso-Q surfaces. For the out-of-phase configuration, the flow changes from two-dimensional steady to two-dimensional unsteady in the Re range of 175–185, and then three-dimensional unsteady flow is observed for the Re varying from 250 to 260. On the contrary, for the in-phase configuration, the transition happens directly from steady two-dimensional flow (Re < 101) to unsteady three-dimensional (Re > 102) in a very narrow range of Re. Transitions in the two different wavy channels have been examined in detail using Hilbert–Huang transformation, phase-space reconstruction, Poincaré section, recurrence plot, and dynamic mode decomposition. Frequency, growth rate, and vortex structures of the dominant modes are illustrated corresponding to each value of Re for the considered channel configurations.

The Computational Complexity of the Elliptic Curve Factorization Algorithm over Real Field

Several mathematical concepts from analytics number theory, especially the counting functions (CFs) are employed to solve some modern problems in mathematics, computer sciences, engineering and others. One of them is the factorization problem for integers into two primes. This work proposes an extended factorization problem using the CFs, as main part from analytics number theory, to factor a real number r into two primes p and q. The computations of the points doubling and addition on the elliptic curves E modulo a composite number n are also used in this extension to give new two versions of the factorization over real field R. On the first version, the primes are obtained from doubling and addition on elliptic curve points that are computed modulo composite number which is resulting as output of the CFs algorithm with the input r. Whereas, the primes, on the second version, are got directly from applying the CFs algorithm with r as input. The successful computation of the scalar multiplication kP on the elliptic curve E modulo primes are determined. The computational complexities of extended elliptic curve factorization versions are determined using the counting operations. These operations are elliptic curve and finite field operations. New numerical results on two versions are computed as study cases. The elliptic curve factorization algorithm over R (ECF-R) with two versions, is more efficient for factoring-based cryptography in comparing to the original ECM.

Efficient Software Implementation of the SIKE Protocol Using a New Data Representation

In the SIKE implementation, the Montgomery representation has been mostly adopted in the finite field arithmetic computing as the corresponding reduction algorithm is considered the fastest method for implementing the modular reduction. In this paper, we propose a new data representation for the supersingular isogeny-based elliptic-curve cryptography (ECC), of which the SIKE is a subclass. The new representation can facilitate faster modular reduction implementation than the Montgomery reduction. Meanwhile, the other finite field arithmetic operations in the ECC can also benefit from the proposed data representation. We have implemented all the arithmetic operations in C language with constant execution time based on our proposed data representation and applied them to the newest SIKE software library. Targeting at the SIKEp751, we run our design and the optimized generic implementation on a 2.6GHz Intel Xeon E5-2690 processor. The experiment results show that for the parameters of SIKEp751, the proposed modular reduction algorithm is about 2.61x faster than the best Montgomery one and our scheme also performs significantly better for the other finite field operations. With these improvements, the overall software implementation for the SIKEp751 achieves about 1.65x speedup compared to the state-of-the-art generic implementatio

An area-efficient ECC architecture over GF([formula omitted]) for resource-constrained applications

Elliptic Curve Cryptography (ECC), an asymmetric-key cryptographic system, received extensive research and industry recognition owing to its reliable security with relatively smaller key sizes. It is most effective with resource-constrained applications. The very intensive function in ECC is point-multiplication. In this article, we propose a novel architecture for elliptic curve point-multiplication based on modified Lopez–Dahab–Montgomery(LDM) point-multiplication algorithm to achieve a reduction in hardware complexity and time complexity. The proposed architectural data-path is pipelined and organized to realize finite-field operations i.e., FF-multiplication and FF-square operations, in parallel to reduce the critical-path delay. The FF-operations are scheduled to perform each iteration of point-addition(PA) and point-doubling(PD) operations in eight clock-cycles without data-dependency. The elliptic curve-point-multiplication(ECPM) implementation over the National Institute of Standards and Technology(NIST) recommended binary curve GF(2163) shows that the proposed design achieves point-multiplication in 3.71μs utilizing 8529 LUTs on Xilinx Virtex-7 FPGA. In addition the design achieves an improvement of 36%, 32%, and 39% area-time efficiency when compared to the best existing designs in the literature when implemented over GF(2163), GF(2233) and GF(2283) respectively.

EFFICIENT OPERATIONS IN LARGE FINITE FIELDS FOR ELLIPTIC CURVE CRYPTOGRAPHIC

An efficient method to compute the finite field multiplication for Elliptic Curve point multiplication at high speed encryption of the message is presented. The methods of the operations are based on dynamic lookup table and modified Horner rule method. The modified Horner rule method is not only to finite field operations but also to Elliptic curve scalar multiplication in the encryption and decryption. By comparison with using Russian Peasant method and in the new proposed method, one of the advantages of utilizing the proposed algorithm is that in the Elliptic Curve point addition are reduced by a factor of three in GF (2163). Therefore, using the Algorithm 1 running on Intel CPU, computation cost of the multiplication method is above 70% faster than using standard multiplication by Russian Peasant method. Ultimately, the proposed Algorithm 1 for evaluating multiplication can be made regular, simple and suitable for software implementations.

ISA Extensions for Finite Field Arithmetic

We present and evaluate a custom extension to the RISC-V instruction set for finite field arithmetic. The result serves as a very compact approach to software-hardware co-design of PQC implementations in the context of small embedded processors such as smartcards. The extension provides instructions that implement finite field operations with subsequent reduction of the result. As small finite fields are used in various PQC schemes, such instructions can provide a considerable speedup for an otherwise software-based implementation. Furthermore, we create a prototype implementation of the presented instructions for the extendable VexRiscv core, integrate the result into a chip design, and evaluate the design on two different FPGA platforms. The effectiveness of the extension is evaluated by using the instructions to optimize the Kyber and NewHope key-encapsulation schemes. To that end, we also present an optimized software implementation for the standard RISC-V instruction set for the polynomial arithmetic underlying those schemes, which serves as basis for comparison. Both variants are tuned on an assembler level to optimally use the processor pipelines of contemporary RISC-V CPUs. The result shows a speedup for the polynomial arithmetic of up to 85% over the basic software implementation. Using the custom instructions drastically reduces the code and data size of the implementation without introducing runtime-performance penalties at a small cost in circuit size. When used in the selected schemes, the custom instructions can be used to replace a full general purpose multiplier to achieve very compact implementations.

Fast Erasure Coding for Data Storage

Various techniques have been proposed in the literature to improve erasure code computation efficiency, including optimizing bitmatrix design and computation schedule, common XOR (exclusive-OR) operation reduction, caching management techniques, and vectorization techniques. These techniques were largely proposed individually, and, in this work, we seek to use them jointly. To accomplish this task, these techniques need to be thoroughly evaluated individually and their relation better understood. Building on extensive testing, we develop methods to systematically optimize the computation chain together with the underlying bitmatrix. This led to a simple design approach of optimizing the bitmatrix by minimizing a weighted computation cost function, and also a straightforward coding procedure—follow a computation schedule produced from the optimized bitmatrix to apply XOR-level vectorization. This procedure provides better performances than most existing techniques (e.g., those used in ISA-L and Jerasure libraries), and sometimes can even compete against well-known but less general codes such as EVENODD, RDP, and STAR codes. One particularly important observation is that vectorizing the XOR operations is a better choice than directly vectorizing finite field operations, not only because of the flexibility in choosing finite field size and the better encoding throughput, but also its minimal migration efforts onto newer CPUs.

Microblaze-based parallel implementations of elliptic curve scalar multiplication over <i>F<SUB align="right">p</i> on FPGA

This paper presents flexible software/hardware parallel architectures for embedded elliptic curve cryptosystem (ECC) on FPGA as multi-processor system on programmable circuit (MPSoPC) design. The implementations perform elliptic curve scalar multiplication (ECSM) over arbitrary prime fields (Fp) using montgomery power ladder (MPL) algorithm and Chudnovsky projective system. Our aim is to achieve the best trade-off between flexibility, area and speed. In fact, the integration of multi Microblaze processors allows not only the flexibility of the overall system but also the exploitation of the parallelism in ECSM computation with several degrees. At the low abstraction level, the critical finite field operation which is Montgomery modular multiplication (MMM) is implemented in hardware Accelerator MMM (AccMMM) core based on the modified high radix-r (r = 232) MMM algorithm. The proposed architectures have been implemented in Xilinx Virtex-5 FPGA. The execution times for performing 256-bit and 521-bit ECSM are 19.98 ms and 81.42 ms, respectively.

An Improved BP Decoding of BATS Codes With Iterated Incremental Gaussian Elimination

In this letter, we propose an improved algorithm for decoding finite-length BATS codes using belief propagation (BP) decoding. Our proposed algorithm iteratively performs BP decoding and incremental Gaussian elimination for improving the decoding performance. Furthermore, instead of directly using Gaussian elimination after BP decoding, the incremental Gaussian elimination has been iteratively used to resume BP decoding, which can noticeably reduce the computational complexity of decoding. The simulation results demonstrate that the proposed decoding algorithm can achieve the same decoding performance as conventional Gaussian elimination while significantly reducing the number of finite field operations in decoding.