Finite Field Operations Research Articles

Array Codes With Local Properties

In general, array codes consist of m × n arrays and in many cases, the arrays satisfy parity constraints along lines of different slopes (generally with a toroidal topology). Such codes are useful for RAID type of architectures, since they allow to replace finite field operations by XORs. We present expansions to traditional array codes of this type, like Blaum-Roth (BR) and extended EVENODD codes, by adding parity on columns. This vertical parity allows for recovery of one or more symbols in a column locally, i.e., by using the remaining symbols in the column without invoking the rest of the array. Properties and applications of the new codes are discussed, in particular to Locally Recoverable (LRC) codes.

On the Security of a Latin-Bit Cube-Based Image Chaotic Encryption Algorithm

In this paper, the security analysis of an image chaotic encryption algorithm based on Latin cubes and bit cubes is given. The proposed algorithm adopts a first-scrambling-diffusion- second-scrambling three-stage encryption scheme. First, a finite field is constructed using chaotic sequences. Then, the Latin cubes are generated from finite field operation and used for image chaotic encryption. In addition, according to the statistical characteristics of the diffusion image in the diffusion stage, the algorithm also uses different Latin cube combinations to scramble the diffusion image for the second time. However, the generation of Latin cubes in this algorithm is independent of plain image, while, in the diffusion stage, when any one bit in the plain image changes, the corresponding number of bits in the cipher image follows the change with obvious regularity. Thus, the equivalent secret keys can be obtained by chosen plaintext attack. Theoretical analysis and experimental results indicate that only a maximum of plain images are needed to crack the cipher image with resolution. The size of equivalent keys deciphered by the method proposed in this paper are much smaller than other general methods of cryptanalysis for similar encryption schemes.

Low-Complexity Elliptic Curve Cryptography Processor Based on Configurable Partial Modular Reduction Over NIST Prime Fields

We proposed a high-performance elliptic curve cryptography (ECC) processor over NIST prime fields. Instead of applying a full modular reduction to a $2{k}$ -bit product, the proposed partial modular reduction method iteratively performs reductions on partial products whose bit length is slightly greater than ${k}$ , where ${k}$ is the bit length of field elements. As a result, the computational complexity of modular multiplication (MM) was significantly reduced. Moreover, the amount of computation is configurable by parameterizing the size of the partial products. This is a very desirable characteristic of the proposed ECC processor, because the hardware complexity and processing time of the entire ECC processor can be adjusted according to the requirements of various Internet of Things environments. Including the proposed MM module, finite field operation modules are integrated into a single module to further reduce the required resources. The proposed ECC processor synthesized using 180-nm CMOS process technology can perform a 256-bit elliptic curve point multiplication in 0.20–0.74 ms with 144.8k–65.4k gate counts. These results and the experimental results in various FPGA devices show that the proposed ECC processor has significantly better throughput per area than the previously reported ones.

A Vendor-Neutral Unified Core for Cryptographic Operations in GF(p) and GF(2m) Based on Montgomery Arithmetic

In the emerging IoT ecosystem in which the internetworking will reach a totally new dimension the crucial role of efficient security solutions for embedded devices will be without controversy. Typically IoT-enabled devices are equipped with integrated circuits, such as ASICs or FPGAs to achieve highly specific tasks. Such devices must have cryptographic layers implemented and must be able to access cryptographic functions for encrypting/decrypting and signing/verifying data using various algorithms and generate true random numbers, random primes, and cryptographic keys. In the context of a limited amount of resources that typical IoT devices will exhibit, due to energy efficiency requirements, efficient hardware structures in terms of time, area, and power consumption must be deployed. In this paper, we describe a scalable word-based multivendor-capable cryptographic core, being able to perform arithmetic operations in prime and binary extension finite fields based on Montgomery Arithmetic. The functional range comprises the calculation of modular additions and subtractions, the determination of the Montgomery Parameters, and the execution of Montgomery Multiplications and Montgomery Exponentiations. A prototype implementation of the adaptable arithmetic core is detailed. Furthermore, the decomposition of cryptographic algorithms to be used together with the proposed core is stated and a performance analysis is given.

Bandwidth Overhead-Free Data Reconstruction Scheme for Distributed Storage Code With Low Decoding Complexity

The $(n,k)$ combination property (CP) is defined as follows: $k$ source packets are mapped into $n \geq k$ packets and any $k$ out of these $n$ packets are able to recover the information of the original $k$ packets. This $(n,k)$ CP is extensively needed by cloud storage service providers. Reed-Solomon (RS) codes possess CP at the cost of high encoding and decoding complexity for two reasons: operation over a large-size finite field and time-consuming matrix inversion operation. By operating within the binary field and by allowing only zigzag decoding at the decoder, binary zigzag decoding that possesses CP lowers the decoding complexity significantly. The drawback is that storage room overhead is needed. Corresponding to this storage room overhead, in the data reconstruction process, intuitively fetching $k$ whole stored packets will consume overhead bandwidth. In this paper, a data reconstruction scheme that is optimal in terms of bandwidth consumption is designed, where optimal means the bandwidth consumption is equal to the volume of data to be reconstructed, namely, no overhead bandwidth is needed. To do that, a universal method of fetching sub-packet is proposed, and its corresponding decoding method is also designed.

Low Complexity Digit Serial Multiplier for Finite Field using Redundant Basis

Cryptography has been increasingly used due to its rapid trends. In recent days, it has been used mostly in communication and in financial transactions through automated machines or internet. The applications of cryptography and coding theory require finite field operations and are realized based on the finite field computations. In this paper efficient digit-serial multiplier over finite field is implemented and is obtained by using Redundant Basis (RB), intend to present highthroughput multiplier. Area and power are the two factors which obtain less when compared to the previous multipliers. The digit-serial multiplier for 32-bit is implemented using Verilog HDL and synthesized to know its better performance in terms of area and power compared to previous multipliers.

Fast Decoding ECC for Future Memories

High-performance storage class memories could benefit from a fast decoding error correcting code (ECC), able to correct a few errors in just a few nanoseconds. The class of BCH codes provides excellent candidates to play this role. The low latency requirement prevents adopting iterative or sequential processes in the encoding and decoding phases-as traditionally done for storage application based on Flash NAND technology. Therefore, we propose an architecture for fast decoding of double and triple ECCs. In our architecture, any time-consuming iterative computation is eliminated, and the most complex evaluations are isolated and carried in parallel with the other terms, to avoid bottlenecks in the decoder. In particular, the error locator polynomial is computed by a combinatorial logic, and its roots are searched by testing all the bits simultaneously. Here, we describe a gate-level design of these architectures. We also give an in-depth analysis of hardware-oriented implementations of finite field operations, and of bases for element representation.

BASIC Codes: Low-Complexity Regenerating Codes for Distributed Storage Systems

In distributed storage systems, regenerating codes can achieve the optimal tradeoff between storage capacity and repair bandwidth. However, a critical drawback of existing regenerating codes, in general, is the high coding and repair complexity, since the coding and repair processes involve expensive multiplication operations in finite field. In this paper, we present a design framework of regenerating codes, which employ binary addition and bitwise cyclic shift as the elemental operations, named BASIC regenerating codes. The proposed BASIC regenerating codes can be regarded as a concatenated code with the outer code being a binary parity-check code, and the inner code being a regenerating code utilizing the binary parity-check code as the alphabet. We show that the proposed functional-repair BASIC regenerating codes can achieve the fundamental tradeoff curve between the storage and repair bandwidth asymptotically of functional-repair regenerating codes with less computational complexity. Furthermore, we demonstrate that the existing exact-repair product-matrix construction of regenerating codes can be modified to exact-repair BASIC product-matrix regenerating codes with much less encoding, repair, and decoding complexity from the theoretical analysis, and with less encoding time, repair time, and decoding time from the implementation results.

О выпуклых многогранниках распределений, сохраняемых операциями конечного поля

О выпуклых многогранниках распределений, сохраняемых операциями конечного поля

On convex polytopes of distributions preserved by finite field operations

On convex polytopes of distributions preserved by finite field operations

Mathematical analysis of the computational complexity of integer sub-decomposition algorithm

In this paper, the computational complexity to compute a scalar multiplication on classes of elliptic curve over a prime field that have efficiently-computable endomorphismsis analyzed mathematically. This scalar multiplication is called integer sub-decomposition (ISD) method, which is based on the GLV method of Gallant, Lambert and Vanstone that was initially proposed in the year 2001. In this work, the mathematical proof of the computational cost of ISD implementation is presented. The computational cost of ISD algorithm has been proven based on the operations counting. Two types of the operations are used, namely, elliptic curve operations represented by elliptic curve point addition A and elliptic curve point doubling D and finite field operations represented by field inversion I, field multiplication M and field squaring S that design the computation of the running time of ISD scalar multiplication.

Light combinators for finite fields arithmetic

This work completes the definition of a library which provides the basic arithmetic operations in binary finite fields as a set of functional terms with very specific features. Such a functional terms have type in Typeable Functional Assembly (TFA). TFA is an extension of Dual Light Affine Logic (DLAL). DLAL is a type assignment designed under the prescriptions of Implicit Computational Complexity (ICC), which characterises polynomial time costing computations.We plan to exploit the functional programming patterns of the terms in the library to implement cryptographic primitives whose running-time efficiency can be obtained by means of the least hand-made tuning as possible.We propose the library as a benchmark. It fixes a kind of lower bound on the difficulty of writing potentially interesting low cost programs inside languages that can express only computations with predetermined complexity. In principle, every known and future ICC compliant programming language for polynomially costing computations should supply a simplification over the encoding of the library we present, or some set of combinators of comparable interest and difficulty.We finally report on the applicative outcome that our library has and which is a reward we get by programming in the very restrictive scenario that TFA provides. The term of TFA which encodes the inversion in binary fields suggested us a variant of a known and efficient imperative implementation of the inversion itself given by Fong. Our variant, can outperform Fong's implementation of inversion on specific hardware architectures.

Improved Iterative Hard- and Soft-Reliability Based Majority-Logic Decoding Algorithms for Non-Binary Low-Density Parity-Check Codes

Non-binary low-density parity-check (LDPC) codes have some advantages over their binary counterparts, but unfortunately their decoding complexity is a significant challenge. The iterative hard- and soft-reliability based majority-logic decoding algorithms are attractive for nonbinary LDPC codes, since they involve only finite field additions and multiplications as well as integer operations and, hence, have significantly lower complexity than other algorithms. In this paper, we propose two improvements to the majority-logic decoding algorithms. Instead of the accumulation of reliability information in the existing majority-logic decoding algorithms, our first improvement is a new reliability information update. The new update not only results in better error performance and fewer iterations on average, but also further reduces computational complexity. Since existing majority-logic decoding algorithms tend to have a high error floor for codes whose parity check matrices have low column weights, our second improvement is a reselection scheme, which leads to much lower error floors, at the expense of more finite field operations and integer operations, by identifying periodic points, reselecting intermediate hard decisions, and changing reliability information.

Joint detection – decoding of majority‐logic decodable non‐binary low‐density parity‐check coded modulation systems: an iterative noise reduction algorithm

In this study, the authors present a low-complexity iterative joint detection–decoding algorithm for majority-logic decodable non-binary low-density parity-check (LDPC) coded modulation systems. In the proposed algorithm, a hard-in–hard-out decoder is combined with a hard-decision signal detector in an iterative manner. Each iteration consists of five phases. Firstly, the detector makes hard decisions based on the iteratively updated ‘received’ signals; secondly, these hard decisions are distributed via variable nodes to check nodes; thirdly, check nodes compute hard extrinsic messages; fourthly, each variable node counts hard extrinsic messages from its adjacent check nodes and feeds back to the detection node the symbol with the most votes as well as the difference between the most votes and the second most votes; finally, these feedbacks are used to shift each ‘received’ signal point along an estimated direction to possibly reduce noise. The proposed algorithm requires only integer operations and finite field operations and consequently can be implemented with simple combinational logic circuits in practical systems. Simulation results show that the proposed algorithm performs well and hence serves as an attractive candidate for trading off performance against complexity for majority-logic decodable non-binary LDPC codes.

Complexity of computation in finite fields

We give a review of some works on the complexity of implementation of arithmetic operations in finite fields by Boolean circuits.

단순 전력분석 공격에 대처하는 타원곡선 암호프로세서의 하드웨어 설계

In this paper hardware implementation of GF(2 191 ) elliptic curve cryptographic coprocessor which supports 7 operations such as scalar multiplication(kP), Menezes-Vanstone(MV) elliptic curve cipher/decipher algorithms, point addition(P+Q), point doubling(2P), finite-field multiplication/division is described. To meet structure resistant against simple power analysis, the ECC processor adopts the Montgomery scalar multiplication scheme which main loop operation consists of the key-independent operations. It has operational characteristics that arithmetic units, such GF_ALU, GF_MUL, and GF_DIV, which have 1, (m/8), and (m-1) fixed operation cycles in GF(2m ), respectively, can be executed in parallel. The processor has about 68,000 gates and its simulated worst case delay time is about 7.8 ns under 0.35um CMOS technology. Because it has about 320 kbps cipher and 640 kbps rate and supports 7 finite-field operations, it can be efficiently applied to the various cryptographic and communication applications.

Generalized high speed Itoh–Tsujii multiplicative inversion architecture for FPGAs

Among all finite field operations, finite field inversion is the most computationally intensive operation. Yet, it is an essential component of several public-key cryptographic algorithms such as elliptic curve cryptography. For hardware implementations over extended binary fields, the Itoh–Tsujii inversion algorithm (ITA) is the most efficient. In this paper we propose acceleration techniques for ITA on FPGA platforms. We first propose a generalization of the parallel ITA which uses exponentiation by 2n and 2n, where n≥1. Parallel ITA has several drawbacks which limit its speed. We propose a novel technique supported with theoretical analysis to overcome the drawbacks. The technique reduces the critical delay of the ITA architecture without increasing the clock cycle requirement. Experimental results are presented to show that the proposed technique outperforms reported results.

Software Implementation of Curve based Cryptography for Constrained Devices

Curve based cryptography are preferred for embedded hardware since they require shorter operand size than RSA to attain the same security level. So ECC and HECC are more suitable in constrained environment such as smart cards if we can select suitable curves and efficient scalar multiplication technique to speed up arithmetic on the curve. With this in view, this paper explores in details the main operations like scalar multiplication, group operations on Jacobian, finite field operations etc which are the prime steps for efficient implementation of ECC / HECC. We also have compared the timings of main operations like scalar multiplication, encryption and decryption of Elliptic and Hyperelliptic curve cryptosystems to study the relative performance of these cryptosystems.

A Low Complexity Decoding Algorithm for Majority-Logic Decodable Nonbinary LDPC Codes

In this letter, we propose a low complexity decoding algorithm for majority-logic decodable nonbinary low-density parity-check (LDPC) codes. The proposed algorithm is initialized with the quantized squared Euclidean distances between the constellation points and the received signals. Like most of the existing reliability-based decoding algorithms, the proposed algorithm requires only integer operations and finite field operations and (hence) can be implemented with simple combinational logic circuits in practical systems. Simulation results show that the proposed algorithm suffers from a little performance degradation compared with FFT-QSPA. The algorithm provides a candidate for trade-offs between performance and complexity.

Two Low-Complexity Reliability-Based Message-Passing Algorithms for Decoding Non-Binary LDPC Codes

This paper presents two low-complexity reliability-based message-passing algorithms for decoding LDPC codes over non-binary finite fields. These two decoding algorithms require only finite field and integer operations and they provide effective trade-off between error performance and decoding complexity compared to the non-binary sum product algorithm. They are particularly effective for decoding LDPC codes constructed based on finite geometries and finite fields.