Finite Field Multiplication Research Articles

Reliable Architecture-Oblivious Error Detection Schemes for Secure Cryptographic GCM Structures

To augment the confidentiality property provided by block ciphers with authentication, the Galois Counter Mode (GCM) has been standardized by the National Institute of Standards and Technology. The GCM is used as an add-on to 128-bit block ciphers, such as the Advanced Encryption Standard (AES), SMS4, or Camellia, to verify the integrity of data. Prior works on the error detection of the GCM either use linear codes to protect the GCM architectures or are based on AES–GCM architectures, confining the mechanisms to the AES block cipher. Although such structures are efficient, they are not only confined to specific architectures of the GCM but might also not fully take advantage of the parallel architectures of the GCM. Moreover, linear codes have been shown to be potentially ineffective with respect to biased faults. In this paper, we propose algorithm-oblivious constructions through recomputing with swapped ciphertext and additional authenticated blocks, which can be applied to the GCM architectures using different finite field multipliers in $GF(2^{128})$ . Such obliviousness for the proposed constructions used in the GCM gives freedom to the designers. We present the results of error simulations and application-specific integrated circuit implementations to demonstrate the utility of the presented schemes. Based on the overhead/degradation tolerance for implementation/performance metrics, one can fine-tune the proposed method to achieve more reliable architectures for the GCM.

An area-efficient bit-serial sequential polynomial basis finite field GF(2m) multiplier

Many cryptographic and error control coding algorithms rely on finite field arithmetic. Hardware implementation of these algorithms requires an efficient realization of finite field GF(2m) arithmetic operations. Finite field multiplication is complex among the basic arithmetic operations, and it is employed in field exponentiation and inversion operations. Various algorithms and architectures are proposed in the literature for hardware implementation of finite field multiplication to achieve a reduction in area and delay. In this paper, a modified interleaved modular reduction multiplication algorithm and its bit-serial sequential architecture are proposed. It is observed from the comparison of analytical results that the proposed architecture achieves the reduction in area and area-delay product compared to the existing multipliers. The proposed multiplier achieves an improvement of 39% in area and 17% in area-delay product estimations for field order of 409 when compared with the best sequential multiplier available in the literature. Application specific integrated circuit (ASIC) implementation of the proposed multiplier together with the two most comparable multipliers confirms that the proposed multiplier outperforms in terms of area and area-delay product. The proposed multiplier is suitable for implementation of security in Internet of Things (IoT) gateways and edge-devices.

Multiplier-Free Implementation of Galois Field Fourier Transform on a FPGA

A novel approach to implementing Galois field Fourier transform (GFT) is proposed that completely eliminates the need for any finite field multipliers by transforming the symbols from a vector representation to a power representation. The proposed method is suitable for implementing GFTs of prime and nonprime lengths on modern FPGAs that have a large amount of on-chip distributed embedded memory. For GFT of length 255 that is widely used in many applications, the proposed memory-based implementation exhibits 25% improvement in latency, 27% improvement in throughput, and 56% reduction in power consumption compared to a finite field multiplier-based implementation.

Efficient multiplications in finite fields for multivariate signatures

Efficient multiplications in finite fields for multivariate signatures

Novel Bit-Parallel and Digit-Serial Systolic Finite Field Multipliers Over $GF(2^m)$ Based on Reordered Normal Basis

Efficient implementation of finite field multipliers based on a reordered normal basis (RNB) is highly desirable in the current/emerging cryptosystems since it offers almost free realization of squaring operation. Therefore, in this paper, we propose novel bit-parallel and digit-serial finite field multipliers over $GF(2^{m})$ based on RNB. By efficient transformation of the core multiplication algorithm using a unique circular shifting feature, we have derived an efficient algorithm for low-complexity systolic mapping. Both bit-parallel and digit-serial structures of the multipliers are then obtained and optimized to enhance the area–time efficiency. We have also utilized the unique feature of the proposed multiplication algorithm to obtain the systolic multipliers by Karatsubalike decomposition. Detailed analysis and comparison show the superior performance of the proposed implementation. For example, the proposed regular and Karatsuba-based bit-parallel designs involve at least 48.4% less area-delay product (ADP) and 42.2% less power-delay product (PDP) than the best existing ones (37.7% and 55.3% less ADP and PDP on field-programmable gate array platform), respectively. The proposed multipliers, because of their lower area–time complexities, can be used for efficient realization of cryptographic applications.

A proof of the Beierle–Kranz–Leander conjecture related to lightweight multiplication in $$\mathbb {F}_{2^n}$$

Lightweight cryptography is an important tool for building strong security solutions for pervasive devices with limited resources. Due to the stringent cost constraints inherent in extremely large applications, the efficient implementation of cryptographic hardware and software algorithms is of utmost importance to realize the vision of generalized computing. In CRYPTO 2016, Beierle, Kranz and Leander have considered lightweight multiplication in $$\mathbb {F}_{2^n}$$. Specifically, they have considered the fundamental question of optimizing finite field multiplications with one fixed element and investigated which field representation, that is which choice of basis, allows for an optimal implementation. They have left open a conjecture related to an XOR-count of two. Using the theory of linear algebra, we prove in the present paper that their conjecture is correct. Consequently, this proved conjecture can be used as a reference for further developing and implementing cryptography algorithms in lightweight devices.

Novel Systolization of Subquadratic Space Complexity Multipliers Based on Toeplitz Matrix–Vector Product Approach

Systolic finite field multiplier over $GF(2^{m})$ , because of its superior features such as high throughput and regularity, is highly desirable for many demanding cryptosystems. On the other side, however, obtaining high-performance systolic multiplier with relatively low hardware cost is still a challenging task due to the fact that the systolic structure usually involves large area complexity. Based on this consideration, in this paper, we propose to carry out two novel coherent interdependent efforts. First, a new digit-serial multiplication algorithm based on polynomial basis over binary field $(GF(2^{m}))$ is proposed. Novel Toeplitz matrix–vector product (TMVP)-based decomposition strategy is employed to derive an efficient subquadratic space complexity. Second, The proposed algorithm is then innovatively mapped into a low-complexity systolic multiplier, which involves less area-time complexities than the existing ones. A series of resource optimization techniques also has been applied on the multiplier which optimizes further the proposed design (it is the first report on digit-serial systolic multiplier based on TMVP approach covering all irreducible polynomials, to the best of our knowledge). The following complexity analysis and comparison confirm the efficiency of the proposed multiplier, that is, it has lower area-delay product (ADP) than the existing ones. The extension of the proposed multiplier for bit-parallel implementation is also considered in this paper.

Optimized Modular Multiplication for Supersingular Isogeny Diffie-Hellman

Recent progress in quantum physics shows that quantum computers may be a reality in the not too distant future. Post-quantum cryptography (PQC) refers to cryptographic schemes that are based on hard problems which are believed to be resistant to attacks from quantum computers. The supersingular isogeny Diffie-Hellman (SIDH) key exchange protocol shows promising security properties among various post-quantum cryptosystems that have been proposed. In this paper, we propose two efficient modular multiplication algorithms with special primes that can be used in SIDH key exchange protocol. Hardware architectures for the two proposed algorithms are also proposed. The hardware implementations are provided and compared with the original modular multiplication algorithm. The results show that the proposed finite field multiplier is over 6.79 times faster than the original multiplier in hardware. Moreover, the SIDH hardware/software codesign implementation using the proposed FFM2 hardware is over 31 percent faster than the best SIDH software implementation.

Analysis on FPGA Designs of Parallel High Performance Multipliers

For many applications from the areas of cryptography and coding, finite field multiplication is the most resource and time consuming operation. In this paper, optimized high performance parallel GF(2233) multipliers for an FPGA realization were designed and the time and area complexities were analyzed. One of the multipliers uses a new hybrid structure to implement the Karatsuba algorithm. For increasing performance, we make excessive use of pipelining and efficient control techniques and use a modern state-of-the-art FPGA technology. As a result we have, to our knowledge, the first hardware realization of sub quadratic arithmetic and currently the fastest and most efficient implementation of 233 bit finite field multipliers

Low‐complexity unidirectional systolic Dickson basis multiplier for lightweight cryptosystems

Finite field multiplier is a very important operation for realising elliptic curve cryptography. Dickson basis is a recently developed basis for representing finite elements in GF(2 m ). This study will propose a unidirectional systolic multiplier for such Dickson basis. The unidirectional systolic structure offers low space and time complexities and can be easily modified to have error detection capability which can resist side-channel attacks.

Gaps between prime numbers and tensor rank of multiplication in finite fields

We present effective upper bounds on the symmetric bilinear complexity of multiplication in extensions of a base finite field $$\mathbb {F}_{p^2}$$ of prime square order, obtained by combining estimates on gaps between prime numbers together with an optimal construction of auxiliary divisors for multiplication algorithms by evaluation-interpolation on curves. Most of this material dates back to a 2011 unpublished work of the author, but it still provides the best results on this topic at the present time. Then a few updates are given in order to take recent developments into account, including comparison with a similar work of Ballet and Zykin, generalization to classical bilinear complexity over $$\mathbb {F}_p$$ , and to short multiplication of polynomials, as well as a discussion of open questions on gaps between prime numbers or more generally values of certain arithmetic functions.

Efficient systolic multiplications in composite fields for cryptographic systems

Multiplications in finite fields are playing a key role in areas of cryptography and mathematic. We present approaches to exploit systolic architecture for multiplications in composite fields, which are expected to reduce the time-area product substantially. We design a pipelined architecture for multiplications in composite fields \begin{document} $GF({({2^n})^2})$ \end{document} , where \begin{document} $n$ \end{document} is a positive integer. Besides, we design systolic architectures for multiplications and additions in finite fields \begin{document} $GF(2^n)$ \end{document} . By integrating main improvements and other minor optimizations for multiplications in \begin{document} $GF({({2^n})^2})$ \end{document} , the non-pipelined versions of our design takes \begin{document} $8n+4$ \end{document} AND gates and \begin{document} $8n$ \end{document} XOR gates to compute multiplications with the executing time of \begin{document} $nT_{AND}+4nT_{XOR}$ \end{document} , where \begin{document} $T_{AND}$ \end{document} and \begin{document} ${T_{XOR}}$ \end{document} are delays of AND and XOR gates respectively; with the aid of pipelining, the pipelined version of our design has a throughput rate of one result per \begin{document} $2nT_{XOR}$ \end{document} . Other words, the time complexity and area complexity of our design are \begin{document} $O(n)$ \end{document} . Thus, the complexity of time-area product of our design is \begin{document} $O(n^2)$ \end{document} . Experimental results and comparisons show that our design provides significant reductions in executing time and area of multiplications.

Efficient VLSI Implementation of a Sequential Finite Field Multiplier Using Reordered Normal Basis in Domino Logic

In this paper, a high-speed power-efficient VLSI implementation of a finite field multiplier in GF( $2^{m}$ ) is presented. The proposed design has a serial-in parallel-out architecture and performs the multiplication operation using a reordered normal basis. The basic idea is to implement the main building block of the multiplier in domino logic to reduce the critical path delay. Reduction in dynamic power consumption is achieved by limiting the contention current between the keeper transistor and the pull-down network at the beginning of the evaluation phase by employing a new keeper control circuit. The semicustom layout of the multiplier was realized in 65-nm CMOS technology. The post place-and-route simulations showed that the multiplier can perform multiplication correctly up to a clock rate of 3.85 GHz and consumes marginally less power than the static CMOS counterpart (also implemented with custom placement and route). The size of the multiplier is currently recommended by the National Institute of Standards and Technology for binary field multiplication in elliptic curve cryptography. The proposed design methodology can also be used in the implementation of similar finite field multipliers possessing regular architectures.

High-Performance Pipelined Architecture of Point Multiplication on Koblitz Curves

Point multiplication is the key operation that dominates the speed and area of each elliptic curve cryptosystem. In this brief, we propose a highly efficient architecture for point multiplication on Koblitz curves. The right-to-left point multiplication algorithm is adopted to allow parallel computation of Frobenius maps and point additions. In order to achieve short latency as well as high frequency, we explore operation rescheduling in consecutive point additions with a pipelined bit-parallel finite field multiplier accumulator. Furthermore, the pipelined mixed-form double-digit scalar converter with compact recoding is employed to reduce the wait time and consumed logic resources by scalar conversion. Fast inversion based on optimal addition chains is used to further reduce the latency. Implementation results on Xilinx Virtex V show that the proposed architecture can perform a point multiplication in as few as 2.50, 4.09, 5.81, 9.50, $18.51~ {\mu }\text{s}$ over the five NIST Koblitz curves K-163, K-233, K-283, K-409, and K-571, respectively. To the best of our knowledge, the proposed architecture of point multiplication has the fastest speed in comparison to the reported results.

Dense families of modular curves, prime numbers and uniform symmetric tensor rank of multiplication in certain finite fields

We obtain new uniform bounds for the symmetric tensor rank of multiplication in finite extensions of any finite field $$\mathbb {F}_p$$ or $$\mathbb {F}_{p^2}$$ where p denotes a prime number $$\ge 5$$ . In this aim, we use the symmetric Chudnovsky-type generalized algorithm applied on sufficiently dense families of modular curves defined over $$\mathbb {F}_{p^2}$$ attaining the Drinfeld–Vladuts bound and on the descent of these families to the definition field $$\mathbb {F}_p$$ . These families are obtained thanks to prime number density theorems of type Hoheisel, in particular a result due to Dudek (Funct Approx Commmentarii Math, 55(2):177–197, 2016).

Low Register-Complexity Systolic Digit-Serial Multiplier Over Based on Trinomials

Digit-serial systolic multipliers over $GF(2^m)$ based on the National Institute of Standards and Technology (NIST) recommended trinomials play a critical role in the real-time operations of cryptosystems. Systolic multipliers over $GF(2^m)$ involve a large number of registers of size $O(m^2)$ which results in significant increase in area complexity. In this paper, we propose a novel low register-complexity digit-serial trinomial-based finite field multiplier. The proposed architecture is derived through two novel coherent interdependent stages: (i) derivation of an efficient hardware-oriented algorithm based on a novel input-operand feeding scheme and (ii) appropriate design of novel low register-complexity systolic structure based on the proposed algorithm. The extension of the proposed design to Karatsuba algorithm (KA)-based structure is also presented. The proposed design is synthesized for FPGA implementation and it is shown that it (the design based on regular multiplication process) could achieve more than 12.1 percent saving in area-delay product and nearly 2.8 percent saving in power-delay product. To the best of the authors’ knowledge, the register-complexity of proposed structure is so far the least among the competing designs for trinomial based systolic multipliers (for the same type of multiplication algorithm).

Design and Implementation of a Novel Bit-Parallel Systolic Multiplier Over GF(2m) for Irreducible Pentanomials

Cryptography in current digital world offers integrity and confidentiality of data being transferred over a communication network. Modern cryptography provides such security through cryptographic algorithms which mainly involve multiplication operation in finite fields. Since the finite field multiplication operation is a computationally intensive operation, various algorithms and architectures are proposed in the literature to obtain efficient finite field multiplications in both hardware and software. In this paper, a modified interleaved multiplication algorithm to perform multiplication of two finite field elements over GF(2m) for pentanomials is derived from a conventional interleaved multiplication algorithm using a novel Pre-Computation (PC) technique to reduce the computational complexity of the algorithm. Consequently, an m-bit systolic multiplier for pentanomials (SMP) is designed by employing the proposed algorithm. Hardware and delay complexity analysis is performed and comparison of the proposed SMP structure with similar multipliers available in the literature is presented. The SMP structure achieves about 28% improvement in hardware for [Formula: see text] when compared with the best multiplier available in the literature. The functionality of the proposed SMP structure is verified by implementing on a field-programmable gate array (FPGA) Virtex-7 (XC7V2000TFLG1925-2) prototype board and synthesizing in application specific integrated circuit (ASIC) using Synopsys Design Vision compiler with 90[Formula: see text]nm generic library. It can be observed from FPGA and ASIC implementation results that the proposed SMP structure shows improvement in area and power consumption when compared with similar multipliers available in the literature.

Low Complexity Implementation of Unified Systolic Multipliers for NIST Pentanomials and Trinomials Over <inline-formula> <tex-math notation="LaTeX">$\textit{GF}(2^{m})$ </tex-math> </inline-formula>

Systolic finite field multiplier over $\textit {GF}(2^{m})$ based on the National Institute of Standards and Technology (NIST) recommended pentanomials or trinomials can be used as a critical component in many cryptosystems. In this paper, for the first time, we propose a novel low-complexity unified (hybrid field size) systolic multiplier for NIST pentanomials and trinomials over $\textit {GF}(2^{m})$ . We have proposed a computation-core-based design strategy to obtain the desired low-complexity unified multiplier for both NIST pentanomials and trinomials. The proposed multiplier can swift between pentanomial-based and trinomial-based multipliers through a control signal. First of all, a novel strategy is briefly introduced to implement a certain matrix-vector multiplication, which can be packed as a standard computation core (or computation core like). Then, based on the computation-core concept, a novel unified multiplication algorithm is derived that it can realize both the pentanomial-based and trinomial-based multiplications. After that, an efficient systolic structure is presented that it can fully employ the introduced computation core. A detailed example of the proposed unified multiplier (for $\textit {GF}(2^{163})$ and $\textit {GF}(2^{233})$ ) is also presented. Both the theoretical and field-programmable gate array implementation results show that the proposed design has efficient performance in area-time-power complexities, e.g., the proposed design (the one performs $\textit {GF}(2^{163})$ and $\textit {GF}(2^{233})$ multiplications) is found to have at least 14.2% and 13.3% less area-delay product and power-delay product than the combination of the existing individual $\textit {GF}(2^{163})$ and $\textit {GF}(2^{233})$ multipliers (best among all competing designs), respectively. Because of its structural regularity and functional flexibility, the proposed unified multiplier can be used as an intellectual property core for various cryptosystems.

Analysis of Systolic Penalties and Design of Efficient Digit-Level Systolic-like Multiplier for Binary Extension Fields

Systolic designs are considered as suitable candidate for high-speed VLSI realization for their inherent advantages of simplicity, regularity, modularity, and local interconnections. During the past few decades several systolic designs of finite field multipliers have been proposed in the literature. They are popularly used to achieve very high-throughput rate without any centralized control. But, all these designs incorporate heavy systolic penalties in terms of register complexity and latency of computation. We have analyzed here the hidden systolic penalties in those multipliers and proposed a digit-level systolic-like structure and a super-systolic-like structure for finite field multiplication. We have shown that the key issues to obtain such designs are the choice of design layout and digit size which substantially affect the register complexity, critical path, and latency. We have determined the optimal digit size and design layout to reduce the systolic penalties and at the same time to achieve lower critical path, higher-throughput rate, and lower latency with less register complexity with lower overall area complexity.

High-speed hardware architecture for implementations of multivariate signature generations on FPGAs

Multivariate signature belongs to Multivariate-Quadratic-Equations Public Key Cryptography (MPKC), which is secure to quantum computer attacks. Compared with RSA and ECC, it is required to speed up multivariate signature implementations. A high-speed hardware architecture for signature generations of a multivariate scheme is proposed in this paper. The main computations of signature generations of multivariate schemes are additions, multiplications, inversions, and solving systems of linear equations (LSEs) in a finite field. Thus, we improve the finite field multiplications via using composite field expression and design a finite field inversion via using binary trees. Besides, we improve solving LSEs in a finite field based on a variant algorithm of Gauss-Jordan elimination and use the XOR gates to compute additions. We implement the high-speed hardware architecture based on the above improvements on an Altera Stratix Field-Programmable Gate Array (FPGA), which shows that it takes only 90 clock cycles and 0.9 μs to generate a multivariate signature. The comparison shows that the hardware architecture is much faster than other implementations.