Finite Field Multiplication Research Articles

Pyecsca: Reverse engineering black-box elliptic curve cryptography via side-channel analysis

Side-channel attacks on elliptic curve cryptography (ECC) often assume a white-box attacker who has detailed knowledge of the implementation choices taken by the target implementation. Due to the complex and layered nature of ECC, there are many choices that a developer makes to obtain a functional and interoperable implementation. These include the curve model, coordinate system, addition formulas, and the scalar multiplier, or lower-level details such as the finite-field multiplication algorithm. This creates a gap between the attack requirements and a real-world attacker that often only has black-box access to the target – i.e., has no access to the source code nor knowledge of specific implementation choices made. Yet, when the gap is closed, even real-world implementations of ECC succumb to side-channel attacks, as evidenced by attacks such as TPM-Fail, Minerva, the Side Journey to Titan, or TPMScan [MSE+20; JSS+20; RLM+21; SDB+24].We study this gap by first analyzing open-source ECC libraries for insight into realworld implementation choices. We then examine the space of all ECC implementations combinatorially. Finally, we present a set of novel methods for automated reverse engineering of black-box ECC implementations and release a documented and usable open-source toolkit for side-channel analysis of ECC called pyecsca.Our methods turn attacks around: instead of attempting to recover the private key, they attempt to recover the implementation configuration given control over the private and public inputs. We evaluate them on two simulation levels and study the effect of noise on their performance. Our methods are able to 1) reverse-engineer the scalar multiplication algorithm completely and 2) infer significant information about the coordinate system and addition formulas used in a target implementation. Furthermore, they can bypass coordinate and curve randomization countermeasures.

Enhancing Field Multiplication in IoT Nodes with Limited Resources: A Low-Complexity Systolic Array Solution

Enhancing Field Multiplication in IoT Nodes with Limited Resources: A Low-Complexity Systolic Array Solution

High Performance M-Term Karatsuba-Like Multiplier for Finite Field Arithmetic

Abstract: Finite field multiplication plays a crucial role in cryptographic circuits due to its widespread application. However, building circuits for these multiplications poses significant challenges due to their complexity. To mitigate this, the Karatsuba algorithm is employed, dividing each number into n/2 bits to reduce space complexity. While this approach reduces space complexity, it also increases time complexity. In our research, we introduce a hybrid approach, implementing a Karatsuba-like multiplier that combines elements of both Karatsuba and SBM (school book multiplication) techniques. Here in the proposed design, we replace the Array multiplier with a Wallace tree multiplier to further enhance design performance. This combination effectively reduces both time and space complexity. Our findings, based on reported device utilization and latency, demonstrate that the proposed multiplier outperforms the standard Karatsuba multiplier in terms of speed and efficiency, particularly in the area–delay product metric.

3D medical image encryption algorithm using biometric key and cubic S-box

Considering the scarcity of research on 3D medical image encryption, this paper proposes a novel 3D medical image encryption scheme based on biometric key and cubic S-box. To enhance the data security, biometric keys are utilized to overcome the limitations of traditional methods where secret keys with no practical meaning, fixed length, and finite key space, while cubic S-box is constructed to increase the nonlinearity of image cryptosystem. The proposed cryptosystem mainly consists of four phases: pseudo-random sequence generation, confusion, substitution, and diffusion. Firstly, the stepwise iterative algorithm based on coupled chaotic systems is utilized for generating pseudo-random sequences for confusion and diffusion. Secondly, the confusion algorithm based on multiple sorting can scramble pixel positions in 3D images. Thirdly, guided by the designed cubic S-box, pixel substitution is executed sequentially. Lastly, the diffusion algorithm based on ECA and finite field multiplication is capable of increasing the plaintext sensitivity of cryptosystem by concealing the statistical characteristics of plaintext. Simulation experiments performed on multiple 3D medical images demonstrate that the proposed encryption scheme exhibits favorable statistical performance, sufficiently large key space, strong system sensitivity and robustness, and can resist various typical cryptographic attacks.

RGMU: A High-flexibility and Low-cost Reconfigurable Galois Field Multiplication Unit Design Approach for CGRCA

Finite field multiplication is a non-linear transformation operator that appears in the majority of symmetric cryptographic algorithms. Numerous specified finite field multiplication units have been proposed as a fundamental module in the coarse-grained reconfigurable cipher logic array to support more cryptographic algorithms; however, it will introduce low flexibility and high overhead, resulting in reduced performance of the coarse-grained reconfigurable cipher logic array. In this article, a high-flexibility and low-cost reconfigurable Galois field multiplication unit (RGMU) is proposed to balance the tradeoffs between the function, delay, and area. All the finite field multiplication operations, including maximum distance separable matrix multiplication, parallel update of Fibonacci linear feedback shift register, parallel update of Galois linear feedback shift register, and composite field multiplication, are analyzed and two basic operation components are abstracted. Further, a reconfigurable finite field multiplication computational model is established to demonstrate the efficacy of reconfigurable units and guide the design of RGMU with high performance. Finally, the overall architecture of RGMU and two multiplication circuits are introduced. Experimental results show that the RGMU can not only reduce the hardware overhead and power consumption but also has the unique advantage of satisfying all the finite field multiplication operations in symmetric cryptography algorithms.

Exploring the solution space: CB-WCA for efficient finite field multiplication in post-quantum cryptography

Exploring the solution space: CB-WCA for efficient finite field multiplication in post-quantum cryptography

Look-up the Rainbow: Table-based Implementation of Rainbow Signature on 64-bit ARMv8 Processors

The Rainbow Signature Scheme is one of the finalists in the National Institute of Standards and Technology (NIST) Post-Quantum Cryptography (PQC) standardization competition, but failed to win because it has lack of stability in the parameter selection. It is the only signature candidate based on a multivariate quadratic equation. Rainbow signatures have smaller signature sizes compared with other post-quantum cryptography candidates. However, they require expensive tower-field based polynomial multiplications. In this article, we propose an efficient implementation of Rainbow signatures using a look-up table–based multiplication method. The polynomial multiplications in Rainbow signatures are performed on the 𝔽 16 field, which is divided into sub-fields 𝔽 4 and 𝔽 2 under the tower-field method. To accelerate the multiplication process on target processors, we propose a look-up table–based tower-field multiplication technique. In 𝔽 16 , all values are expressed in 4-bit data format and can be implemented using a 256-byte look-up table access. The implementation uses the TBL and TBX instructions of the 64-bit ARMv8 target processor. For Rainbow III and Rainbow V, they are computed on the 𝔽 256 field using an additional 16-byte table instead of creating a new look-up table. The proposed technique uses the vector registers of 64-bit ARMv8 processors and can calculate 16 result values with a single instruction. We also proposed implementations that are resistant to timing attacks. There are two types of implementations. The first one is the cache side-attack resistant implementation, which utilizes the 128-byte cache lines of the M1 processor. In this implementation, cache misses do not occur, and cache hits always occur. The second type is the constant-time implementation. This method takes a step-by-step approach to finding the required look-up table value and ensures that the same number of accesses is made regardless of which look-up table value is called. This implementation is designed to be constant-time, meaning it does not leak timing information. Our experiments on modern Apple M1 processors showed up to 428.73× and 114.16× better performance for finite field multiplications and Rainbow signatures schemes, respectively, compared with previous reference implementations. To the best of our knowledge, this proposed Rainbow implementation is the first optimized Rainbow implementation for 64-bit ARMv8 processors.

Domain-oriented masked bit-parallel finite-field multiplier against side-channel attacks

Side-Channel Analysis (SCA) constitutes a serious threat to the security of implemented cryptosystems. In SCA, the attacker can obtain information leakage from a device executing cryptographic algorithms by means of the measure of side-channels such as power consumption, electromagnetic radiation and execution time. For this reason, effective countermeasures against SCA are indispensable in implemented cryptographic devices. The use of masking schemes (in which intermediate computations are independent from the sensible input data) constitutes the most effective approach to achieve resistance against physical attacks. Among the different masking methods proposed for hardware, domain-oriented masking is one of the most promising due to its lower implementation costs, level of security and glitch resistance. In this paper, a new bit-parallel first-order domain-oriented masked finite field multiplier is presented which incorporates the addition of fresh random values without increasing the computation delay. Explicit expressions for the computation of the new masked multiplier for the binary extension field used in the Advanced Encryption Standard (AES) are also given.

A quantum algorithm for Toeplitz matrix-vector multiplication

Toeplitz matrix-vector multiplication is widely used in various fields, including optimal control, systolic finite field multipliers, multidimensional convolution, etc. In this paper, we first present a non-asymptotic quantum algorithm for Toeplitz matrix-vector multiplication with time complexity , where κ and 2n are the condition number and the dimension of the circulant matrix extended from the Toeplitz matrix, respectively. For the case with an unknown generating function, we also give a corresponding non-asymptotic quantum version that eliminates the dependency on the L 1-norm ρ of the displacement of the structured matrices. Due to the good use of the special properties of Toeplitz matrices, the proposed quantum algorithms are sufficiently accurate and efficient compared to the existing quantum algorithms under certain circumstances.

Low-Space Complexity Finite Field Multiplier Using Both Dickson and Polynomial Bases

Low-Space Complexity Finite Field Multiplier Using Both Dickson and Polynomial Bases

Reliable Architectures for Finite Field Multipliers Using Cyclic Codes on FPGA Utilized in Classic and Post-Quantum Cryptography

Fault detection is becoming greatly important in protecting cryptographic designs that can suffer from both natural or malicious faults. Finite fields over <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text {GF}(2^{m})$ </tex-math></inline-formula> are widely used in such designs, since their data are coded in binary form for practical reasons. Among the different finite field arithmetic, multiplication is the bottleneck operation for many cryptosystems due to its complexity. Therefore, in this work, fault detection schemes based on cyclic codes for finite field multipliers using different fields found in traditional and post-quantum cryptography are derived. Moreover, we implement such schemes by embedding them into the original architectures to perform an exhaustive study, benchmark the different overheads obtained, and prove their suitability for deeply constrained embedded systems. These implementations are performed on advanced micro devices (AMD)/Xilinx field-programmable gate array (FPGA) and provide a very high error coverage with acceptable overhead.

Low-Complexity One-Dimensional Parallel Semi-Systolic Structure for Field Montgomery Multiplication Algorithm Perfect for Small IoT Edge Nodes

The use of IoT technology in several applications is hampered by security and privacy concerns with IoT edge nodes. Security flaws can only be resolved by implementing cryptographic protocols on these nodes. The resource constraints of the edge nodes make it extremely difficult to implement these protocols. The majority of cryptographic protocols’ fundamental operation is finite-field multiplication, and their performance is significantly impacted by their effective implementation. Therefore, this work mainly focuses on implementing low-area with low-energy and high-speed one-dimensional bit-parallel semi-systolic multiplier for the Montgomery multiplication algorithm. The space and delay complexity analysis of the proposed multiplier structure reveals that the proposed design has a significant reduction in delay and a marginal reduction in the area when compared to the competitive one-dimensional multipliers. The obtained ASIC synthesis report demonstrates that the suggested multiplier architecture saves a marginal amount of space as well as a significant amount of time, area–delay product (ADP), and power–delay product (PDP) when compared to the competitive ones. The obtained results indicate that the proposed multiplier layout is very appropriate for use in devices with limited resources such as IoT edge nodes and tiny embedded devices.

A Novel Multiplier Hardware Organization for Finite Fields Defined by All-One Polynomials

In this brief, a novel, energy-efficient hardware organization for a finite-field multiplier based on irreducible all-one polynomials (AOPs) is proposed. The proposed AOP multiplier organization deploys three distinct submodules, which constitute a left-shifting network (reduction), an AND network (multiplication), and a three-input XOR tree (accumulation). Previously reported state-of-the-art implementation distributes these operations to systolic arrays, which are elegant in layout but do not yield the most efficient solution. The advantages of the proposed organization compared with those reported in the literature include reduced cost and power dissipation for a given clock frequency constraint (or increased clock frequency for a given power constraint) and the absence of bypassing problems due to fewer pipeline stages. Both the previously reported and the proposed organizations have been implemented in Verilog for three different binary-field sizes using the TSMC 90 nm standard cell library and have been synthesized for three distinct frequency targets using Cadence Genus Synthesis tool. The proposed organization achieves 18%, 31%, and 19% reduction in average leakage, dynamic capacitance, and area, respectively, compared with state-of-the-art schemes and thus can be considered for energy-efficient, compact portable systems, including wireless sensors.

Hardware Optimization and System Design of Elliptic Curve Encryption Algorithm Based on FPGA

Since entering the era of big data, the degree of information sharing is getting higher and higher; the information exchange is becoming more and more convenient, but at the same time, personal information is also easy to be exposed to the network environment, if it is used by criminals to lead to information leakage, and then bring certain risks. Therefore, it is in the information age and do a good job of network information security and confidentiality. At present, the security and secrecy of network information are mainly realized by cryptography. Public key cryptography can encrypt information and ensure the security of information transmission, so it is widely used in the contemporary society. At present, elliptic curve encryption is highly respected in the research field of public key cryptosystem. Elliptic curve encryption is divided into two main points, multiplication and inversion, respectively. Through the comparison of these two algorithms, it can be found that there are several choices if the main research objective is to save time, and the Euclidean extension method is mainly discussed in this paper. In other words, more efficient algorithms are used in the hardware implementation process, and a variety of algorithms can be used instead of a single curve algorithm. In this process, we can find the special features of upper level operation and bottom level finite operation. The upper level operation is KP operation, while the bottom level operation is fast calculation of four kinds of K in finite field operation, and finally realize FPGA algorithm. With the help of Quartus ii developed by predecessors, the upper and lower operations of elliptic curve are carried out using VHDL language. Combined ANXIX9.62 in the elliptic curve of each module to test, so as to ensure the accuracy of the data, reduces the error. According to the test results, the designed chip can efficiently complete the elliptic curve encryption system in the whole process. And the average KP operation time can reach 15.15 ms at 20 MHz frequency. At the same time, the chip can complete the operation on ECC public key with any variable curve in F domain less than 256. Therefore, this chip is a high-speed elliptic curve cryptographic chip with optional system parameters. Based on this, this article on the elliptic curve encryption algorithm based on FPGA hardware implementation of system design, from the view of mathematical study analysis, was carried out on the elliptic curve cryptosystem, according to the above two big difficulty, namely, the polynomial of GF(2), the finite field multiplication, and inversion; there will be a detailed studies of discussion, through software comparison to find the differences between different software, especially the software implementation performance level. In addition, it will also focus on the design of elliptic curve algorithm PGA, so as to explore the solution of the algorithm hardware.

Step-by-Step Decoding of Binary Quasi-Reversible BCH Codes

Binary quasi-reversible BCH codes whose defining set contains consecutive elements from negative to positive integers have received considerable attention in recent years due to their efficient decoding suitable for a wide range of applications. This paper combines the concept of the weight and quasi-reversible structures to introduce two subclasses of BCH codes: odd-like/even-like quasi-reversible BCH codes. The step-by-step decoding of these codes is developed as follows: First, the weight evaluation of a received polynomial is able to judge whether the number of errors is odd or even, which helps to simplify the decoding processes. Second, based on Chiò’s pivotal condensation process which can be easily implemented in a parallel computing architecture, the determinant calculation of the band matrix instead of Peterson’s matrix in column-echelon form is faster. Third, a newly proposed non-monic error-locator polynomial is sparser than the conventional ones. As a consequence, the theoretical analysis and experimental results validate potential benefits in requiring fewer finite field additions and multiplications used in the decoding of binary odd-like/even-like quasi-reversible BCH codes up to half the minimum distance when compared with the narrow-sense BCH codes with small error-correcting capability.

A High-Performance SIKE Hardware Accelerator

Supersingular isogeny key encapsulation (SIKE) is a promising candidate in the NIST postquantum cryptography (PQC) standardization process, which has the smallest key lengths. It is the only isogeny-based cryptographic scheme in the NIST list that leverages the traditional elliptic curve cryptography (ECC) arithmetic; however, the high computational complexity is one of its limiting factors. In this work, we proposed a high-performance hardware architecture for the SIKE protocol. The architecture includes an improved multiplier based on the high-performance finite field multiplication (HFFM) algorithm which is 15%–20.7% faster than the previous multiplier based on the HFFM algorithm and a unified adder/subtractor with radix <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3^{b}$ </tex-math></inline-formula> . In addition, it also comprises an efficient scheduler strategy that decomposes all the functions of SIKE into finite field <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$F_{p}$ </tex-math></inline-formula> and then effectively schedules through optimized multiplication chains for maximal performance. The proposed architecture is synthesized and implemented on Xilinx Virtex-7 FPGA for all the four variants of SIKE having security levels from 1 to 5 and achieved 2.6%–7.8% faster speeds as well as consumed less equivalent number of slices (ENS) than the state-of-the-art designs. In the comparison of area and time (AT), the proposed architecture is 14.2%–34.5% lower than the previous architecture.

An Optimized M-Term Karatsuba-Like Binary Polynomial Multiplier for Finite Field Arithmetic

Finite field multiplication is a fundamental and frequently used operation in various cryptographic circuits and systems. Because of its high complexity, this operation generally determines the overall complexity and cost of these systems. Therefore, finite field multipliers and their hardware implementation have received considerable attention from researchers. This article proposes a methodology to design an efficient Galois field multiplier. First, space and time complexities for theoretical and field-programmable gate array (FPGA) implementations of M-term Karatsuba-like finite field multipliers were obtained. In addition, an algorithm was developed to obtain an efficient design based on a composite M-term Karatsuba-like multiplier. Furthermore, the proposed multipliers were verified and implemented on various FPGA devices, and implementation results were presented. Reported device utilization and latency indicated that the proposed multiplier is roughly 26% faster and 15% more efficient in the area–delay product compared to the standard Karatsuba multiplier. Moreover, comparison with state of the art also indicated that the proposed design is leading in terms of effectiveness and speed.

A Scalable Digit-Parallel Polynomial Multiplier Architecture for NIST-Standardized Binary Elliptic Curves

This work presents a scalable digit-parallel finite field polynomial multiplier architecture with a digit size of 32 bits for NIST-standardized binary elliptic fields. First, a dedicated digit-parallel architecture is proposed for each binary field recommended by NIST, i.e., 163, 233, 283, 409 and 571. Then, a scalable architecture having support for all variants of binary fields of elliptic curves is proposed. For performance investigation, we have compared dedicated multiplier architectures with scalable design. After this, the dedicated and scalable architectures are compared with the most relevant state-of-the-art multipliers. All multiplier architectures are implemented in Verilog HDL using the Vivado IDE tool. The implementation results are reported on a 28 nm Virtex-7 FPGA technology. The dedicated multipliers utilize slices of 1182 (for m=163), 1451 (for m=233), 1589 (for m=283), 2093 (for m=409) and 3451 (for m=571). Moreover, our dedicated designs can operate at a maximum frequency of 500, 476, 465, 451 and 443 MHz. Similarly, for all supported binary fields, our scalable architecture (i) utilizes 3753 slices, (ii) achieves 305 MHz clock frequency, (iii) takes 0.013 μs for one finite field multiplication and (iv) consumes 3.905 W power. The proposed scalable digit-parallel architecture is more area-efficient than most recent state-of-the-art multipliers. Consequently, the reported results and comparison to the state of the art reveal that the proposed architectures are well suited for cryptographic applications.

Throughput/Area Optimized Architecture for Elliptic-Curve Diffie-Hellman Protocol

This paper presents a high-speed and low-area accelerator architecture for shared key generation using an elliptic-curve Diffie-Hellman protocol over GF(2233). Concerning the high speed, the proposed architecture employs a two-stage pipelining and a Karatsuba finite field multiplier. The use of pipelining shortens the critical path which ultimately improves the clock frequency. Similarly, the employment of a Karatsuba multiplier decreases the required number of clock cycles. Moreover, an efficient rescheduling of point addition and doubling operations avoids data hazards that appear due to pipelining. Regarding the low area, the proposed architecture computes finite field squaring and inversion operations using the hardware resources of the Karatsuba multiplier. Furthermore, two dedicated controllers are used for efficient control functionalities. The implementation results after place-and-route are provided on Virtex-7, Spartan-7, Artix-7 and Kintex-7 FPGA (field-programmable gate arrays) devices. The utilized FPGA slices are 5102 (on Virtex-7), 5634 (on Spartan-7), 5957 (on Artix-7) and 6102 (on Kintex-7). In addition to this, the time required for one shared-key generation is 31.08 (on Virtex-7), 31.68 (on Spartan-7), 31.28 (on Artix-7) and 32.51 (on Kintex-7). For performance comparison, a figure-of-merit in terms of throughputarea is utilized which shows that the proposed architecture is 963.3 and 2.76 times faster as compared to the related architectures. In terms of latency, the proposed architecture is 302.7 and 132.88 times faster when compared to the most relevant state-of-the-art approaches. The achieved results and performance comparison prove the significance of presented architecture in all those shared key generation applications which require high speed with a low area.

Hardware Implementation of Efficient Elliptic Curve Scalar Multiplication using Vedic Multiplier

This paper presents an area efficient and high-speed FPGA implementation of scalar multiplication using a Vedic multiplier. Scalar multiplication is the most important operation in Elliptic Curve Cryptography(ECC), which used for public key generation and the performance of ECC greatly depends on it. The scalar multiplication is multiplying integer k with scalar P to compute Q=kP, where k is private key and P is a base point on the Elliptic curve. The Scalar multiplication underlying finite field arithmetic operation i.e. addition multiplication, squaring and inversion to compute Q. From these finite field operations, multiplication is the most time-consuming operation, occupy more device space and it dominates the speed of Scalar multiplication. This paper presents an efficient implementation of finite field multiplication using a Vedic multiplier. The scalar multiplier is designed over Galois Binary field GF(2233) for field size=233-bit which is secured curve according to NIST. The performances of the proposed design are evaluated by comparing it with Karatsuba based scalar multiplier for area and delay. The results show that the proposed scalar multiplication using Vedic multiplier has consumed 22% less area on FPGA and also has 12% less delay, than Karatsuba, based scalar multiplier. The scalar multiplier is coded in Verilog HDL, synthesize and simulated in Xilinx 13.2 ISE on Virtex6 FPGA.