Finite Field Arithmetic Research Articles

Paving the Way for SQIsign: Toward Efficient Deployment on 32-bit Embedded Devices

The threat of quantum computing has spurred research into post-quantum cryptography. SQIsign, a candidate submitted to the standardization process of the National Institute of Standards and Technology, is emerging as a promising isogeny-based signature scheme. This work aimed to enhance SQIsign’s practical deployment by optimizing its low-level arithmetic operations. Through hierarchical decomposition and performance profiling, we identified the ideal-to-isogeny translation, primarily involving elliptic curve operations, as the main bottleneck. We developed efficient 32-bit finite field arithmetic for elliptic curves, such as basic operations, like addition with carry, subtraction with borrow, and conditional move. We then implemented arithmetic operations in the Montgomery domain, and extended these to quadratic field extensions. Our implementation offers improved compatibility with 32-bit architectures and enables more fine-grained SIMD acceleration. Performance evaluations demonstrated the practicality in low-level operations. Our work has potential in easing the development of SQIsign in practice, making SQIsign more efficient and practical for real-world post-quantum cryptographic applications.

New Compact Finite-Field Arithmetic Circuits Over GF(p) Based on Spiking Neural P Systems With Communication on Request Implemented in a Low-Cost FPGA

New Compact Finite-Field Arithmetic Circuits Over GF(p) Based on Spiking Neural P Systems With Communication on Request Implemented in a Low-Cost FPGA

Optimizations and Practicality of High-Security CSIDH

In this work, we assess the real-world practicality of CSIDH, an isogeny-based non-interactive key exchange. We provide the first thorough assessment of the practicality of CSIDH in higher parameter sizes for conservative estimates of quantum security, and with protection against physical attacks. This requires a three-fold analysis of CSIDH. First, we describe two approaches to efficient high-security CSIDH implementations, based on SQALE and CTIDH. Second, we optimize such high-security implementations, on a high level by improving several subroutines, and on a low level by improving the finite field arithmetic. Third, we benchmark the performance of high-security CSIDH. As a stand-alone primitive, our implementations outperform previous results by a factor up to 2.53×. As a real-world use case considering network protocols, we use CSIDH in TLS variants that allow early authentication through a NIKE. Although our instantiations of CSIDH have smaller communication requirements than post-quantum KEM and signature schemes, even our highly-optimized implementations result in too-large handshake latency (tens of seconds), showing that CSIDH is only practical in niche cases.

MiRitH: Efficient Post-Quantum Signatures from MinRank in the Head

Since 2016’s NIST call for standardization of post-quantum cryptographic primitives, developing efficient post-quantum secure digital signature schemes has become a highly active area of research. The difficulty in constructing such schemes is evidenced by NIST reopening the call in 2022 for digital signature schemes, because of missing diversity in existing proposals. In this work, we introduce the new postquantum digital signature scheme MiRitH. As direct successor of a scheme recently developed by Adj, Rivera-Zamarripa and Verbel (Africacrypt ’23), it is based on the hardness of the MinRank problem and follows the MPC-in-the-Head paradigm. We revisit the initial proposal, incorporate design-level improvements and provide more efficient parameter sets. We also provide the missing justification for the quantum security of all parameter sets following NIST metrics. In this context we design a novel Grover-amplified quantum search algorithm for solving the MinRank problem that outperforms a naive quantum brute-force search for the solution.MiRitH obtains signatures of size 5.7 kB for NIST category I security and therefore competes for the smallest signatures among any post-quantum signature following the MPCitH paradigm.At the same time MiRitH offers competitive signing and verification timings compared to the state of the art. To substantiate those claims we provide extensive implementations. This includes a reference implementation as well as optimized constant-time implementations for Intel processors (AVX2), and for the ARM (NEON) architecture. The speedup of our optimized AVX2 implementation relies mostly on a redesign of the finite field arithmetic, improving over existing implementations as well as an improved memory management.

Secure Groups for Threshold Cryptography and Number-Theoretic Multiparty Computation

In this paper, we introduce secure groups as a cryptographic scheme representing finite groups together with a range of operations, including the group operation, inversion, random sampling, and encoding/decoding maps. We construct secure groups from oblivious group representations combined with cryptographic protocols, implementing the operations securely. We present both generic and specific constructions, in the latter case specifically for number-theoretic groups commonly used in cryptography. These include Schnorr groups (with quadratic residues as a special case), Weierstrass and Edwards elliptic curve groups, and class groups of imaginary quadratic number fields. For concreteness, we develop our protocols in the setting of secure multiparty computation based on Shamir secret sharing over a finite field, abstracted away by formulating our solutions in terms of an arithmetic black box for secure finite field arithmetic or for secure integer arithmetic. Secure finite field arithmetic suffices for many groups, including Schnorr groups and elliptic curve groups. For class groups, we need secure integer arithmetic to implement Shanks’ classical algorithms for the composition of binary quadratic forms, which we will combine with our adaptation of a particular form reduction algorithm due to Agarwal and Frandsen. As a main result of independent interest, we also present an efficient protocol for the secure computation of the extended greatest common divisor. The protocol is based on Bernstein and Yang’s constant-time 2-adic algorithm, which we adapt to work purely over the integers. This yields a much better approach for multiparty computation but raises a new concern about the growth of the Bézout coefficients. By a careful analysis, we are able to prove that the Bézout coefficients in our protocol will never exceed 3max(a,b) in absolute value for inputs a and b. We have integrated secure groups in the Python package MPyC and have implemented threshold ElGamal and threshold DSA in terms of secure groups. We also mention how our results support verifiable multiparty computation, allowing parties to jointly create a publicly verifiable proof of correctness for the results accompanying the results of a secure computation.

Accelerating Finite Field Arithmetic for Homomorphic Encryption on GPUs

Fully Homomorphic Encryption (FHE) is a rapidly developing technology that enables computation directly on encrypted data, making it a compelling solution for security in cloud-based systems. In addition, modern FHE schemes are believed to be resistant to quantum attacks. Although FHE offers unprecedented potential for security, current implementations suffer from prohibitively high latency. Finite field arithmetic operations, particularly the multiplication of high-degree polynomials, are key computational bottlenecks. The parallel processing capabilities provided by modern Graphical Processing Units (GPUs) make them compelling candidates to target these highly parallelizable workloads. In this article, we discuss methods to accelerate polynomial multiplication with GPUs, with the goal of making FHE practical.

How to use a CAS for Hardware Design Automation

With the rise of new technologies, the demand for efficient cryptographic hardware is rising. This work is focusing on finite field based cryptography. To explore the vast design space obtained from possible finite field parameters, automated generation of hardware submodules using designer-specified algorithms for finite field arithmetic is needed. This work presents a hardware design automation framework exploiting symbolic computation capabilities of GAP to generate the expressions, needed for hardware implementations, on-the-fly, and compiles them into synthesizable datapaths, test-vectors, and testbences.

Topgun: An ECC Accelerator for Private Set Intersection

Elliptic Curve Cryptography (ECC), one of the most widely used asymmetric cryptographic algorithms, has been deployed in Transport Layer Security (TLS) protocol, blockchain, secure multiparty computation, and so on. As one of the most secure ECC curves, Curve25519 is employed by some secure protocols, such as TLS 1.3 and Diffie-Hellman Private Set Intersection (DH-PSI) protocol. High-performance implementation of ECC is required, especially for the DH-PSI protocol used in privacy-preserving platform. Point multiplication, the chief cryptographic primitive in ECC, is computationally expensive. To improve the performance of DH-PSI protocol, we propose Topgun, a novel and high-performance hardware architecture for point multiplication over Curve25519. The proposed architecture features a pipelined Finite-field Arithmetic Unit and a simple and highly efficient instruction set architecture. Compared to the best existing work on Xilinx Zynq 7000 series FPGA, our implementation with one Processing Element can achieve 3.14× speedup on the same device. To the best of our knowledge, our implementation appears to be the fastest among the state-of-the-art works. We also have implemented our architecture consisting of 4 Compute Groups, each with 16 PEs, on an Intel Agilex AGF027 FPGA. The measured performance of 4.48 Mops/s is achieved at the cost of 86 Watts power, which is the record-setting performance for point multiplication over Curve25519 on FPGAs.

Faster Montgomery multiplication and Multi-Scalar-Multiplication for SNARKs

The bottleneck in the proving algorithm of most of elliptic-curve-based SNARK proof systems is the Multi-Scalar-Multiplication (MSM) algorithm. In this paper we give an overview of a variant of the Pippenger MSM algorithm together with a set of optimizations tailored for curves that admit a twisted Edwards form. We prove that this is the case for SNARK-friendly chains and cycles of elliptic curves, which are useful for recursive constructions. Our contribution is twofold: first, we optimize the arithmetic of finite fields by improving on the well-known Coarsely Integrated Operand Scanning (CIOS) modular multiplication. This is a contribution of independent interest that applies to many different contexts. Second, we propose a new coordinate system for twisted Edwards curves tailored for the Pippenger MSM algorithm.Accelerating the MSM over these curves is critical for deployment of recursive proof< systems applications such as proof-carrying-data, blockchain rollups and blockchain light clients. We implement our work in Go and benchmark it on two different CPU architectures (x86 and arm64). We show that our implementation achieves a 40-47% speedup over the state-of-the-art implementation (which was implemented in Rust). This MSM implementation won the first place in the ZPrize competition in the open division “Accelerating MSM on Mobile” and will be deployed in two real-world applications: Linea zkEVM by ConsenSys and probably Celo network.

CryptOpt: Verified Compilation with Randomized Program Search for Cryptographic Primitives

Most software domains rely on compilers to translate high-level code to multiple different machine languages, with performance not too much worse than what developers would have the patience to write directly in assembly language. However, cryptography has been an exception, where many performance-critical routines have been written directly in assembly (sometimes through metaprogramming layers). Some past work has shown how to do formal verification of that assembly, and other work has shown how to generate C code automatically along with formal proof, but with consequent performance penalties vs. the best- known assembly. We present CryptOpt, the first compilation pipeline that specializes high-level cryptographic functional programs into assembly code significantly faster than what GCC or Clang produce, with mechanized proof (in Coq) whose final theorem statement mentions little beyond the input functional program and the operational semantics of x86-64 assembly. On the optimization side, we apply randomized search through the space of assembly programs, with repeated automatic benchmarking on target CPUs. On the formal-verification side, we connect to the Fiat Cryptography framework (which translates functional programs into C-like IR code) and extend it with a new formally verified program-equivalence checker, incorporating a modest subset of known features of SMT solvers and symbolic-execution engines. The overall prototype is quite practical, e.g. producing new fastest-known implementations of finite-field arithmetic for both Curve25519 (part of the TLS standard) and the Bitcoin elliptic curve secp256k1 for the Intel 12𝑡ℎ and 13𝑡ℎ generations.

MRNA Approach Image Encryption Using LUC Algorithm

Bioinformatics is one of the computer science and biology sub-subjects concerned with the processes applied to biological data, such as gathering, processing, storing, and analyzing it. Biological data (ribonucleic acid (RNA), deoxyribonucleic acid (DNA), and protein sequences) has many applications and uses in many fields (data security, data segmentation, feature extraction, etc.). DNA sequences are used in the cryptography field, using the properties of biomolecules as the carriers of the data. Messenger RNA (mRNA) is a single strand used to make proteins containing genetic information. The information recorded from DNA also carries messages from DNA to ribosomes in the cytosol. In this paper, a new encryption technique based on (mRNA) amino acids to increase the diffusion of the algorithm was proposed, also using the LUC algorithm with finite field arithmetic to increase the complexity of the algorithm. The results show high resistance against well-known attacks on the proposed method. For Entropy, the achieved value for the encrypted images was above 7.998. The range of peak signal to noise ratio (PSNR) between plain and encrypted images was below 8.7. Finally, the unified average change intensity (UACI) was close to 0.335. The number of changing pixel rates (NPCR) was close to 0.996, which is considered a good result.

Recent progress for five-particle two-loop scattering amplitudes with an off-shell leg

We report on the advances in the calculation of the two-loop scattering amplitudes for five-particle processes with one off-shell leg. Focusing on the production of a Higgs boson in association with a bottom quark pair, we outline how the newly developed technology allows us to overcome the computational bottlenecks. In particular, we discuss the use of finite field arithmetic and elucidate a convenient way to evaluate numerically the special functions appearing in the amplitudes.

Reliable Architectures for Finite Field Multipliers Using Cyclic Codes on FPGA Utilized in Classic and Post-Quantum Cryptography

Fault detection is becoming greatly important in protecting cryptographic designs that can suffer from both natural or malicious faults. Finite fields over <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text {GF}(2^{m})$ </tex-math></inline-formula> are widely used in such designs, since their data are coded in binary form for practical reasons. Among the different finite field arithmetic, multiplication is the bottleneck operation for many cryptosystems due to its complexity. Therefore, in this work, fault detection schemes based on cyclic codes for finite field multipliers using different fields found in traditional and post-quantum cryptography are derived. Moreover, we implement such schemes by embedding them into the original architectures to perform an exhaustive study, benchmark the different overheads obtained, and prove their suitability for deeply constrained embedded systems. These implementations are performed on advanced micro devices (AMD)/Xilinx field-programmable gate array (FPGA) and provide a very high error coverage with acceptable overhead.

Performance Comparison of Channel Coding Techniques for OFDM System

Wireless communication is one of the speedily evolving and dynamic technology areas in the realm of communication. OFDM is an acronym for Orthogonal Frequency Division Multiplexing. It is a version of FDM in which orthogonal subcarriers are closely spaced to maximize bandwidth consumption. By decreasing Inter Symbol Interference (ISI) and increasing the Signal-to-Noise ratio (SNR), it has enhanced the quality of long-distance communication. It’s commonly employed in digital communication systems to safeguard digital data from noise and interference while also reducing bit mistakes. Convolutional codes, Block codes, are the two fundamental forms of channel codes. Block codes are based on abstract algebra and finite field arithmetic. They are capable of detecting and correcting faults. This category includes LDPC and Reed Solomon codes. Convolution codes, alternatively are created using a distinct strong mathematical framework and are generally utilised for real-time error correction. They combine all of the data into a single codeword. Reed-Solomon codes are block-based error correcting codes used in digital communications, storage, and ADSL, among other uses. The BER performance of an OFDM system is investigated in this paper using various channel coding algorithms.

Design of Low Power Versatile Bit-Serial Multiplier in Finite Field GF (2m)

Finite field arithmetic is the most important component in applications like cryptography, computer algebra and error correcting codes. Versatility is an important property the hardware industry lacks and trying to establish as much as possible. To survive in this booming technological word, the new designs should be of an adjustable one, which processes the versatile property. In this we have proposed an efficient VLSI design for versatile bit-serial multiplier in finite fields GF (2m). The versatile multiplier designed here modifications done by reducing the unwanted switching activity removed by clock gating scheme. Our design provides a solution to the power reduction. The introduced multiplier operates over a variety of binary fields up to an order of 2m. The value of m can vary up to 264 bits. Multiplier is designed using Verilog HDL.

Two-loop leading colour helicity amplitudes for W±γ + j production at the LHC

We present the two-loop leading colour QCD helicity amplitudes for the process pp → W (→ lν)γ + j. We implement a complete reduction of the amplitudes, including the leptonic decay of the W-boson, using finite field arithmetic, and extract the analytic finite remainders using a recently identified basis of special functions. Simplified analytic expressions are obtained after considering permutations of a rational kinematic parametrisation and multivariate partial fractioning. We demonstrate efficient numerical evaluation of the two-loop colour and helicity summed finite remainders for physical kinematics, and hence the suitability for phenomenological applications.

An Optimized M-Term Karatsuba-Like Binary Polynomial Multiplier for Finite Field Arithmetic

Finite field multiplication is a fundamental and frequently used operation in various cryptographic circuits and systems. Because of its high complexity, this operation generally determines the overall complexity and cost of these systems. Therefore, finite field multipliers and their hardware implementation have received considerable attention from researchers. This article proposes a methodology to design an efficient Galois field multiplier. First, space and time complexities for theoretical and field-programmable gate array (FPGA) implementations of M-term Karatsuba-like finite field multipliers were obtained. In addition, an algorithm was developed to obtain an efficient design based on a composite M-term Karatsuba-like multiplier. Furthermore, the proposed multipliers were verified and implemented on various FPGA devices, and implementation results were presented. Reported device utilization and latency indicated that the proposed multiplier is roughly 26% faster and 15% more efficient in the area–delay product compared to the standard Karatsuba multiplier. Moreover, comparison with state of the art also indicated that the proposed design is leading in terms of effectiveness and speed.

Fast asymmetric encryption and decryption of SimpleMatrix scheme for Internet of Things

Asymmetric cryptography plays an essential role in many areas, including cloud computing, big data, blockchain, and the Internet of Things (IoT). However, most of them are based on the difficulty of factorizing large numbers or discrete logarithm problems, which are not secure to quantum computer attacks. SimpleMatrix is a new multivariate encryption scheme based on simple matrix multiplications, which can resist quantum computer attacks. Because of the low speed and demands of large finite fields, SimpleMatrix is limited in applications that use small finite fields. As a result, it is critical to improve the efficiency of SimpleMatrix to make its applications broader. In this paper, we speed up the encryption and decryption of SimpleMatrix by building efficient small finite field arithmetics based on Field-Programmable Gate Arrays (FPGAs) technology. We propose a fast architecture for encryption and decryption of SimpleMatrix based on table look-up based composite field multiplications and inversions and fast Gauss–Jordan elimination for solving systems of linear equations in a composite field. We test and verify the hardware architecture of SimpleMatrix on an FPGA, and the experimental results confirm our estimates and comparisons show that our design is much faster than other implementations. Thus, the hardware architecture can be used in FPGA-based systems of cloud computing, IoT, etc., for accelerating encryption and decryption.

Area efficient and high-speed Galois field multiplier for mobile edge computing devices

Mobile Edge Computing is one of the prominent technologies in 5G communication to improve throughput, scalability and reliability. In this work, area efficient and high-speed multipliers are implemented using finite field (Galois field) arithmetic which are widely utilised by edge computing devices. The performance of finite field multiplication operation is closely related to finite field elements representation. The proposed polynomial-based finite field bit parallel systolic array multiplier is able to achieve almost double the speed of existing multipliers. There is a considerable reduction in area and power for the proposed word-level normal basis finite field multiplier compared to the existing multipliers. The results clearly indicate that the proposed method improves the efficiency of finite field multipliers in terms of area, delay or power consumption. In order to process the real-time data efficiently, both the local computing and data offloading are carried out in developing a joint computation algorithm. The trade-off analysis between local computing and data offloading shows that local computing plays a more important role when the data size is small, but data offloading is preferred when the data size increases.

Supersingular Isogeny Key Encapsulation (SIKE) Round 2 on ARM Cortex-M4

We present the first practical software implementation of Supersingular Isogeny Key Encapsulation (SIKE) round 2, targeting NIST's 1, 2, 3, and 5 security levels on 32-bit ARM Cortex-M4 microcontrollers. The proposed library introduces a new speed record of all SIKE Round 2 protocols with reasonable memory consumption on the low-end target platform. We achieved this record by adopting several state-of-the-art engineering techniques as well as highly-optimized hand-crafted assembly implementation of finite field arithmetic. In particular, we carefully redesign the previous optimized implementations of finite field arithmetic on the 32-bit ARM Cortex-M4 platform and propose a set of novel techniques which are explicitly suitable for SIKE primes. The benchmark result on STM32F4 Discovery board equipped with 32-bit ARM Cortex-M4 microcontrollers shows that entire key encapsulation and decapsultation over SIKEp434 take about 184 million clock cycles (i.e., 1.09 seconds @168 MHz). In contrast to the previous optimized implementation of the isogeny-based key exchange on low-end 32-bit ARM Cortex-M4, our performance evaluation shows feasibility of using SIKE mechanism on the low-end platform. In comparison to the most of the post-quantum candidates, SIKE requires an excessive number of arithmetic operations, resulting in significantly slower timings. However, its small key size makes this scheme as a promising candidate on low-end microcontrollers in the quantum era by ensuring the lower energy consumption for key transmission than other schemes.